CN105427883A - Pre-reading method and programming method for three-dimensional NAND flash memory - Google Patents
Pre-reading method and programming method for three-dimensional NAND flash memory Download PDFInfo
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- CN105427883A CN105427883A CN201410454938.0A CN201410454938A CN105427883A CN 105427883 A CN105427883 A CN 105427883A CN 201410454938 A CN201410454938 A CN 201410454938A CN 105427883 A CN105427883 A CN 105427883A
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Abstract
The invention discloses a pre-reading method and a programming method for a three-dimensional NAND flash memory. The pre-reading method comprises the following steps: applying a first select voltage to one of multiple bit lines to select one of multiple layers; applying a second select voltage to one of multiple string select lines to select one of multiple strings in the selected layer, wherein the selected string comprises one first memory cell, two second memory cells and multiple third memory cells, the second memory cells are adjacent to the first memory cell, and the third memory cells are not adjacent to the first memory cell; and through multiple word lines, applying a first break-over voltage to the second memory cells, applying a second break-over voltage to the third memory cells, and applying a read voltage to the first memory cell to read data in the first memory cell, wherein the first break-over voltage is higher than the second break-over voltage.
Description
Technical field
The invention relates to a kind of pre-head method and wiring method, and relate to a kind of pre-head method for three-dimensional Sheffer stroke gate high-speed cache (3DNANDflashmemory) and wiring method especially.
Background technology
When the critical dimension reduction of device in integrated circuit is to the limit of common storage unit technology, deviser need find the technology of the multilevel storage unit of lamination to reach larger storage volume, and reaches every bit (bit) lower cost.
Therefore, develop low manufacturing cost three-dimensional structure integrated circuit memory, comprise the high and minimum memory element of fiduciary level and improve and the contiguous process window with the lamination of the storage unit of grid structure.
Summary of the invention
The invention relates to a kind of pre-head method for three-dimensional Sheffer stroke gate high-speed cache (3DNANDflashmemory) and wiring method, it performs pre-reader, to enable three-dimensional Sheffer stroke gate high-speed cache accurately writing data before being used in write-in program.
According to an aspect of the present invention, a kind of pre-head method for three-dimensional Sheffer stroke gate high-speed cache is proposed, pre-head method comprises the following steps: that applying one first selects voltage (selectvoltage) in one of them of several bit line (bitline), to select one of them of several layers; Applying one second selects voltage in one of them of several serial selection line (stringselectline), to select one of them of several serial in this layer selected; This serial selected comprises one first storage unit (memorycell), 2 second storage unit and several 3rd storage unit; This little second storage unit is adjacent to the first storage unit, and this little 3rd storage unit is non-conterminous in the first storage unit.Via several wordline (wordlines), apply one first forward voltage (passvoltage) and read voltage (readvoltage) in the first storage unit, to read data of the first storage unit in this little second storage unit, applying one second forward voltage in this little 3rd storage unit and applying one.First forward voltage is greater than the second forward voltage.
According to a further aspect in the invention, a kind of wiring method for three-dimensional Sheffer stroke gate high-speed cache is proposed, wiring method comprises the following steps: that applying one first selects voltage (selectvoltage) in one of them of several bit line (bitline), to select one of them of several layers; Applying one second selects voltage in one of them of several serial selection line (stringselectline), to select one of them of several serial in this layer selected; This serial selected comprises one first storage unit (memorycell), 2 second storage unit and several 3rd storage unit; This little second storage unit is adjacent to the first storage unit, and this little 3rd storage unit is non-conterminous in the first storage unit; Via several wordline (wordlines), apply one first forward voltage (passvoltage) and read voltage (readvoltage) in the first storage unit, to read data of the first storage unit in this little second storage unit, applying one second forward voltage in this little 3rd storage unit and applying one; First forward voltage is greater than the second forward voltage; Write the first storage unit.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating institute's accompanying drawings, being described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates a three-dimensional Sheffer stroke gate high-speed cache (3DNANDflashmemory).
Fig. 2 illustrates the schematic diagram of four kinds of states of multistage (multi-levelcell, MLC) Sheffer stroke gate high-speed cache.
Fig. 3 illustrates three-dimensional Sheffer stroke gate high-speed cache and to be interfered the situation of (interference).
Fig. 4 illustrates the process flow diagram of the wiring method of three-dimensional Sheffer stroke gate high-speed cache.
Fig. 5 illustrates the serial selected.
Fig. 6 illustrates two reading voltage curves of the first storage unit be interfered.
[symbol description]
100: three-dimensional Sheffer stroke gate high-speed cache
BL: bit line
C1, C2: read voltage curve
CSL: common source line
GSL: ground connection selects line
MC1: the first storage unit
MC2: the second storage unit
MC3: the three storage unit
S410, S411, S412, S413, S420: process step
SSL: serial selection line
W1, W2: window
WL: wordline
Embodiment
Please refer to Fig. 1, it illustrates a three-dimensional Sheffer stroke gate high-speed cache (3DNANDflashmemory) 100.Three-dimensional Sheffer stroke gate high-speed cache 100 can be energy gap engineering silicon-oxygen-nitrogen-oxygen-silicon (BE-SONOS) storer.Three-dimensional Sheffer stroke gate high-speed cache 100 comprises several bit line (bitlines) BL, several serial selection line (stringselectline) SSL, several ground connection selects line (groundselectline) GSL, several common source line (commonsourceline) CSL and several wordline (wordlines) WL.Each bit line BL is in order to select a certain layer.Each serial selection line SSL is in order to select a particular serial.
In Fig. 1, voltage (selectvoltage) can be selected in one of them of bit line BL by applying one first, select two layers wherein one.In one deck, voltage can be selected in one of them of serial selection line SSL by applying one second, select wherein one of four serials.In a serial, several storage unit (memorycell) can by applying one forward voltage and conducting, and a storage unit can read voltage by applying one and write voltage (programvoltage) to write to carry out reading or applies one.
Please refer to Fig. 2, it illustrates the schematic diagram of four kinds of states of multistage (multi-levelcell, MLC) Sheffer stroke gate high-speed cache.In multistage Sheffer stroke gate flash memory, four kinds of states can represent in low paging (l0wpage) and high paging (highpage).For example, if low paging position is " 0 " and high paging position is " 1 ", be then state " 10 ".If low paging position is " 1 " and high paging position is " 0 ", then it is state " 01 ".In write-in program, if multistage Sheffer stroke gate flash memory is positioned at state " 11 " and for being written to state " 10 ", then needs low paging position to be changed into " 0 " by " 1 ".If multistage Sheffer stroke gate flash memory is positioned at state " 11 " and for being written to state " 01 ", then needs high paging position to be changed into " 0 " by " 1 ".If multistage Sheffer stroke gate flash memory is positioned at state " 10 " and for being written to state " 00 ", then needs high paging position to be changed into " 0 " by " 1 ".That is, when writing multistage Sheffer stroke gate flash memory to NextState, the current state of multistage Sheffer stroke gate flash memory first correctly must be read.
Please refer to Fig. 3, it illustrates three-dimensional Sheffer stroke gate high-speed cache 100 and to be interfered the situation of (interference).In order to the gap reducing three-dimensional Sheffer stroke gate high-speed cache 100, first storage unit MC1 and two the second storage unit MC2 become less.The first storage unit MC1 between two the second storage unit MC2 may be subject to the interference of the second storage unit MC2.Therefore, the current state of the first storage unit MC1 possibly cannot correctly read.Thus, the first storage unit MC1 possibly correctly cannot write to NextState.
Therefore, before the write-in program carrying out three-dimensional Sheffer stroke gate high-speed cache 100, first must perform and pre-read (pre-reading) program accurately.Please refer to Fig. 4, it illustrates the process flow diagram of the wiring method of three-dimensional Sheffer stroke gate high-speed cache 100.Step S410 is a pre-head method.Step S410 and S420 is then a wiring method.Before step S410 is executed in step S420, correctly to read the current state for each storage unit of write in three-dimensional Sheffer stroke gate high-speed cache 100.
Step S410 comprises step S411, S412 and S413.In step S411, please refer to Fig. 1, apply first and select voltage in one of them of bit line BL, to select one of them of several layers.For example, first voltage is selected can be 3 volts (V).
In step S412, please refer to Fig. 1, apply one second and select voltage in one of them of several serial selection line SSL, to select one of them of several serial in this layer selected.For example, second voltage is selected can be 3 volts.
Please refer to Fig. 5, it illustrates the serial selected.The serial selected comprises the first storage unit MC1, two the second storage unit MC2 and several 3rd storage unit MC3.Second storage unit MC2 is adjacent to the first storage unit MC1, and the 3rd storage unit MC3 is non-conterminous in the first storage unit MC1.First storage unit MC1 may be subject to the interference of the second storage unit MC2.
In step S413, by wordline WL apply the first forward voltage (passvoltage) in the second storage unit MC2, apply the second forward voltage in the 3rd storage unit MC3 and apply read voltage in the first storage unit MC1, to read the data of the first storage unit MC1.First forward voltage is higher than the second forward voltage.
Please refer to Fig. 6, its two of illustrating the first storage unit MC1 be interfered read voltage curve C1, C2.In reading voltage curve C1, the first storage unit MC1 is positioned at state " 0 ", and in reading voltage curve C2, the first storage unit MC1 is positioned at state " 1 ".The second forward voltage putting on the 3rd storage unit MC3 is 6 volts.As shown in Figure 6, when the first forward voltage putting on the second storage unit MC2 brings up to 7 volts by 6 volts, read voltage curve C1 and will reduce by 133 millivolts (mV), and reading voltage curve C2 will reduce by 266 millivolts (mV).Read voltage curve C1 not identical with the reduction amplitude reading voltage curve C2.
That is, when the first forward voltage is greater than the second forward voltage, reads between voltage curve C1 and reading voltage curve C2 and form a window (window) W1.Window W1 can be positioned at state " 0 " or state " 1 " in order to identification first storage unit MC1.
Moreover, when the first forward voltage putting on the second storage unit MC2 is increased to 9 volts by 6 volts, reads voltage curve C1 and will reduce by 355 millivolts, and reading voltage curve C2 will reduce by 755 millivolts.That is, when the first forward voltage be greater than the second forward voltage more time, that reads that voltage curve C1 and the window W2 read between voltage curve C2 becomes is larger.Therefore the first storage unit MC1 is positioned at state " 0 " or state " 1 " and is more easily identified.
According to the explanation of Fig. 6, if the first forward voltage for be greater than the second forward voltage and be 7 ~ 9 volts time, even if the first storage unit MC1 is interfered, the current state of the first storage unit MC1 still can read exactly.
In one embodiment, step S410 can perform twice, to read the low paging position of the first storage unit MC1 and high paging position.
Then, in the step s 420, the write-in program of the first storage unit MC1 is carried out.Because pre-reader (i.e. step S410) first performs, the first storage unit MC1 can carry out write-in program exactly.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. pre-read (pre-reading) method, for a three-dimensional Sheffer stroke gate high-speed cache (3DNANDflashmemory), this pre-head method comprises:
Applying one first selects voltage (selectvoltage) in one of them of multiple bit line (bitline), to select one of them of multilayer;
Applying one second selects voltage in one of them of multiple serial selection line (stringselectline), to select one of them of multiple serial in this layer selected, this serial wherein selected comprises one first storage unit (memorycell), 2 second storage unit and multiple 3rd storage unit, these second storage unit are adjacent to this first storage unit, and these the 3rd storage unit are non-conterminous in this first storage unit; And
Via multiple wordline (wordlines), apply one first forward voltage (passvoltage) and read voltage (readvoltage) in this first storage unit in these second storage unit, applying one second forward voltage in these the 3rd storage unit and applying one, to read data of this first storage unit, wherein this first forward voltage is greater than this second forward voltage.
2. pre-head method according to claim 1, wherein this first forward voltage is 7 to 9 volts (V), and this first forward voltage is higher than this second forward voltage 3 volts.
3. pre-head method according to claim 1, wherein this first selection voltage is 3 volts, and this second selection voltage is 3 volts.
4. pre-head method according to claim 1, wherein this pre-head method be executed in programming this first storage unit step before.
5. pre-head method according to claim 1, wherein this three-dimensional Sheffer stroke gate high-speed cache is energy gap engineering silicon-oxygen-nitrogen-oxygen-silicon (BE-SONOS) storer.
6. write (programming) method, for a three-dimensional Sheffer stroke gate high-speed cache (3DNANDflashmemory), this wiring method comprises:
Applying one first selects voltage (firstselectvoltage) in one of them of multiple bit line (bitline), to select one of them of multilayer;
Applying one second selects voltage in one of them of multiple serial selection line (stringselectline), to select one of them of multiple serial in this layer selected, this serial wherein selected comprises one first storage unit (memorycell), 2 second storage unit and multiple 3rd storage unit, these second storage unit are adjacent to this first storage unit, and these the 3rd storage unit are non-conterminous in this first storage unit;
Via multiple wordline (wordlines), apply one first forward voltage (passvoltage) and read voltage (readvoltage) in this first storage unit in these second storage unit, applying one second forward voltage in these the 3rd storage unit and applying one, to read data of this first storage unit, wherein this first forward voltage is greater than this second forward voltage; And
Write this first storage unit.
7. wiring method according to claim 6, wherein this first forward voltage is 7 to 9 volts (V), and this first forward voltage is higher than this second forward voltage 3 volts.
8. wiring method according to claim 6, wherein this first selection voltage is 3 volts, and this second selection voltage is 3 volts.
9. wiring method according to claim 6, wherein apply this reading voltage with read the step of this first storage unit be executed in write this first storage unit step before.
10. wiring method according to claim 6, wherein this three-dimensional Sheffer stroke gate high-speed cache is energy gap engineering silicon-oxygen-nitrogen-oxygen-silicon (BE-SONOS) storer.
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Cited By (3)
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| CN109411002A (en) * | 2017-08-15 | 2019-03-01 | 华为技术有限公司 | A kind of method and flash controller of reading data |
| WO2021159223A1 (en) * | 2020-02-10 | 2021-08-19 | Yangtze Memory Technologies Co., Ltd. | Memory including plurality of portions and used for reducing program disturbance and program method thereof |
| US11195842B2 (en) | 2020-01-06 | 2021-12-07 | International Business Machines Corporation | Vertical non-volatile memory structure with additional bitline in wordline stack |
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| WO2012134098A2 (en) * | 2011-04-01 | 2012-10-04 | (주)아토솔루션 | Memory and memory-reading method |
| CN103514952A (en) * | 2012-06-20 | 2014-01-15 | 旺宏电子股份有限公司 | NAND flash and biasing method therefor |
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| WO2012134098A2 (en) * | 2011-04-01 | 2012-10-04 | (주)아토솔루션 | Memory and memory-reading method |
| CN103514952A (en) * | 2012-06-20 | 2014-01-15 | 旺宏电子股份有限公司 | NAND flash and biasing method therefor |
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Cited By (4)
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| CN109411002A (en) * | 2017-08-15 | 2019-03-01 | 华为技术有限公司 | A kind of method and flash controller of reading data |
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| US11195842B2 (en) | 2020-01-06 | 2021-12-07 | International Business Machines Corporation | Vertical non-volatile memory structure with additional bitline in wordline stack |
| WO2021159223A1 (en) * | 2020-02-10 | 2021-08-19 | Yangtze Memory Technologies Co., Ltd. | Memory including plurality of portions and used for reducing program disturbance and program method thereof |
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