CN105427883B - Pre-head method and wiring method for three-dimensional NAND gate cache - Google Patents
Pre-head method and wiring method for three-dimensional NAND gate cache Download PDFInfo
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- CN105427883B CN105427883B CN201410454938.0A CN201410454938A CN105427883B CN 105427883 B CN105427883 B CN 105427883B CN 201410454938 A CN201410454938 A CN 201410454938A CN 105427883 B CN105427883 B CN 105427883B
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Abstract
The invention discloses a kind of pre-head methods and wiring method being used for a three-dimensional NAND gate cache.Pre-head method includes the following steps：Apply first choice voltage in one of several bit lines, to select one of several layers；Apply the second selection voltage in one of several serial selection lines, to select several serial wherein one in this layer selected；What is selected includes serially one first storage unit, 2 second storage units and several third storage units；Second storage unit is adjacent to the first storage unit, and third storage unit is non-conterminous in the first storage unit；Via several wordline, applies the first conducting voltage and read voltage in the first storage unit, to read the data of the first storage unit in these third storage units and application in these second storage units, the second conducting voltage of application.First conducting voltage is more than the second conducting voltage.
Description
Technical field
The invention relates to a kind of pre-head method and wiring methods, and in particular to one kind for three-dimensional NAND gate
The pre-head method and wiring method of cache (3D NAND flash memory).
Background technology
When the limit of the critical dimension reduction of device in integrated circuit to common storage unit technology, designer needs to find
The technology of the multilevel storage unit of lamination reaches every bit (bit) lower cost to reach larger storage volume.
Therefore, low manufacturing cost three-dimensional structure integrated circuit memory, including reliability height and minimum storage are developed
Element and the processing window of improvement and the lamination of the neighbouring storage unit with gate structure.
Invention content
The invention relates to a kind of pre-reading for three-dimensional NAND gate cache (3D NAND flash memory)
Method and wiring method execute pre- reader before being used in write-in program, so that three-dimensional NAND gate cache can be correct
Data are written.
According to an aspect of the invention, it is proposed that a kind of pre-head method for three-dimensional NAND gate cache, pre-head method
Include the following steps：Apply a first choice voltage (select voltage) in several bit lines (bit line) wherein it
One, to select one of several layers；Apply one second selection voltage in several serial selection lines (string select
Line one of), several one of serial to be selected in the layer selected；This selected is serial including one
First storage unit (memory cell), 2 second storage units and several third storage units；These second storage unit phases
Adjacent to the first storage unit, and these third storage units are non-conterminous in the first storage unit.Via several wordline (word
Lines), apply one first conducting voltage (pass voltage) in these second storage units, one second conducting voltage of application
In these third storage units and apply a reading voltage (read voltage) in the first storage unit, is deposited with reading first
One data of storage unit.First conducting voltage is more than the second conducting voltage.
According to another aspect of the invention, it is proposed that a kind of wiring method for three-dimensional NAND gate cache, write-in side
Method includes the following steps：Apply a first choice voltage (select voltage) in several bit lines (bit line) wherein it
One, to select one of several layers；Apply one second selection voltage in several serial selection lines (string select
Line one of), several one of serial to be selected in the layer selected；This selected is serial including one
First storage unit (memory cell), 2 second storage units and several third storage units；These second storage unit phases
Adjacent to the first storage unit, and these third storage units are non-conterminous in the first storage unit；Via several wordline (word
Lines), apply one first conducting voltage (pass voltage) in these second storage units, one second conducting voltage of application
In these third storage units and apply a reading voltage (read voltage) in the first storage unit, is deposited with reading first
One data of storage unit；First conducting voltage is more than the second conducting voltage；The first storage unit is written.
More preferably understand in order to which the above-mentioned and other aspect to the present invention has, preferred embodiment cited below particularly, and coordinates institute
Accompanying drawings are described in detail below：
Description of the drawings
Fig. 1 is painted a three-dimensional NAND gate cache (3D NAND flash memory).
Fig. 2 is painted the schematic diagram of four kinds of states of multistage (multi-level cell, MLC) NAND gate cache.
Fig. 3 be painted three-dimensional NAND gate cache be interfered (interference) the case where.
Fig. 4 is painted the flow chart of the wiring method of three-dimensional NAND gate cache.
Fig. 5 be painted selected it is serial.
Fig. 6 is painted two reading voltage curves of the first storage unit being interfered.
【Symbol description】
100：Three-dimensional NAND gate cache
BL：Bit line
C1、C2：Read voltage curve
CSL：Common source line
GSL：It is grounded selection line
MC1：First storage unit
MC2：Second storage unit
MC3：Third storage unit
S410、S411、S412、S413、S420：Process step
SSL：Serial selection line
W1、W2：Window
WL：Wordline
Specific implementation mode
Referring to FIG. 1, it is painted a three-dimensional NAND gate cache (3D NAND flash memory) 100.It is three-dimensional with
NOT gate cache 100 can be energy gap engineering silicon-oxygen-nitrogen-oxygen-silicon (BE-SONOS) memory.Three-dimensional NAND gate high speed
Caching 100 includes several bit lines (bit lines) BL, several serial selection lines (string select line) SSL, Shuo Gejie
Ground selection line (ground select line) GSL, several common source lines (common source line) CSL and several words
Line (word lines) WL.Each bit line BL is selecting a certain layer.Each serial selection line SSL is selecting a specific string
Row.
In Fig. 1, can by applying a first choice voltage (select voltage) in one of bit line BL,
To select wherein the one of two layers.In one layer, can by apply one second selection voltage in serial selection line SSL wherein it
One, to select four serial wherein one.In one is serial, several storage units (memory cell) can be by applying one
Conducting voltage and be connected, a storage unit can by apply one read voltage to be read out or apply a write-in voltage
(program voltage) is to be written.
Fig. 2 is please referred to, four kinds of states of multistage (multi-level cell, MLC) NAND gate cache are painted
Schematic diagram.In multistage NAND gate flash memory, four kinds of states can carry out table with low paging (l0w page) and high paging (high page)
Show.For example, if low paging position is " 0 " and high paging position is " 1 ", for state " 10 ".If low paging position is " 1 " and high score
Page position is " 0 ", then is state " 01 ".In write-in program, if multistage NAND gate flash memory is located at state " 11 " and shape to be written to
State " 10 " then needs by " 1 " to change into low paging position " 0 ".If multistage NAND gate flash memory is located at state " 11 " and is intended to be written to
State " 01 " then needs by " 1 " to change into high paging position " 0 ".If multistage NAND gate flash memory is located at state " 10 " and is intended to be written to
State " 00 " then needs by " 1 " to change into high paging position " 0 ".That is, multistage NAND gate flash memory is written to NextState
When, it is necessary to first correctly read the current state of multistage NAND gate flash memory.
Please refer to Fig. 3, be painted three-dimensional NAND gate cache 100 be interfered (interference) the case where.For
Three-dimensional NAND gate cache 100 is reduced, the gap change of the first storage unit MC1 and two second storage unit MC2 is more
It is small.The first storage unit MC1 between two the second storage unit MC2 may be done by the second storage unit MC2
It disturbs.Therefore, the current state of the first storage unit MC1 possibly can not correctly be read.Thus, which the first storage unit MC1 can
It can not be correctly written in NextState.
Therefore, before the write-in program for carrying out three-dimensional NAND gate cache 100, it is necessary to first carry out and accurately pre-read
(pre-reading) program.Fig. 4 is please referred to, the flow chart of the wiring method of three-dimensional NAND gate cache 100 is painted.Step
Rapid S410 is a pre-head method.Step S410 and S420 are then a wiring method.Before step S410 is implemented in step S420, with just
Really read the current state of each storage unit to be written in three-dimensional NAND gate cache 100.
Step S410 includes step S411, S412 and S413.In step S411, Fig. 1 is please referred to, applies first choice electricity
It is pressed on one of bit line BL, to select one of several layers.For example, first choice voltage can be 3 volts
(V)。
In step S412, please refer to Fig. 1, apply one second selection voltage in several serial selection line SSL wherein it
One, it is several one of serial to be selected in the layer selected.For example, the second selection voltage can be 3 volts.
Please refer to Fig. 5, be painted selected it is serial.Selected include serially the first storage unit MC1, two second
Storage unit MC2 and several third storage unit MC3.Second storage unit MC2 is deposited adjacent to the first storage unit MC1, third
Storage unit MC3 is non-conterminous in the first storage unit MC1.First storage unit MC1 may be done by the second storage unit MC2
It disturbs.
In step S413, the first conducting voltage (pass voltage) is applied in the second storage unit by wordline WL
MC2, apply the second conducting voltage in third storage unit MC3 and apply reading voltage in the first storage unit MC1, to read
The data of first storage unit MC1.First conducting voltage is higher than the second conducting voltage.
Fig. 6 is please referred to, be painted the first storage unit MC1 being interfered two read voltage curve C1, C2.It is reading
It taking in voltage curve C1, the first storage unit MC1 is located at state " 0 ", in reading voltage curve C2, the first storage unit MC1
Positioned at state " 1 ".The second conducting voltage for being applied to third storage unit MC3 is 6 volts.As shown in fig. 6, when being applied to second
When the first conducting voltage of storage unit MC2 is increased to 7 volts by 6 volts, will be reduced by reading voltage curve C1 by 133 millivolts
(mV), and reading voltage curve C2 will be reduced by 266 millivolts (mV).It reads voltage curve C1 and reads the reduction of voltage curve C2
Amplitude simultaneously differs.
That is, when the first conducting voltage is more than the second conducting voltage, reads voltage curve C1 and read voltage song
A window (window) W1 is formed between line C2.Window W1 can be located at state " 0 " or shape to recognize the first storage unit MC1
State " 1 ".
Furthermore when the first conducting voltage for being applied to the second storage unit MC2 increases to 9 volts by 6 volts, electricity is read
The line C1 that buckles will reduce by 355 millivolts, and reading voltage curve C2 will reduce by 755 millivolts.That is, when the first electric conduction
When pressure is more more than the second conducting voltage, reads voltage curve C1 and read the bigger that the window W2 between voltage curve C2 becomes.
Therefore the first storage unit MC1 is located at state " 0 " or state " 1 " is easier to be identified out.
According to the explanation of Fig. 6, if the first conducting voltage is is 7~9 volts more than the second conducting voltage, even if first
Storage unit MC1 is interfered, and the current state of the first storage unit MC1 can be still accurately read.
In one embodiment, step S410 can be executed twice, to read low paging position and the height of the first storage unit MC1
Paging position.
Then, in the step s 420, the write-in program of the first storage unit MC1 is carried out.Due to pre- reader (i.e. step
S410 it) has first carried out, the first storage unit MC1 can accurately carry out write-in program.
In conclusion although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (10)
1. one kind pre-reading (pre-reading) method, for a three-dimensional NAND gate cache (3D NAND flash
Memory), which includes：
Apply a first choice voltage (select voltage) in one of multiple bit lines (bit line), it is more to select
One of layer；
Apply one second selection voltage in one of multiple serial selection lines (string select line), in having selected
Selected in the layer selected it is multiple one of serial, wherein this selected includes serially one first storage unit (memory
Cell), 2 second storage units and multiple third storage units, these second storage units adjacent to first storage unit,
And these third storage units are non-conterminous in first storage unit；And
Via multiple wordline (word lines), it is single in these second storages to apply one first conducting voltage (pass voltage)
Member, apply one second conducting voltage in these third storage units and apply one read voltage (read voltage) in this
One storage unit, to read a data of first storage unit, wherein first conducting voltage is more than second conducting voltage.
2. pre-head method according to claim 1, wherein first conducting voltage are 7 to 9 volts (V), first conducting
Voltage is 3 volts higher than second conducting voltage.
3. pre-head method according to claim 1, wherein the first choice voltage are 3 volts, this second selects voltage for 3
Volt.
4. pre-head method according to claim 1, the wherein pre-head method, which are implemented in, programs first storage unit
Before step.
5. pre-head method according to claim 1, wherein the three-dimensional NAND gate cache are an energy gap engineering silicon-oxygen-
Nitrogen-oxygen-silicon (BE-SONOS) memory.
6. a kind of write-in (programming) method, for a three-dimensional NAND gate cache (3D NAND flash
Memory), which includes：
Apply a first choice voltage (first select voltage) in one of multiple bit lines (bit line), with
Select one of multilayer；
Apply one second selection voltage in one of multiple serial selection lines (string select line), in having selected
Selected in the layer selected it is multiple one of serial, wherein this selected includes serially one first storage unit (memory
Cell), 2 second storage units and multiple third storage units, these second storage units adjacent to first storage unit,
And these third storage units are non-conterminous in first storage unit；
Via multiple wordline (word lines), it is single in these second storages to apply one first conducting voltage (pass voltage)
Member, apply one second conducting voltage in these third storage units and apply one read voltage (read voltage) in this
One storage unit, to read a data of first storage unit, wherein first conducting voltage is more than second conducting voltage；
And
First storage unit is written.
7. wiring method according to claim 6, wherein first conducting voltage are 7 to 9 volts (V), first conducting
Voltage is 3 volts higher than second conducting voltage.
8. wiring method according to claim 6, wherein the first choice voltage are 3 volts, this second selects voltage for 3
Volt.
9. wiring method according to claim 6, wherein applying the step of the reading voltage to read first storage unit
Suddenly it is before being implemented in the step of first storage unit is written.
10. wiring method according to claim 6, wherein the three-dimensional NAND gate cache are an energy gap engineering silicon-oxygen-
Nitrogen-oxygen-silicon (BE-SONOS) memory.
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| CN201410454938.0A CN105427883B (en) | 2014-09-09 | 2014-09-09 | Pre-head method and wiring method for three-dimensional NAND gate cache |
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| CN105427883B true CN105427883B (en) | 2018-09-14 |
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| CN109411002B (en) * | 2017-08-15 | 2021-01-29 | 华为技术有限公司 | Data reading method and flash memory controller |
| US11195842B2 (en) | 2020-01-06 | 2021-12-07 | International Business Machines Corporation | Vertical non-volatile memory structure with additional bitline in wordline stack |
| KR20220019052A (en) * | 2020-02-10 | 2022-02-15 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | A memory comprising a plurality of parts and used to reduce program interruption and a program method therefor |
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| CN102163457A (en) * | 2010-02-18 | 2011-08-24 | 三星电子株式会社 | Nonvolatile memory device, programming method thereof and memory system including the same |
| WO2012134098A2 (en) * | 2011-04-01 | 2012-10-04 | (주)아토솔루션 | Memory and memory-reading method |
| CN103514952A (en) * | 2012-06-20 | 2014-01-15 | 旺宏电子股份有限公司 | NAND flash and biasing method therefor |
| CN103928042A (en) * | 2013-01-16 | 2014-07-16 | 旺宏电子股份有限公司 | Programming Multibit Memory Cells |
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Patent Citations (4)
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| CN102163457A (en) * | 2010-02-18 | 2011-08-24 | 三星电子株式会社 | Nonvolatile memory device, programming method thereof and memory system including the same |
| WO2012134098A2 (en) * | 2011-04-01 | 2012-10-04 | (주)아토솔루션 | Memory and memory-reading method |
| CN103514952A (en) * | 2012-06-20 | 2014-01-15 | 旺宏电子股份有限公司 | NAND flash and biasing method therefor |
| CN103928042A (en) * | 2013-01-16 | 2014-07-16 | 旺宏电子股份有限公司 | Programming Multibit Memory Cells |
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