CN105518859B - Use the low package parasitic inductance of threading mediator - Google Patents

Abstract

A kind of mediator for chipset, including being included in plural layers capacitor therein to reduce the parasitic inductance in the chipset.Power terminal and ground terminal are laid out with the pattern being staggered to eliminate the magnetic field between conductive through hole, to reduce equivalent series inductance (ESL).

Description

Use the low package parasitic inductance of threading mediator

Open field

All aspects of this disclosure relate generally to semiconductor packages, and more particularly to low parasitic inductance and equivalent series The semiconductor packages of inductance.

Background technique

Integrated circuit (IC) is fabricated on chip.In general, these chips are semiconductor material (for example, silicon).By grinding Study carefully and development effort, the size for constituting the transistor of IC is reduced, and the voltage of these transistors is therefore supplied to also to subtract It is small.

IC is commonly coupled to the voltage-stablizer of a part as the power delivery network for the IC.Voltage-stablizer is by power supply Voltage is converted into lower voltage used in IC.Voltage-stablizer ensures that predictable power supply is provided to IC.

However, the load on power supply rapidly changes, this is proposed to voltage-stablizer with the transistor turns and cut-off of IC Added requirement.The distance between voltage-stablizer and IC result in long response time, so that preventing voltage-stablizer immediately is that IC increases function Rate, especially when transistor on and off per second is millions of or billions of secondary.Decoupling capacitors are the power for being supplied to IC Additional stability is provided.

The decoupling capacitors set up close to IC provide instant electric current for IC.As the demand to power supply quickly changes, the electricity Container provides additional power and can recharge in later time when power demand reduces.Decoupling capacitors allow IC is operated with the desired high frequency of consumer and calculating speed.However, as transistor size reduction and transistor are close Degree increases, and finding on IC becomes difficult for the area of decoupling capacitors.

Decoupling capacitors are directly placed on IC tube core by a configuration of decoupling IC.However, decoupling capacitors are direct It is placed on the die area for occupying on IC tube core and can be used for efficient circuit system originally.Additionally, decoupling capacitors are manufactured It is related to additional manufacturing time on tube core, which increase manufacturing costs.

As an example, conventional decoupling capacitors used in IC are thin film capacitors.Thin film capacitor can made It is fabricated on chip during making with additional cost.These capacitors are usually the alternating layer that dielectric material is followed by conductor. Although thin film capacitor is simple structure, capacitor is largely determined by series capacitance number in parallel.However, with More capacitors be added, the height of thin film capacitor structure increases.

Metal-insulator-metal type (MIM) capacitor, which can be manufactured into, meets height more smaller than thin film capacitor about Beam.It highly may be important consideration factor when encapsulating these capacitors.In addition, MIM capacitor delivers net in design power Flexibilities more more than thin film capacitor are provided in equivalent series inductance (ESL) and equivalent series resistance (ESR) in network.

As encapsulation is reduced in size to meet the relatively small form factor presented in mobile device, available sky in encapsulation Between reduce.Additionally, because circuit it requires higher capacitor to ensure circuit system and crystal with higher frequencies of operation The appropriate operation of pipe.

For example, they are influenced by the total characteristic impedance of power delivery network because IC is with higher frequencies of operation. Total characteristic impedance is by the inductance (that is, parasitic inductance) of the trace in decoupling capacitors and the equivalent series electricity of decoupling capacitors Feel the influence of (ESL).Parasitic inductance in traditional IC arrangement can be up to 100pH or more, and the equivalent string of decoupling capacitors Connection inductance can be up to 400pH or more.

Routinely arrange a problem for semiconductor packages is the impedance sensitivity of power delivery network by being subjected to Total inductance influence.For example, in 100 megahertzs of frequency caused by the total inductance being subjected to there are power delivery network The strong resonance peak of surrounding.When the transistor in IC starts switching, power delivery network is needed to supply electric current.Because of the electricity Stream flows through the impedance of power delivery network, so supply voltage Possible waves, so that damage is supplied to the stability of the power of IC. The operation that injured stability will lead to IC degrades.

Thus, it is desirable to the improved device and method for reducing the total characteristic impedance in semiconductor packages.

It summarizes

For example, each example embodiment of the invention be related to by the device of the mediator in chipset, system, method and based on Calculation machine readable medium.The mediator includes being included in plural layers capacitor therein to reduce the parasitic inductance in chipset. Power terminal and ground terminal are arranged with the pattern being staggered to eliminate the magnetic field between conductive through hole, to reduce equivalent series Inductance (ESL).

In one or more implementations, which includes multiple power terminals by being arranged with the pattern being staggered and ground connection Multiple plural layers capacitors that terminal is formed.The mediator further includes that the pattern for being configured to for this being staggered is coupled in first group of touching Multiple conductive through holes between point and second group of contact, wherein first group of contact has the spacing less than second group of contact.This is more A plural layers capacitor is disposed between first group of contact and multiple conductive through hole.

The mediator may include more than second a plural layers being formed between multiple conductive through hole and second group of contact Capacitor.Multiple plural layers capacitor can be formed with metal-insulator-metal type (MIM) configuration.Multiple plural layers Capacitor may include multiple trench capacitors.The mediator, which can be, wears glass through-hole (TGV) mediator.The mediator, which can be, to be worn Through silicon via (TSV) mediator.The mediator can be ceramic mediator.The mediator can be organic mediator.It is multiple more Layer film capacitor may include multiple trench capacitors.

In one or more implementations, a kind of system includes the mediator with the first side and second side.The mediator packet Include the multiple plural layers capacitors formed by the multiple power terminals and ground terminal with the pattern arrangement being staggered.The mediator It further include multiple conductive through holes that the pattern for being configured to for this being staggered is coupled between first group of contact and second group of contact.This is System further includes the tube core being arranged on mediator.

First group of contact can have the spacing smaller than second group of contact.Multiple plural layers capacitor is disposed in Between one group of contact and multiple conductive through hole.The system may also include be formed in multiple conductive through hole and second group of contact it Between more than second a plural layers capacitors.Multiple plural layers capacitor can be matched with metal-insulator-metal type (MIM) It sets to be formed.Multiple plural layers capacitor may include multiple trench capacitors.The tube core can be trigger.The system can be into One step includes the substrate being arranged in second side of mediator.The pattern being staggered can be the figure being staggered line by line and/or by column At least one of case.

In one or more implementations, a kind of method making mediator includes providing multiple power ends with the pattern being staggered Son and ground terminal.This method further includes that multiple conductive through holes are coupled to multiple power terminal and ground terminal is more to be formed A plural layers capacitor.This method further comprises that the pattern that this is staggered and multiple conductive through hole are coupled in first group Between contact and second group of contact.

First group of contact can have the spacing smaller than second group of contact.Multiple plural layers capacitor can use gold Category-insulator-metal (MIM) configuration is formed.The pattern being staggered can be the pattern being staggered line by line and/or by column.It is multiple Plural layers capacitor may include multiple trench capacitors.Multiple conductive through hole, which can be, to be worn glass through-hole (TGV) and/or wears silicon Through-hole (TSV).Forming multiple conductive through hole can be executed with ceramic material, organic material, glass material and/or silicon.

In one or more implementations, a kind of computer readable storage medium includes data, which accesses by machine When make machine execute as described in this article production mediator method.The computer readable storage medium can be non-transient 's.

Brief description

Attached drawing is provided to help that the embodiment of the present invention is described, and provide attached drawing be only used for explain embodiment rather than it is right It is defined.

Figure 1A is that the section of conventional IC package indicates.

Figure 1B is the schematic diagram of the simulation lumped circuit model of discribed IC package in Figure 1A.

Fig. 1 C is the resistance according to one or more power delivery network impedance simulations realized of techniques described herein The graphical representation of anti-curve.

Fig. 2 shows the section tables for the integrated circuits (IC) realized according to the one or more of techniques described herein Show.

Fig. 3, which is illustrated, to scheme according to what the one or more of techniques described herein was realized with the power being staggered and ground connection The top view of the mediator of case.

Fig. 4 is shown according to the realization of one or more metal-insulator-metal types (MIM) of techniques described herein The section of mediator with the power and grounding pattern that are staggered indicates.

Fig. 5 is shown according to the realization of one or more metal-insulator-metal types (MIM) of techniques described herein The section of two layers of mediator indicates.

Fig. 6 is shown according to the realization of one or more metal-insulator-metal types (MIM) of techniques described herein The section of multilayer mediator indicates.

Fig. 7 is shown to be indicated according to the section of one or more mediators realized of techniques described herein.

Fig. 8 is the flow chart explained according to the method described herein for realizing production mediator.

Detailed description

In general, a realization of presently disclosed subject matter content is related to for reducing the parasitism in semiconductor packages System, the method and apparatus of inductance and equivalent series inductance (ESL).Figure 1A is that the section of conventional IC package 100 indicates.It is explained IC package 100 include the tube core 102 that package substrate 104 is installed to using first group of contact 106.Printed circuit board (PCB) 108 Package substrate 104 is installed to using second group of contact 110.Bulk capacitor 112 is mounted to PCB 108.Decoupling capacitors 114 are embedding Enter in package substrate 104.Tube core 102, package substrate 104 and PCB 108 are coupled using a series of through-holes 116.Art Both language " contact " and " through-hole " can refer to conductor/trace structure for being electrically connected in different interconnection levels.

Figure 1B is the schematic diagram of the simulation lumped circuit model 120 of IC package 100.The lumped circuit model 120 explained Tube core 102 is shown to employ multiple resistance, capacitor, the movement for being inductively coupled to power management IC (PMIC) 122 and current source It stands modem (MSM) core.MSM core 102 is shown as with capacitor and resistance by model 120.Model 120 is by package substrate 104 It is shown as with resistance and inductance.Package substrate 104 is also shown as the trace with decoupling capacitors 114 and trace by model 120 Inductance 116.PMIC 122 is shown as with inductance and resistance by model 120.Model 120 further illustrates bulk capacitor 122, even With resistance, capacitor and the inductance of the various other modelings being coupled between package substrate 104 and PMIC 122.

Fig. 1 C is the impedance according to the simulation of one or more power delivery networks realized of techniques described herein The graphical representation of curve 150.The frequency response of power delivery network is plotted on the x-axis by the impedance curve 150 explained, relatively Ground is by the impedance (Z of power delivery network (PDN)_PDN) mark and draw on the y axis.Net is delivered from tube core 102 to 122 simulated power of PMIC Impedance (the Z of network_PDN), including the capacitor from bulk capacitor 102, the capacitor from decoupling capacitors 114 and come from trace Trace inductance 116.

The impedance curve 150 explained includes strong resonance peak 152, can be the trace due to decoupling capacitors 114 Inductance (that is, parasitic inductance) combines caused with the equivalent series inductance (ESL) of decoupling capacitors 114.Typically, this is humorous The peak value that shakes occurs near 100 megahertzs.

In one or more implementations, system, method and apparatus reduce parasitic inductance and equivalent series inductance (ESL).Knot Fruit is that resonance peak 152 is lowered to the level for being equivalent to resonance peak 154.

Fig. 2 shows the section expressions for the systems 200 realized according to the one or more of techniques described herein, wherein Resonance peak 152 can be lowered to resonance peak 154.The system 200 explained in Fig. 2 depicts the core including tube core 202 Piece group is disposed on mediator 204.Mediator 204 is disposed on printed circuit board (PCB) 206.Tube core 202 includes multiple Power terminal (VDD) and ground terminal (GND).In one or more implementations, tube core 202 is trigger application processor.When So, tube core 202 can be any suitable functional semiconductor block.

In one or more implementations, glass through-hole (TGV) technology and/or silicon through hole (TSV) skill are worn in 204 use of mediator Art is realized.In one or more implementations, mediator 204 is ceramic mediator, glass mediator, silicon mediator and/or has Machine mediator.

Mediator 204 includes multiple metal wires and/or trace 208,210,212 and 213.208 He of metal wire and/or trace 210 are respectively coupled to multiple power terminal 214A and 214B.Metal wire and/or trace 212 and 213 are respectively coupled to ground terminal 216A and 216B.Pattern arrangement of the power terminal 214A and 214B and ground terminal 216A and 216B to be staggered.What this was staggered Pattern can be line by line, it is by column or such.By power terminal 214A and 214B and ground terminal 216A and 216B shape At multiple plural layers capacitors.Pattern cloth of the power terminal 214A and 214B and ground terminal 216A and 216B to be staggered It sets.Thus metal wire and/or trace 208,210,212 and 213 are also arranged by the pattern being staggered.The pattern being staggered eliminates often The magnetic field between metal wire and/or trace can be present in the case of rule.The pattern being staggered can be line by line, by column or such as It is such.

Mediator 204 further includes being configured to that the more of mediator 204 and substrate 206 will be coupled to from the signal of tube core 202 A terminal 218A and 218B.Mediator 204 further includes that the power terminal for being configured to the pattern that will be staggered and ground terminal are coupled in Multiple conductive through hole 220A, 220B, 220C and 220D between first group of contact 222 and second group of contact 224.

In one implementation, it can be configured on the side and/or two sides of mediator with metal-insulator-metal type (MIM) Form plural layers capacitor.In this implementation, plural layers capacitor can be trench capacitor.

MIM configuration in metal wire can be aluminium (Al), copper (Cu), Al and Cu alloy or provide for couple or Interconnect other suitable conductors of the signal path of electric circuit.Certainly, in the situation of non-MIM configuration, than metal Conductor be suitable.The materials such as DOPOS doped polycrystalline silicon, doped monocrystalline silicon, titanium (Ti), molybdenum (Mo) and refractory metal silicon compound Material is the example of other conductors.

First group of contact 222 is arranged on the ball grid array (BGA) of the first side of mediator 204.Second group of contact 224 It is arranged on the BGA of second side of mediator 204.BGA includes multiple solder projections.

First group of contact 222 has the spacing smaller than second group of contact 224.For example, first group of contact 222 can have 100 microns of spacing, and second group of contact 224 can have 400 microns of spacing.By this method, mediator 204 can be used as from touching Send out the contact device BGA 222 100 microns of spacing to the contact BGA 224 400 microns of spacing space convertor.

In one or more implementations, it is formed by power terminal 214A and 214B and ground terminal 216A and 216B more Peak value 152 on impedance curve 150 is reduced to peak value 154 by layer film capacitor.This be by by plural layers capacitor with Mediator combination is completed with shortening the power cycle from tube core to PMIC.That is, in being combined with plural layers capacitor Mediator substantially eliminates slave flipflop convex block to the trace inductance (or parasitic inductance) of electrode for capacitors (or through-hole).

Recalling conventional decoupling capacitors has the magnetic field generated between its electrode.This is because function under normal conditions Rate terminal and ground terminal are laid out with checkerboard pattern.The unconventional chess with the novel pattern being staggered line by line and/or by column Disk pattern reduces the equivalent of the mediator according to designed by techniques described herein to be laid out power terminal and ground terminal Series inductance (ESL), because the pattern being staggered line by line and/or by column eliminates conventional multilayer thin film capacitor and under normal circumstances can The magnetic field of generation.

Further recall, according to the realization of technology described herein, power terminal and ground terminal with line by line and/ Or the pattern being staggered by column is arranged on mediator.Fig. 3 is illustrated to be realized according to the one or more of techniques described herein The mediator 300 with the power and grounding pattern being staggered line by line and/or by column top view.The mediator 300 explained Including multiple ground connection (GND) terminal (302A ...) being arranged in the pattern being staggered on mediator 300 and multiple power (VDD) Terminal (304A ...).For example, column 306A and tool with power terminal 304A, 304B, 304C, 304D, 304E, 304F and 304G There are the column 308A of power terminal 302H, 302J, 302K, 302L, 302M, 302N and 302P to be staggered.That is, replacing the chess for having conventional Disk pattern, mediator 300 have the power terminal and ground terminal row and column being mutually staggered line by line and/or by column.For example, intermediary Power and ground plane in body 300 are two-dimensionally replaced with the pattern being staggered.

Under normal conditions, power terminal and ground terminal layout are made decoupling in decoupling capacitors with checkerboard pattern Magnetic field is generated between the electrode of capacitor.Function is laid out with the pattern that is staggered line by line and/or by column and unconventional checkerboard pattern Rate terminal and ground terminal reduce the equivalent series inductance (ESL) of mediator 300 because the pattern being staggered eliminate it is conventional more The magnetic field that layer film capacitor can generate under normal circumstances.

In an example implementation, mediator 300 can be used as multilager base plate (for example, M1-M4).In this implementation, function Rate and ground signalling can be routed back to the BGA on tube core.

In an example implementation, mediator 300 includes that six solder projections being arranged in this group of power contact (do not show Out) and six solder projection (not shown) being arranged on this group of earthing contact.This leads to 12 terminals and about The ESL of 70pH, because there is no magnetic field eliminations.Alternatively, mediator 300 includes 12 be arranged in this group of power contact A solder projection (not shown) and 12 solder projection (not shown) being arranged on this group of earthing contact.These power It is staggered line by line and/or column by column with earthing contact.This leads to 24 terminals and (six, which multiply six, matches from the value of about 70pH Set) to about 2pH value ESL change because the magnetic field between conductive through hole is eliminated.

In one or more implementations, mediator 300 includes two rows, 18 solders being arranged in this group of power contact Convex block (not shown) and two row solder projection (not shown) being arranged on this group of earthing contact.These power and ground connection touching Point is staggered line by line and/or column by column.This leads to 36 terminals and from the value (six multiply six configurations) of about 70pH to about The ESL of the value of 1pH changes, because the magnetic field between conductive through hole is eliminated.

In the realization of one or more replaceabilities, mediator 300 includes two rows 30 being arranged in this group of power contact Three solder projection (not shown) and two rows, the 40 solder projection (not shown) being arranged on this group of earthing contact.This A little power and earthing contact are staggered line by line and/or column by column.This leads to 73 terminals and (six multiply from the value of about 70pH Six configuration) to about 0.3pH value ESL change because the magnetic field between conductive through hole is eliminated.

For example, if power terminal and ground terminal form are that adduction subtracts pattern, then existing therefrom between conductive through hole The magnetic field counterclockwise of mediator bottom is arrived at the top of mediator.Lower a pair of adjacent conductive vias also has magnetic field counterclockwise.If as a result, only Have power terminal and ground terminal six multiply six configurations, it would be possible that eliminating without magnetic field.

Fig. 4 is shown according to the bilateral MIM of techniques described herein realization with the power and grounding pattern being staggered Mediator 400 section indicate.The mediator 400 explained includes MIM layer 402, MIM layer 404 and is arranged in MIM layers Mediator 406 between 402 and MIM layer 404.

The mediator 406 explained includes the multiple multilayers formed by multiple conductive through hole 410A, 410B, 410C and 410D Thin film capacitor.It will appear in normal conditions between conductive through hole 410A, 410B, 410C and 410D by what dotted arrow indicated Magnetic field in plural layers capacitor is eliminated using the configuration of mediator 406.

MIM layer 402 includes the insulating layer 411 for being wherein disposed with multiple metal wires and/or trace 412,414,416 and 418. In one or more implementations, insulating layer 411 may include inorganic oxide and/or inorganic nitride, such as silica, nitridation Silicon, tantalum oxide, strontium oxide strontia, hafnium oxide, titanium oxide, zirconium oxide, aluminum oxide or such.Alternatively, insulating layer can To be organic insulator, such as polyimides, benzo chlorobutane (BCB) or such.In one or more implementations, golden Belonging to trace 412,414,416 and 418 may include copper, copper alloy or other suitable materials.

MIM layer 404 includes the insulating layer 419 for being wherein disposed with multiple metal wires and/or trace 420,422,424 and 426. In one or more implementations, insulating layer 411 may include inorganic oxide and/or inorganic nitride, such as silica, nitridation Silicon, tantalum oxide, strontium oxide strontia, hafnium oxide, titanium oxide, zirconium oxide, aluminum oxide or such.Alternatively, insulating layer can To be organic insulator, such as polyimides, benzo chlorobutane (BCB) or such.In one or more implementations, golden Belonging to trace 412,414,416 and 418 may include copper, copper alloy or other suitable materials.

The surface of the MIM layer 402 explained includes multiple power terminal 428A and 428B and multiple ground terminal 430A And 430B.According to the realization of technology described herein, power terminal 428A and 428B and ground terminal 430A and 430B It is arranged on mediator 400 with the pattern being staggered line by line and/or by column.With the pattern that is staggered line by line and/or by column and it is non-traditional Checkerboard pattern reduce the equivalent series inductance (ESL) of mediator 400 to be laid out power terminal and ground terminal because being staggered Pattern eliminate the magnetic field that conventional multilayer thin film capacitor can generate under normal circumstances.

Fig. 5 shows the mediator with the power and grounding pattern that are staggered of the realization according to techniques described herein 500 section indicates.Mediator 500 includes two mediators being arranged together using solder projection 502 and solder projection 504 400.The two mediators 400 are shifted, so that power terminal 428A and 428B correspond respectively to ground terminal 430A and 430B. As single layer mediator 400, the double-deck mediator 500 make its power terminal 428A and 428B and ground terminal 430A and 430B is arranged with the pattern that is staggered line by line and/or by column.With the pattern that is staggered line by line and/or by column and unconventional chessboard figure Case reduces the equivalent series inductance (ESL) of mediator 500 to be laid out power terminal and ground terminal, because the pattern being staggered disappears The magnetic field that can be generated under normal circumstances in addition to conventional multilayer thin film capacitor.

Fig. 6 is shown to be indicated according to the section of the multilayer mediator 600 of the realization of techniques described herein.It is explained Mediator 600 includes the multiple mediators 500 having with the power and grounding pattern being staggered of arrangement on top of each other.As in As mediator 500, pattern that mediator 600 makes its power terminal and ground terminal to be staggered line by line and/or by column is arranged. With the pattern that is staggered line by line and/or by column and unconventional checkerboard pattern reduces intermediary to be laid out power terminal and ground terminal The equivalent series inductance (ESL) of body 600, because the pattern being staggered eliminates conventional multilayer thin film capacitor and under normal circumstances can The magnetic field of generation.

Fig. 7 is shown to be indicated according to the section of the multilayer mediator 700 of the realization of techniques described herein, wherein film The capacitor of capacitor can double, become four times etc..In the realization explained, multilayer mediator 700 is described in Fig. 6 The film version of mediator 600.For example, multilayer mediator 700 includes four layer 702,704,706 and 708.Such as mediator 600 Equally, mediator 700 makes its power terminal and ground terminal to be staggered line by line and/or by column pattern is arranged.With line by line And/or the pattern that is staggered by column and unconventional checkerboard pattern reduce mediator 700 to be laid out power terminal and ground terminal Equivalent series inductance (ESL) because the pattern being staggered eliminates conventional multilayer thin film capacitor and can generate under normal circumstances Magnetic field.

Fig. 8 is the flow chart explained according to the method 800 described herein for realizing production mediator.In frame 802, method 800 are operated by providing multiple power terminals and ground terminal with the pattern being staggered.In frame 804, method 800 passes through will be multiple Conductive through hole is coupled to multiple power terminal and ground terminal and is operated with forming multiple plural layers capacitors.In frame 806, Method 800, which passes through, is coupled in first group of contact for the power terminal for the pattern being staggered and ground terminal and multiple conductive through hole It is operated between second group of contact.

Each aspect of the present invention below for the specific embodiment of the invention description and related attached drawing in be disclosed.It can be with Alternative embodiment is designed without departing from the scope of the present invention.In addition, well-known element will not be retouched in detail in the present invention It states or will be removed in order to avoid falling into oblivion correlative detail of the invention.

Wording " exemplary " is used herein to mean that " being used as example, example or explanation ".Here depicted as " example Any embodiment of property " is not necessarily to be construed as preferred or advantageous over other embodiments.Equally, term " the embodiment of the present invention " is not It is required that all embodiments of the invention all include discussed feature, advantage or operating mode.

Term used herein is not intended to be limiting reality of the invention merely for for the purpose of describing particular embodiments Apply example.As it is used herein, " one " of singular, " certain " and "the" are intended to also include plural form, unless context is another It clearly dictates otherwise.It will also be understood that term " includes ", " having ", "comprising" and/or " containing " indicate that institute is old as used herein The presence of feature, integer, step, operation, element, and/or the component stated, but other one or more features, whole are not precluded Number, step, operation, element, component and/or the presence of its group or addition.

In addition, many embodiments are according to will be described by the action sequence that the element for for example calculating equipment executes.It will Recognize, various movements described herein can by special circuit (for example, application-specific integrated circuit (ASIC)), by just by one or more handle The program instruction or executed by combination of the two that device executes.In addition, these action sequences described herein can be considered as It is embodied in any type of computer readable storage medium completely, associated processing will just be made once execution by being stored with The corresponding computer instruction set of device execution functionality described here.Therefore, various aspects of the invention can with it is several not It is embodied with form, all these forms have all been contemplated to fall in the range of subject content claimed.In addition, for Each embodiment described herein, the corresponding form of any such embodiment can be described herein as example " being configured to Execute the described logic acted ".

Skilled artisans will appreciate that various any one of various different technologies and skill can be used for information and signal It indicates.For example, through be described above the data that may be addressed always, instruction, order, information, signal, position (bit), symbol, With chip can by voltage, electric current, electromagnetic wave, magnetic field or magnetic particle, light field or light particle, or any combination thereof indicate.

In addition, skilled artisans will appreciate that, various illustratives described in conjunction with the examples disclosed in this document are patrolled Collect the combination that block, module, circuit and algorithm steps can be implemented as electronic hardware, computer software, or both.For clearly This interchangeability of hardware and software is explained, various illustrative components, block, module, circuit and step are with its function above The form of energy property makees generalization description.Such functionality is implemented as hardware or software depends on concrete application and application In the design constraint of total system.Technical staff can realize described function with different modes for every kind of specific application Property, but such realization decision should not be interpreted to cause departing from the scope of the present invention.

Method, sequence and/or algorithm described in conjunction with the examples disclosed in this document can be embodied directly in hardware, in by It is embodied in the software module that reason device executes or in combination of the two.Software module can reside in RAM memory, flash memory, Institute in ROM memory, eprom memory, eeprom memory, register, hard disk, removable disk, CD-ROM or this field In the storage medium for any other form known.Exemplary storage medium is coupled to processor so that the processor can be from/to The storage medium reading writing information.Alternatively, storage medium can be integrated into processor.

Correspondingly, the embodiment of the present invention may include the side embodied for the low package parasitic inductance using threading mediator The computer-readable medium of method.Correspondingly, the present invention is not limited to the examples explained and any for executing described by text Functional means be included in the embodiment of the present invention.

Although disclosed above show illustrative embodiment of the invention, it is noted that can make wherein each The scope of the present invention that kind replacement and change are defined without departing from such as appended claims.It is sent out according to described herein Function, step and/or the movement of the claim to a method of bright embodiment need not be executed by any certain order.In addition, although Element of the invention may be described or claimed with odd number, but plural number be also it is contemplated, unless explicitly It states to be defined in odd number.

Claims (32)

1. a kind of structure including mediator, the mediator has the first side, second side opposite with first side, third Side, fourth side, fiveth side and with fiveth side opposite sixth side opposite with the third side, the structure include:

Including with relative to the third side and the 4th side and relative to the row of the 5th side and the 6th side and The multiple power terminals for the pattern arrangement of column being staggered and multiple plural layers capacitors of ground terminal；

It is coupled to the trace of the power terminal and the ground terminal, wherein being coupled to trace and the coupling of the power terminal Pattern arrangement to the trace of the ground terminal to be staggered；And

Be configured to the multiple conductive through holes pattern being staggered being coupled between first group of contact and second group of contact.

2. structure as described in claim 1, which is characterized in that first group of contact has smaller than second group of contact Spacing.

3. structure as claimed in claim 2, which is characterized in that the multiple plural layers capacitor is disposed in described first Between group contact and the multiple conductive through hole.

4. structure as claimed in claim 3, which is characterized in that further comprise be formed in the multiple conductive through hole with it is described More than second a plural layers capacitors between second group of contact.

5. structure as described in claim 1, which is characterized in that the multiple plural layers capacitor is with metal-insulator-gold Belong to (MIM) configuration to be formed.

6. structure as claimed in claim 5, which is characterized in that the multiple plural layers capacitor includes multiple channel capacitors Device.

7. structure as described in claim 1, which is characterized in that the mediator is to wear glass through-hole (TGV) mediator.

8. structure as described in claim 1, which is characterized in that the mediator is silicon through hole (TSV) mediator.

9. structure as described in claim 1, which is characterized in that the mediator is ceramic mediator.

10. structure as described in claim 1, which is characterized in that the mediator is organic mediator.

11. structure as described in claim 1, which is characterized in that the multiple plural layers capacitor includes multiple groove electricity Container.

12. a kind of system including mediator, comprising:

The mediator, the mediator include the first side and second side opposite with first side, third side, with described the The 4th opposite side of three sides, the 5th side and sixth side opposite with the 5th side, the mediator further comprises:

Including with relative to the third side and the 4th side and relative to the row of the 5th side and the 6th side and The multiple power terminals for the pattern arrangement of column being staggered and multiple plural layers capacitors of ground terminal；

It is coupled to the trace of the power terminal and the ground terminal, wherein being coupled to trace and the coupling of the power terminal Pattern arrangement to the trace of the ground terminal to be staggered；

Be configured to the multiple conductive through holes pattern being staggered being coupled between first group of contact and second group of contact；And

The tube core being arranged on the mediator.

13. system as claimed in claim 12, which is characterized in that first group of contact has smaller than second group of contact Spacing.

14. system as claimed in claim 13, which is characterized in that the multiple plural layers capacitor is disposed in described the Between one group of contact and the multiple conductive through hole.

15. system as claimed in claim 14, which is characterized in that further comprise being formed in the multiple conductive through hole and institute State more than second a plural layers capacitors between second group of contact.

16. system as claimed in claim 12, which is characterized in that the multiple plural layers capacitor is with metal-insulator- Metal (MIM) configuration is formed.

17. system as claimed in claim 16, which is characterized in that the multiple plural layers capacitor includes multiple groove electricity Container.

18. system as claimed in claim 12, which is characterized in that the mediator is to wear glass through-hole (TGV) mediator.

19. system as claimed in claim 12, which is characterized in that the mediator is silicon through hole (TSV) mediator.

20. system as claimed in claim 12, which is characterized in that the mediator is ceramic mediator.

21. system as claimed in claim 12, which is characterized in that the mediator is organic mediator.

22. system as claimed in claim 12, which is characterized in that the multiple plural layers capacitor includes multiple groove electricity Container.

23. system as claimed in claim 12, which is characterized in that the tube core is trigger.

24. system as claimed in claim 12, which is characterized in that further comprise be arranged in the mediator described second Substrate on side.

25. system as claimed in claim 12, which is characterized in that the pattern being staggered is the pattern being staggered line by line and by column At least one of.

26. a kind of manufacture includes the method for the structure of mediator, the mediator has the first side, opposite with first side Second side, third side, fourth side, fiveth side and with fiveth side opposite sixth side opposite with the third side, packet It includes:

With the row and column relative to the third side and the 4th side and relative to the 5th side and the 6th side The pattern being staggered provides multiple power terminals and ground terminal；

Trace is coupled to the power terminal and the ground terminal, wherein being coupled to trace and the coupling of the power terminal Pattern arrangement to the trace of the ground terminal to be staggered；

Multiple conductive through holes are coupled to the multiple power terminal and ground terminal to form multiple plural layers capacitors；With And

The pattern being staggered is coupled between first group of contact and second group of contact.

27. method as claimed in claim 26, which is characterized in that first group of contact has smaller than second group of contact Spacing.

28. method as claimed in claim 26, which is characterized in that the multiple plural layers capacitor is with metal-insulator- Metal (MIM) configuration is formed.

29. method as claimed in claim 26, which is characterized in that the pattern being staggered is the pattern being staggered line by line and by column At least one of.

30. method as claimed in claim 26, which is characterized in that the multiple plural layers capacitor includes multiple groove electricity Container.

31. method as claimed in claim 26, which is characterized in that the multiple conductive through hole is to wear glass through-hole (TGV) and wear At least one of through silicon via (TSV).

32. method as claimed in claim 26, which is characterized in that forming the multiple conductive through hole is with ceramic material, has At least one of machine material, glass material and silicon are performed.