JP5511119B2 - Interposer and semiconductor device - Google Patents

Description

  The present invention relates to an interposer and a semiconductor device, and more particularly to an interposer having a built-in power supply circuit or a capacitor and a semiconductor device in which a semiconductor chip is mounted on the interposer.

  Conventionally, in a semiconductor chip, in order to absorb high frequency noise generated in conjunction with high frequency operation, a decoupling capacitor is arranged around the semiconductor chip to achieve stable operation.

  However, when the operating frequency of the semiconductor chip is 1 GHz or more, a multilayer ceramic capacitor generally used as a decoupling capacitor cannot absorb high frequency noise. For this reason, a method is adopted in which multilayer ceramic capacitors are arranged around the semiconductor chip to suppress high frequency noise. For example, the effect of removing power supply noise including high-frequency noise components between the lead (terminal) of the power supply connected to the pad that supplies power to the circuit that is highly influenced by the high-frequency noise of the semiconductor chip and the ground lead High-capacity, low-capacity ceramic capacitors and multilayer ceramic capacitors are connected.

  In addition, a decoupling capacitor has been developed that realizes an equivalent series inductance with a low pH of 30 pH by forming a capacitor layer made of a ceramic thin film on a silicon substrate and devising the electrode shape of the capacitor layer using thin film microfabrication technology. (See Non-Patent Document 1).

This decoupling capacitor can efficiently remove high frequency noise from a semiconductor chip operating at a high speed of 1 GHz or more.
Fujitsu Laboratories Ltd., "Development of decoupling capacitors for high-speed LSIs operating at GHz-Reducing high-frequency noise to 1/3-", [online], [Search January 24, 2006], Internet <URL: http: //www.labs.fujitsu.com/jp/News/2001/Mar/14.html>

  However, in the prior art, with the miniaturization of the process, the problem of further power supply noise due to an increase in current consumption caused by an increase in integration degree, an increase in frequency, and an increase in the number of input pins becomes serious. In addition, the noise resistance has rapidly deteriorated as the operating voltage of the semiconductor chip is lowered.

  As a result, there is a problem that a voltage drop occurs due to an instantaneous current due to noise during operation in the semiconductor chip, causing a decrease in speed and a decrease in performance due to an increase in clock jitter. In particular, since power is supplied from the periphery in the central part of the semiconductor chip, the power supply wiring becomes long and the voltage drop becomes remarkable. In addition, since a capacitor is arranged around the semiconductor chip, the wiring distance from the capacitor to the pad (or internal circuit) of the semiconductor chip becomes long, and power supply noise including high-frequency noise components cannot be removed (noise removal capability). Is significantly reduced).

  The present invention has been made to solve the above-described problems. By incorporating a power supply circuit or the like in a substrate, for example, a voltage drop can be achieved by supplying power at a short distance to a flip-chip mounted semiconductor chip. It is an object to provide an interposer that prevents the above.

  In addition, by incorporating a capacitor in the substrate, for example, it is possible to provide an interposer that can remove power supply noise including high-frequency noise components by connecting the capacitor at a short distance to a flip-chip mounted semiconductor chip. Objective.

  Furthermore, it aims at providing the semiconductor device which mounted the semiconductor chip in said interposer.

  To achieve the above object, an interposer according to the present invention includes a substrate having a wiring layer formed on a surface layer, a plurality of pads formed on the wiring layer, a power supply circuit including a plurality of transistors, and It includes at least one of a capacitor having a pair of metal plates and a dielectric sandwiched between the metal plates, and at least one circuit formed under the wiring layer of the substrate.

  The circuit formed on the substrate of the present invention can be a power circuit only, a capacitor only, or both a power circuit and a capacitor.

  In the interposer of the present invention, when at least one circuit includes a power supply circuit, the final stage transistor of the power supply circuit may be formed so as to be located below, preferably directly below, any one of the plurality of pads. it can.

  Further, when at least one circuit includes a capacitor, the capacitor can be formed such that the center of the metal plate constituting the capacitor is positioned below any one of the plurality of pads, preferably directly below.

  At least one circuit of the present invention can be formed corresponding to a semiconductor chip mounted on an interposer.

  According to the interposer of the present invention, by forming the power supply circuit on the substrate, the distance to the mounted semiconductor chip can be shortened, thereby preventing a voltage drop and forming a capacitor on the substrate. Thus, noise to the mounted semiconductor chip can be reduced.

  The interposer of the present invention includes a substrate having a wiring layer formed on a surface layer, a plurality of pads formed on the wiring layer, and a plurality of stages of transistors, and the final stage of the transistors in the thickness direction of the substrate. A power supply circuit connected to any one of the plurality of pads through the extended first wiring, a pair of metal plates, and a dielectric sandwiched between the metal plates are stacked in the thickness direction of the substrate. And a capacitor connected to the pad to which the power supply circuit is connected via a second wiring in which the upper metal plate extends in parallel with the first wiring in the thickness direction of the substrate And at least one circuit formed under the wiring layer of the substrate.

  According to the interposer of the present invention, the power supply circuit is connected to one pad via the first wiring, and the capacitor is connected via the second wiring. Can be prevented.

  In the interposer of the present invention, a semiconductor device can be configured by mounting a semiconductor chip on the side of the interposer where the wiring layer is formed.

  A semiconductor device according to the present invention includes a substrate having a wiring layer formed on a surface layer, an interposer having a plurality of pads including a first pad and a second pad formed on the wiring layer, A first semiconductor chip mounted on the side where the wiring layer is formed and connected to the first pad; and a first semiconductor chip connected to the side where the wiring layer is formed on the substrate and connected to the second pad. And a second semiconductor chip, a plurality of transistors are provided, and the final transistor is connected to the first pad via a first wiring extending in the thickness direction of the substrate. A first power circuit connected, a pair of metal plates and a dielectric sandwiched between the metal plates are stacked in the thickness direction of the substrate, and the upper metal plate is connected to the first wiring Extending in the thickness direction of the substrate in parallel A first capacitor connected to the first pad and a plurality of stages of transistors are provided via a wiring, and the final stage transistor extends in parallel with the first wiring in the thickness direction of the substrate. A second power supply circuit connected to the second pad via a third wiring, a pair of metal plates, and a dielectric sandwiched between the metal plates in a thickness direction of the substrate. And a second capacitor connected to the second pad via a fourth wiring in which the upper metal plate extends in parallel with the first wiring in the thickness direction of the substrate, What is necessary is just to form under the wiring layer of a board | substrate.

  According to the semiconductor device of the present invention, the first power supply circuit and the first capacitor are connected to the first semiconductor chip at a short distance via the first pad, and the second power supply circuit and the second capacitor are connected to each other. Since it is connected to the second semiconductor chip at a short distance via the second pad, it is possible to individually prevent voltage drop and power supply noise with respect to the first and second semiconductor chips mounted on the interposer. it can.

  In the above semiconductor device, the magnitude of the voltage supplied from the first power supply circuit to the first semiconductor chip via the first pad and the second power supply circuit from the second power supply circuit to the second semiconductor chip via the second pad. The magnitude of the supplied voltage can be made different.

  As described above, according to the present invention, if the power supply circuit is built in the substrate, power can be supplied from the power supply circuit to the semiconductor chip mounted via the pad at a short distance. In addition, if a capacitor is built in the substrate, the capacitor can be connected to the semiconductor chip connected via the pad at a short distance, so that power noise can be reduced. The effect of is obtained.

  A first embodiment of the present invention will be described with reference to FIG. In this embodiment, a power supply circuit is formed in a substrate of an interposer.

  As shown in FIG. 1, the interposer (relay substrate) 12 is constituted by a substrate having a wiring layer 28 formed on the surface layer. A plurality of pads 18a, 18b, 24, and 26 are formed on the wiring layer 28 formed on the substrate. Further, a power supply circuit 40 including a plurality of stages of transistors is provided under the wiring layer 28 in the substrate. Further, on the upper surface of the wiring layer 28 of the substrate, the first semiconductor chip 14 and the second semiconductor chip 16 are powered via bumps (semiconductor chip connection pins) 30 and 32 formed on the pads 24 and 26. It is flip-chip mounted so as to be electrically connected to the final stage transistor of the circuit 40.

  A CPU or the like can be used as the first semiconductor chip 14 (hereinafter referred to as the first IC 14), and a memory or the like is used as the second semiconductor chip 16 (hereinafter referred to as the second IC 16). Can do.

  More specifically, as shown in FIG. 2, the final stage transistor of the power supply circuit 40 includes a gate polycrystalline silicon 84, a source 84a, a gate oxide film 84b, and a drain 84c. The drain 84c has a power supply wiring 80 formed immediately below any one of the pads 24 formed on the wiring layer 28, and a contact 82 extending in the thickness direction of the substrate so as to connect the power supply wiring 80 to each layer. It is connected to the pad 24 through the provided wiring.

  The first IC 14 is provided with a transistor including a gate polycrystalline silicon 74, a source 74a, a gate oxide film 74b, and a drain 74c. The drain 74c is provided below the wiring layer of the first IC 14. The power supply wiring 70 formed immediately above the formed pad 20 and the contact 20 extending in the thickness direction of the substrate for connecting the power supply wiring 70 to each layer are connected to the pad 20.

  As a result, the drain 84c of the final stage transistor of the power supply circuit 40 formed in the interposer 12 and the drain 74c of the transistor formed in the first IC 14 extend in the thickness direction of the substrate and include the bump 30 Therefore, the power can be supplied at the shortest distance.

  As shown in FIG. 1, gold wires 42 and 44 for wire bonding, which are connection wirings with external terminals connected to leads 46 and 48 which are external terminals, are connected to the pads 18a and 18b on the interposer 12. ing. The interposer 12, the first IC 14, and the second IC 16 are molded with a mold resin 52 for IC encapsulation / protection.

  In the semiconductor device of this embodiment, power is supplied from the leads 46 and 48 to the power supply circuit 40 via the gold wires 42 and 44 and the pads 18a and 18b, and the supplied power is contacted from the final stage transistor of the power supply circuit 40. 82, the power supply wiring 80, the pad 24, the bump 30, and the linear IC including the pad 20 are supplied to the first IC 14 that is flip-chip mounted.

  In the present embodiment, a power supply circuit 40 including a plurality of stages of transistors is built in the substrate of the interposer 12, and the final stage of the power supply circuit 40 is directly below any one of the pads 24 formed on the upper surface of the interposer 12. The drain 84c of the transistor is formed. For this reason, it is possible to supply power to a portion where the voltage drop becomes remarkable due to the low voltage of the operation power supply in the circuit and the influence of power supply noise, and the voltage drop can be prevented.

  In this embodiment, when it is desired to supply power to other semiconductor chips, the interposer 12 is provided with another power supply circuit composed of a plurality of stages of transistors in the interposer 12, and the drain of the final stage transistor is formed in the interposer 12. It may be formed so as to be located immediately below any one of the other pads.

  Further, when there are a plurality of semiconductor chips mounted on the interposer 12 and separated from each other in power supply, if a plurality of power supply circuits corresponding to each semiconductor chip are formed, power is supplied to each semiconductor chip at a short distance. be able to. If a plurality of power supply circuits are formed, different voltages can be supplied to each of the semiconductor chips.

  In the above description, the final-stage transistor is formed immediately below the pad, but may be formed near the pad.

  Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, a capacitor is formed in an interposer substrate. In FIG. 3, the same parts as those in FIG.

  As shown in FIG. 3, a capacitor (Metal-insulator-metal) including a pair of metal plates and a dielectric sandwiched between the metal plates under the wiring layer 28 formed on the substrate constituting the interposer 12. : MIM capacitor (hereinafter referred to as MIM) 60 is provided by laminating a metal plate and a dielectric in the thickness direction of the substrate. Further, the first IC 14 and the second IC 16 are electrically connected to the upper metal plate of the MIM 60 via the bumps 30 and 32 formed on the pads 24 and 26 on the upper surface of the wiring layer 28 of the substrate. It is flip-chip mounted.

  As shown in FIG. 4, the first IC 14 is flip-chip mounted so as to be electrically connected to the center of the upper metal plate of the MIM 60 via the pads 20, 24 and the bumps 30. That is, the center of the metal plate on the upper surface side of the MIM 60 is a power line 80 formed immediately below any one of the plurality of pads 24 formed on the wiring layer 28 and a contact for connecting the power line 80 to each layer. 82, and is connected to the pad 24 via wiring extending in the thickness direction of the substrate. The pad 24 includes a bump 30, a power supply wiring 70 formed immediately above any one of the plurality of pads 20 formed under the wiring layer of the first IC 14, and a contact 72 that connects the power supply wiring 70 to each layer. And is connected to the drain 74c of the transistor.

  In the present embodiment, a MIM 60 that is a capacitor including a pair of metal plates and a dielectric sandwiched between the metal plates is built in the substrate of the interposer 12, and directly below any one of the pads 24 of the interposer 12. The center of the MIM 60 is positioned at the center. Therefore, it is possible to connect to the first IC 14 at a short distance, and it is possible to prevent the influence of power supply noise due to the miniaturization of the process and the lowering of the operating power supply voltage inside the circuit.

  In this embodiment, when it is desired to connect the MIM to another semiconductor chip, the MIM other than the MIM 60 connected to the first IC 14 in the interposer 12 is any of the other pads. What is necessary is just to form so that it may be located under one. In addition, when there are a plurality of semiconductor chips mounted on the interposer 12 and separated from each other, the MIM can be connected to each semiconductor chip at a short distance by forming a plurality of MIMs corresponding to each semiconductor chip. it can. In this case, each of the MIM capacitors may have a different size.

  In the above description, an example in which the MIM is formed so that the center of the MIM is located immediately below the pad has been described. However, a portion other than the center of the MIM may be located immediately below the pad.

  Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 5, the same parts as those in FIGS. In this embodiment, a power supply circuit and an MIM are provided in a substrate.

  As shown in FIG. 5, a first power circuit 54 and a second power circuit 56 each including a plurality of stages of transistors are provided under the wiring layer 28 in the substrate. A first MIM 64 is provided between the first power supply circuit 54 and the wiring layer 28, and a second MIM 66 is provided between the second power supply circuit 56 and the wiring layer 28. It has been. The first IC 14 and the second IC 16 are flip-chip mounted on the upper surface of the wiring layer 28 of the substrate via bumps 30 and 32 formed on the first pad 34 and the second pad 36. ing. The first IC 14 is electrically connected to the final stage transistor of the first power supply circuit 54 and the center of the first MIM 64, and the second IC 16 is the final stage transistor of the second power supply circuit 56. And electrically connected to the center of the second MIM 66.

  More specifically, as shown in FIG. 6, the drain 114c of the final stage transistor of the first power supply circuit 54 is connected to the power supply wiring 116 formed immediately below the pad 34 formed on the wiring layer 28. And a contact 118 for connecting the power supply wiring 116 to each layer, and is connected to the pad 34 via a first wiring extending in the thickness direction of the substrate. The center of the upper metal plate of the first MIM 64 formed by laminating a pair of metal plates and a dielectric sandwiched between the metal plates in the thickness direction of the substrate is also formed on the wiring layer 28. Power supply wiring 110 formed under the pad 34 and a contact 112 for connecting the power supply wiring 110 to each layer, and via a second wiring extending in the thickness direction of the substrate in parallel with the first wiring, It is connected to the first pad 34. The drain 114 c of the first power supply circuit 54 is connected to one end side of the first pad 34 via the power supply wiring 116 and the contact 118, and the center of the first MIM 64 is connected via the power supply wiring 110 and the contact 112. The other end side of the pad 34 is connected. The first pad 34 includes a bump 30 provided at the center of the first pad 34, a pad 20, a power supply wiring 70 formed immediately above the pad 20, and a contact 72 that connects the power supply wiring 70 to each layer. And is connected to the drain 74c of the final stage transistor of the power supply circuit of the first IC 14.

  The drain 124c of the final stage transistor of the second power supply circuit 56 connects the power supply wiring 126 formed under the second pad 36 formed on the wiring layer 28 and the power supply wiring 126 to each layer. A contact 128 is provided and is connected to one end of the second pad 36 via a third wiring extending in the thickness direction of the substrate in parallel with the first wiring. The center of the upper metal plate of the second MIM 66 formed by laminating a pair of metal plates and a dielectric sandwiched between the metal plates in the thickness direction of the substrate was also formed below the second pad 36. The other end side of the 2nd pad 36 is provided with the contact 122 which connects the power supply wiring 120 and the power supply wiring 120 to each hierarchy, and extended in the thickness direction of the board | substrate in parallel with the 1st wiring. Connected with. The second pad 36 includes a bump 32 provided at the center of the second pad 36, a pad 22, a power supply wiring 100 formed immediately above the pad 22, and a contact 102 that connects the power supply wiring 100 to each layer. And is connected to the drain 104c of the final stage transistor of the power supply circuit of the second IC 16.

  In the present embodiment, the first power supply circuit 54 and the second power supply circuit 56, and the first MIM 64 and the second MIM 66 are independently incorporated in the substrate of the interposer 12 and are connected at a short distance. Therefore, the voltage drop and power supply noise of the mounted first IC 14 and second IC 16 can be prevented.

  Further, when there are semiconductor chips mounted on the interposer 12 and operating with different power supply voltages, if a plurality of power supply circuits and MIMs are formed in the substrate as described above corresponding to each semiconductor chip, It is possible to supply power of different magnitudes according to the power supply voltage operating on the semiconductor chip and to prevent power supply noise.

1 is a schematic cross-sectional view of a first embodiment of the present invention. It is sectional drawing which shows the detail of 1st Embodiment. It is a schematic sectional drawing of 2nd Embodiment of this invention. It is sectional drawing which shows the detail of 2nd Embodiment. It is sectional drawing of the outline of 3rd Embodiment of this invention. It is sectional drawing which shows the detail of 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 12 Interposer 14 1st semiconductor chip 16 2nd semiconductor chip 20, 22, 24, 26 Pad 34 1st pad 36 2nd pad 30, 32 Bump 40 Power supply circuit 54 1st power supply circuit 56 2nd power supply Circuit 60 MIM
64 First MIM
66 Second MIM

Claims (3)

A substrate having at least one pad on the surface;
A power supply circuit provided in the substrate, including a plurality of stages of transistors, and a drain of a final stage transistor disposed immediately below the pad;
In-substrate wiring that electrically connects the drain of the final-stage transistor of the power supply circuit and the pad and extends in the thickness direction of the substrate;
A capacitor provided in the substrate and electrically connected to the pad,
The capacitor is an interposer that extends in the thickness direction of the substrate and is connected to the pad by a wiring different from the wiring in the substrate . A substrate having a first pad and a second pad on the surface;
A first power supply circuit provided in the substrate, including a plurality of stages of transistors, and a drain of a final stage transistor disposed immediately below the first pad;
A second power supply circuit provided in the substrate, including a plurality of stages of transistors, and a drain of a final stage transistor disposed immediately below the second pad;
A first capacitor provided in the substrate and disposed immediately below the first pad;
A second capacitor provided in the substrate and disposed immediately below the second pad;
A first wiring electrically connecting a drain of the final stage transistor of the first power supply circuit and the first pad and extending in a thickness direction of the substrate;
A second wiring that electrically connects the first capacitor and the first pad and extends in a thickness direction of the substrate;
A third wiring that electrically connects the drain of the final stage transistor of the second power supply circuit and the second pad and extends in the thickness direction of the substrate;
A fourth wiring electrically connecting the second capacitor and the second pad and extending in a thickness direction of the substrate;
Including an interposer,
A first semiconductor chip having a semiconductor element mounted on the interposer and electrically connected to the first pad;
A second semiconductor chip having a semiconductor element mounted on the interposer and electrically connected to the second pad;
A semiconductor device comprising: The voltage supplied from the first power supply circuit to the first semiconductor chip via the first pad and the second power supply circuit to the second semiconductor chip via the second pad. 3. The semiconductor device according to claim 2 , wherein the magnitude of the supplied voltage is different.

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