CN105514153A - 一种碳化硅半导体 - Google Patents
一种碳化硅半导体 Download PDFInfo
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- CN105514153A CN105514153A CN201610075441.7A CN201610075441A CN105514153A CN 105514153 A CN105514153 A CN 105514153A CN 201610075441 A CN201610075441 A CN 201610075441A CN 105514153 A CN105514153 A CN 105514153A
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- silicon carbide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 27
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 27
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
Abstract
本发明公开了一种碳化硅半导体，所述碳化硅半导体两侧设置有耐压层，可以进一步增加半导体的耐压性能，所述N-集电层内设置有沟道，所述沟道与沟道之间设置有绝缘保护膜，可以在N-集电层内形成低电阻的电流通道，从而提高击穿电压值，所述欧姆接触层内设置有场限环，进一步调制外延JTE区域的电场，使得半导体的注入型区域的电场有明显的提高，从而大大提高了半导体的耐压能力，该碳化硅半导体具有耐压能力强以及使用时间长的优点。
Description
技术领域
本发明涉及定碳化硅半导体领域，特别涉及一种碳化硅半导体。
背景技术
碳化硅半导体作为一种新型半导体材料，具有潜在的优点：更小的体积、更有效率、完全去除开关损耗、低漏极电流、比标准半导体（纯硅半导体）更高的开关频率以及在标准的125℃结温以上工作的能力。小型化和高工作耐温使得这些器件的使用更加自如，甚至可以将这些器件直接置于电机的外壳内。碳化硅半导体具有以下特性：1、反向恢复时间极快，Rds极小，可以超高速开关，减少散热面积体积，大大提升电源节能效率；2、高频特性良好可以有效实现产品轻薄短小化（列如电动汽车充电设备）；3、耐高压特性良好高速列车及大电力等设备可在长时间高温下稳定操作运行；4、耐高温特性良好可让大电力设备（列如电动车）在长时间高温下稳定而且维持高效率运作。目前碳化硅半导体存在着击穿电压小和耐压性能差的问题。
发明内容
本发明所要解决的技术问题是提供一种定电流二极管，以解决现有技术中导致的上述多项缺陷。
为实现上述目的，本发明提供以下的技术方案：一种碳化硅半导体，包括N+衬底层、N-集电层、P型层和欧姆接触层，所述N+衬底层为碳化硅材料，所述N-集电层设置在N+衬底层的上方，所述N-集电层的厚度为14-16um，所述N-集电层的上方设置有基层和外延层，所述P型层设置在N-集电层的外延层上，所述P型层上设置有N+发射层，所述欧姆接触层设置在基层内。
优选的，所述碳化硅半导体两侧设置有耐压层。
优选的，所述N-集电层内设置有沟道。
优选的，所述沟道与沟道之间设置有绝缘保护膜。
优选的，所述欧姆接触层内设置有场限环。
采用以上技术方案的有益效果是：本发明结构的一种碳化硅半导体，所述碳化硅半导体两侧设置有耐压层，可以进一步增加半导体的耐压性能，所述N-集电层内设置有沟道，所述沟道与沟道之间设置有绝缘保护膜，可以在N-集电层内形成低电阻的电流通道，从而提高击穿电压值，所述欧姆接触层内设置有场限环，进一步调制外延JTE区域的电场，使得半导体的注入型区域的电场有明显的提高，从而大大提高了半导体的耐压能力，该碳化硅半导体具有耐压能力强以及使用时间长的优点。
附图说明
图1是本发明一种碳化硅半导体的结构示意图。
图2是沟道的结构示意图。
其中，1-N+衬底层、2-N-集电层、3-P型层、4-欧姆接触层、5-基层、6-外延层、7-N+发射层、8-耐压层、9-沟道、10-绝缘保护膜、11-场限环。
具体实施方式
下面结合附图详细说明本发明的优选实施方式。
图1出示本发明的具体实施方式：一种碳化硅半导体，包括N+衬底层1、N-集电层2、P型层3和欧姆接触层4，所述N+衬底层1为碳化硅材料，所述N-集电层2设置在N+衬底层1的上方，所述N-集电层2的厚度为14-16um，所述N-集电层2的上方设置有基层5和外延层6，所述P型层3设置在N-集电层2的外延层6上，所述P型层3上设置有N+发射层7，所述欧姆接触层4设置在基层5内。
此外，如图2所示，所述碳化硅半导体两侧设置有耐压层8，所述N-集电层2内设置有沟道9，所述沟道9与沟道9之间设置有绝缘保护膜10，所述欧姆接触层4内设置有场限环11。
基于上述，本发明提供一种碳化硅半导体，所述碳化硅半导体两侧设置有耐压层，可以进一步增加半导体的耐压性能，所述N-集电层内设置有沟道，所述沟道与沟道之间设置有绝缘保护膜，可以在N-集电层内形成低电阻的电流通道，从而提高击穿电压值，所述欧姆接触层内设置有场限环，进一步调制外延JTE区域的电场，使得半导体的注入型区域的电场有明显的提高，从而大大提高了半导体的耐压能力，该碳化硅半导体具有耐压能力强以及使用时间长的优点。
以上所述的仅是本发明的优选实施方式，应当指出，对于本领域的普通技术人员来说，在不脱离本发明创造构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。
Claims (5)
1.一种碳化硅半导体，其特征在于，包括N+衬底层、N-集电层、P型层和欧姆接触层，所述N+衬底层为碳化硅材料，所述N-集电层设置在N+衬底层的上方，所述N-集电层的厚度为14-16um，所述N-集电层的上方设置有基层和外延层，所述P型层设置在N-集电层的外延层上，所述P型层上设置有N+发射层，所述欧姆接触层设置在基层内。
2.根据权利要求1所述的一种碳化硅半导体，其特征在于，所述碳化硅半导体两侧设置有耐压层。
3.根据权利要求1所述的一种碳化硅半导体，其特征在于，所述N-集电层内设置有沟道。
4.根据权利要求3所述的一种碳化硅半导体，其特征在于，所述沟道与沟道之间设置有绝缘保护膜。
5.根据权利要求1所述的一种碳化硅半导体，其特征在于，所述欧姆接触层内设置有场限环。
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610075441.7A CN105514153A (zh) | 2016-02-03 | 2016-02-03 | 一种碳化硅半导体 |
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| CN201610075441.7A CN105514153A (zh) | 2016-02-03 | 2016-02-03 | 一种碳化硅半导体 |
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| CN105514153A true CN105514153A (zh) | 2016-04-20 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4472873A (en) * | 1981-10-22 | 1984-09-25 | Fairchild Camera And Instrument Corporation | Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure |
| US5416354A (en) * | 1989-01-06 | 1995-05-16 | Unitrode Corporation | Inverted epitaxial process semiconductor devices |
| CN103681816A (zh) * | 2012-09-09 | 2014-03-26 | 苏州英能电子科技有限公司 | 一种具有浮置环结构的双极型晶体管 |
-
2016
- 2016-02-03 CN CN201610075441.7A patent/CN105514153A/zh active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4472873A (en) * | 1981-10-22 | 1984-09-25 | Fairchild Camera And Instrument Corporation | Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure |
| US5416354A (en) * | 1989-01-06 | 1995-05-16 | Unitrode Corporation | Inverted epitaxial process semiconductor devices |
| CN103681816A (zh) * | 2012-09-09 | 2014-03-26 | 苏州英能电子科技有限公司 | 一种具有浮置环结构的双极型晶体管 |
Non-Patent Citations (2)
| Title |
|---|
| 张倩: "4H_SiC双外延基区双极晶体管模型与实验研究", 《中国博士论文全文数据库 信息科技辑》 * |
| 张有润: "4H_SiCBJT功率器件新结构与特性研究", 《中国博士论文全文数据库 信息科技辑》 * |
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