CN105514107A - Nonvolatile memory and manufacturing method thereof - Google Patents
Nonvolatile memory and manufacturing method thereof Download PDFInfo
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- CN105514107A CN105514107A CN201410487435.3A CN201410487435A CN105514107A CN 105514107 A CN105514107 A CN 105514107A CN 201410487435 A CN201410487435 A CN 201410487435A CN 105514107 A CN105514107 A CN 105514107A
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Abstract
The invention discloses a nonvolatile memory and a manufacturing method thereof. The nonvolatile memory comprises a substrate, a gate structure, a source and a drain, and a doped semiconductor layer. The gate structure comprises a tunneling dielectric layer, a charge trap layer, a top medium layer and a gate material layer, all of which are arranged on the substrate in sequence. The source and the drain are arranged in the substrate on the two sides of the gate structure, and the conductivity type of the source and the drain is opposite to that of the substrate. The doped semiconductor layer is arranged in the drain and connected with the charge trap layer, and the conductivity type of the doped semiconductor layer is opposite to that of the drain. As the energy band width of the doped semiconductor layer is obviously smaller than that of the tunneling dielectric layer, a tunneling channel is formed between the charge trap layer and the substrate and tunneling of electrons is realized through the tunneling channel, the working voltage of the nonvolatile memory is reduced, and the reading-writing speed of the nonvolatile memory is improved.
Description
Technical field
The application relates to the technical field of semiconductor integrated circuit, in particular to a kind of nonvolatile memory and preparation method thereof.
Background technology
Nonvolatile memory (non-volatilememory) be a kind of still can the memory of retention tab internal information after power supply is closed.Usually, nonvolatile memory or can be caught the large major technique of charge structure (such as SONOS structure) two and realizes by floating gate structure.Floating gate type memory has relatively thick tunnel oxide
once existing defects in tunnel oxide, stored charge is easily lost from polysilicon accumulation layer along defect.Catch the thinner thickness of the tunnel oxide of charge type memory, and utilize the silicon nitride medium layer of insulation to capture and stored charge, the trap that silicon nitride is used for catching electric charge is independently, can not cause a large amount of loss of electric charge because of a defect.Catch that charge type memory also has that anti-erasable ability is good, operating voltage is low and power is low, technical process is simple and with the advantage such as standard CMOS process is compatible.
Fig. 1 shows the cross-sectional view for existing nonvolatile memory (catching charge type memory).As shown in Figure 1, this nonvolatile memory comprises substrate 10 ', is arranged at the grid structure 40 ' on substrate 10 ', and be arranged at grid structure 40 ' both sides substrate 10 ' in source electrode 30 ' and drain electrode 20 '.Wherein, grid structure 40 ' comprises the tunneling medium layer 41 ' be set in turn on substrate 10 ', catches charge layer 42 ', top dielectric layer 43 ' and gate material layers 44 '; Drain electrode 20 ' comprises lightly doped drain 21 ' and is formed at the heavy doping drain electrode 23 ' in lightly doped drain 21 ', the heavy doping source electrode 33 ' that source electrode 30 ' comprises light dope source electrode 31 ' and is formed in light dope source electrode 31 '; The conduction type of source electrode 30 ' and drain electrode 20 ' is contrary with the conduction type of substrate 10 '.The material of tunneling medium layer 41 ' can be silica, the material of catching charge layer 42 ' can be silicon nitride, the material of top dielectric layer 43 ' can be silica, now tunneling medium layer 41 ', catch charge layer 42 ' and top dielectric layer 43 ' constitutes ONO structure.
The operation principle of above-mentioned nonvolatile memory is: when programming operation, positive voltage (being generally+12V) is applied between gate material layers 44 ' and substrate 10 ', source electrode 30 ' and drain electrode 20 ' apply identical low-voltage (being generally 0V), electronics generation tunnelling in raceway groove is through tunneling medium layer 41 ', be stored in and catch in charge layer 42 ', complete electron tunneling programming operation process.When erase operation, negative voltage (being generally-10V) is applied between gate material layers 44 ' and substrate 10 ', source electrode 30 ' and drain electrode 20 ' apply identical low-voltage (being generally 0V), the electron tunneling of catching and catching in charge layer 42 ' enters substrate 10 ' erase operation process through tunneling medium layer 41 ' can be completed.
In the course of work of above-mentioned nonvolatile memory, because tunneling medium layer 41 ' has higher bandwidth, make the electronics in raceway groove need to obtain higher energy and tunnelling could pass tunneling medium layer 41 ', the electronics ability tunnelling namely in higher program voltage lower channel is through tunneling medium layer 41 '.Similarly, the electronics needs of catching in charge layer 42 ' obtain higher energy tunnelling could enter substrate 10 ' through tunneling medium layer 41 ', and the electronics of namely catching under higher erasing voltage in charge layer 42 ' tunnelling could pass tunneling medium layer 41 '.Visible, need between gate material layers 44 ' and substrate 10 ', apply higher operating voltage and electron tunneling just can be made to pass tunneling medium layer 41 ', this will cause the read or write speed of nonvolatile memory slow.For the problems referred to above, also there is no effective solution at present.
Summary of the invention
The application aims to provide a kind of nonvolatile memory and preparation method thereof, to reduce the operating voltage of nonvolatile memory, thus improves the read or write speed of nonvolatile memory.
To achieve these goals, this application provides a kind of nonvolatile memory, this nonvolatile memory comprises: substrate; Grid structure, comprises the tunneling medium layer be set in turn on substrate, catches charge layer, top dielectric layer and gate material layers; Source electrode and drain electrode, be arranged in the substrate of the both sides of grid structure, and the conduction type of source electrode and drain electrode is contrary with the conduction type of substrate; Doping semiconductor layer, to be arranged in drain electrode and with catch charge layer and be connected, and the conduction type of doping semiconductor layer is contrary with the conduction type of drain electrode.
Further, doping semiconductor layer is positioned at the below of grid structure, and the upper surface of doping semiconductor layer overlaps with the lower surface of catching charge layer.
Further, the upper surface of doping semiconductor layer is not less than the upper surface of tunneling medium layer, and doping semiconductor layer runs through tunneling medium layer setting.
Further, the upper surface of doping semiconductor layer not higher than the surface of substrate, and catch charge layer run through tunneling medium layer arrange.
Further, the conduction type of substrate is P type, and the conduction type of source electrode and drain electrode is N-type, and the conduction type of doping semiconductor layer is P type; Or the conduction type of substrate is N-type, the conduction type of source electrode and drain electrode is P type, and the conduction type of doping semiconductor layer is N-type.
Further, substrate is p type single crystal silicon, and doping semiconductor layer is P type polysilicon, and the doped chemical in doping semiconductor layer is boron; Or substrate is n type single crystal silicon, be N-type polycrystalline silicon in doping semiconductor layer, and the doped chemical in doping semiconductor layer is phosphorus or arsenic.
Further, drain electrode comprises lightly doped drain and is formed at the heavy doping drain electrode in lightly doped drain, and doping semiconductor layer is arranged in lightly doped drain.
Further, the concentration of the doped chemical in lightly doped drain is 1E+14 ~ 1E+16atoms/cm
3, the concentration of the doped chemical in doping semiconductor layer is 1E+15 ~ 1E+18atoms/cm
3.
Further, tunneling medium layer is SiO
2layer, catching charge layer is SiN layer, and top dielectric layer is SiO
2layer, gate material layers is N-type polycrystalline silicon layer or P type polysilicon layer.
Present invention also provides a kind of manufacture method of nonvolatile memory, be included in and substrate formed by the tunneling medium layer be formed at successively on substrate, catch the grid structure that charge layer, top dielectric layer and gate material layers form, and in the substrate of the both sides of grid structure, form the step of the conduction type source electrode contrary with the conduction type of substrate and drain electrode, wherein, this manufacture method is also included in drain electrode the step forming the doping semiconductor layer contrary with the conduction type of catching that charge layer is connected, conduction type and drain electrode.
Further, drain electrode comprises lightly doped drain and is formed at the heavy doping drain electrode in lightly doped drain, and source electrode comprises light dope source electrode and is formed at the heavy doping source electrode in light dope source electrode; In the step forming doping semiconductor layer, form the doping semiconductor layer of the lightly doped drain be arranged in below grid structure.
Further, this manufacture method comprises the following steps: form basal body structure, comprise substrate, be formed at the lightly doped drain in substrate and light dope source electrode, and to be formed on substrate and there is the Tunnel dielectric preparation layers of the through hole corresponding to the position for forming doping semiconductor layer; In through-holes or the substrate be arranged in below through hole form doping semiconductor layer; Formed successively cover Tunnel dielectric preparation layers and doping semiconductor layer catch electric charge preparation layers, top medium preparation layers and grid material preparation layers; Successively etching grid material preparation layer, top medium preparation layers, catch electric charge preparation layers, Tunnel dielectric preparation layers to exposing substrate, to form grid structure; Ion implantation is carried out to the substrate of the both sides being positioned at grid structure, to form heavy doping drain electrode and heavy doping source electrode.
Further, the step forming doping semiconductor layer in through-holes comprises: form the doped semiconductor preparation layers covering through hole and Tunnel dielectric preparation layers; Planarization doped semiconductor preparation layers to exposing Tunnel dielectric preparation layers, and will remain doped semiconductor preparation layers as doping semiconductor layer.
Further, comprise in the step being arranged in the substrate below through hole and being formed doping semiconductor layer: carry out ion implantation to form doping semiconductor layer being arranged in the substrate below through hole.
Further, the step forming basal body structure comprises: form lightly doped drain and light dope source electrode in the substrate; Substrate is formed Tunnel dielectric preparation layers; Etching runs through Tunnel dielectric preparation layers to form through hole.
Further, after etching runs through Tunnel dielectric preparation layers, continue etched substrate and extend in substrate to make through hole.
The application by arrange in drain electrode with catch charge layer be connected and with the contrary doping semiconductor layer of conduction type of drain electrode, and utilize the bandwidth of doping semiconductor layer to be significantly less than the character of the bandwidth of tunneling medium layer, thus form tunnelling passage to enable electronics by tunnelling passage generation tunnelling catching between charge layer and substrate, and then reduce the operating voltage of nonvolatile memory, and further increase the read or write speed of nonvolatile memory.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the cross-sectional view of existing nonvolatile memory;
The cross-sectional view of the nonvolatile memory that a kind of execution mode that Fig. 2 a shows the application provides;
The cross-sectional view of the nonvolatile memory that the another kind of execution mode that Fig. 2 b shows the application provides;
Fig. 3 shows the schematic flow sheet of the manufacture method of the nonvolatile memory provided in the application's preferred implementation;
Fig. 4 shows in the manufacture method of the nonvolatile memory provided in a kind of preferred implementation of the application, formation comprises substrate, be formed at the lightly doped drain in substrate and light dope source electrode, and be formed on substrate and the cross-sectional view of matrix after there is the basal body structure of the Tunnel dielectric preparation layers of the through hole corresponding to the position for forming doping semiconductor layer;
Fig. 5 shows the cross-sectional view of the matrix after the doped semiconductor preparation layers forming the through hole shown in coverage diagram 4 and Tunnel dielectric preparation layers;
Fig. 6 shows the doped semiconductor preparation layers shown in planarization Fig. 5 to exposing Tunnel dielectric preparation layers, and using the cross-sectional view of residue doped semiconductor preparation layers as the matrix after doping semiconductor layer;
Fig. 7 shows the cross-sectional view of catching the matrix after electric charge preparation layers, top medium preparation layers and grid material preparation layers forming the Tunnel dielectric preparation layers shown in coverage diagram 6 and doping semiconductor layer successively;
Fig. 8 showing and etches the grid material preparation layers shown in Fig. 7, top medium preparation layers successively, catching electric charge preparation layers, Tunnel dielectric preparation layers to exposing substrate, to form the cross-sectional view of the matrix after grid structure;
Fig. 9 shows and carries out ion implantation to the substrate of the both sides being positioned at the grid structure shown in Fig. 8, to form the cross-sectional view of the matrix after heavy doping drain electrode and heavy doping source electrode;
Figure 10 shows in the manufacture method of the nonvolatile memory provided in the another kind of preferred implementation of the application, formation comprises substrate, be formed at the lightly doped drain in substrate and light dope source electrode, and be formed on substrate and the cross-sectional view of matrix after there is the basal body structure of the Tunnel dielectric preparation layers of the through hole corresponding to the position for forming doping semiconductor layer;
Figure 11 show be arranged in the substrate below the through hole shown in Figure 10 form doping semiconductor layer after the cross-sectional view of matrix;
Figure 12 shows the cross-sectional view of catching the matrix after electric charge preparation layers, top medium preparation layers and grid material preparation layers being formed successively and cover the Tunnel dielectric preparation layers shown in Figure 11 and doping semiconductor layer;
Figure 13 showing and etches the grid material preparation layers shown in Figure 12, top medium preparation layers successively, catching electric charge preparation layers, Tunnel dielectric preparation layers to exposing substrate, to form the cross-sectional view of the matrix after grid structure; And
Figure 14 shows and carries out ion implantation to the substrate of the both sides being positioned at the grid structure shown in Figure 13, to form the cross-sectional view of the matrix after heavy doping drain electrode and heavy doping source electrode.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
As what introduce in background technology, in the course of work of existing nonvolatile memory, needing between gate material layers and substrate, apply higher operating voltage just can make electron tunneling pass tunneling medium layer, thus causes the read or write speed of nonvolatile memory slow.
Present inventor studies for the problems referred to above, proposes a kind of nonvolatile memory.As shown in Figure 2 a and 2 b, this nonvolatile memory comprises: substrate 10; Grid structure 40, comprises the tunneling medium layer 41 be set in turn on substrate 10, catches charge layer 42, top dielectric layer 43 and gate material layers 44; Source electrode 30 and drain electrode 20, be arranged in the substrate 10 of the both sides of grid structure 40, and the conduction type of source electrode 30 and drain electrode 20 is contrary with the conduction type of substrate 10; Doping semiconductor layer 60, to be arranged in drain electrode 20 and with catch charge layer 42 and be connected, and the conduction type of doping semiconductor layer 60 is contrary with the conduction type of drain electrode 20.
The application by arranging the doping semiconductor layer 60 connected and contrary with the conduction type of drain electrode 20 with catching charge layer 42 in drain electrode 20, and utilize the bandwidth of doping semiconductor layer 60 to be significantly less than the character of the bandwidth of tunneling medium layer 41, thus form tunnelling passage to enable electronics by tunnelling passage generation tunnelling catching between charge layer 42 and substrate 10, and then reduce the operating voltage of nonvolatile memory, and further increase the read or write speed of nonvolatile memory.
The illustrative embodiments of the nonvolatile memory that the application provides will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, provide these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art.
In above-mentioned nonvolatile memory, those skilled in the art can according to the position of the instruction setting doping semiconductor layer 60 of the application.In order to reduce the operating voltage of nonvolatile memory further, and improve the read or write speed of nonvolatile memory further, preferably, doping semiconductor layer 60 is positioned at the below of grid structure 40, and the upper surface of doping semiconductor layer 60 overlaps with the lower surface of catching charge layer 42.
In above-mentioned preferred implementation, the forming position of doping semiconductor layer 60 can also be different.Such as, the upper surface of doping semiconductor layer 60 is not less than the upper surface of tunneling medium layer 41, and doping semiconductor layer 60 runs through tunneling medium layer 41 arranges.Again such as, the upper surface of doping semiconductor layer 60 not higher than the surface of substrate 10, and is caught charge layer 42 and is run through tunneling medium layer 41 and arrange.
The conduction type of above-mentioned doping semiconductor layer 60 and substrate 10 and source electrode 30 and drain 20 conduction type relevant.Particularly, when the conduction type of substrate 10 is P type, when the conduction type of source electrode 30 and drain electrode 20 is N-type, the conduction type of doping semiconductor layer 60 is P type; When the conduction type of substrate 10 is N-type, when the conduction type of source electrode 30 and drain electrode 20 is P type, the conduction type of doping semiconductor layer 60 is N-type.
Further, when substrate 10 is p type single crystal silicon, doping semiconductor layer 60 is P type polysilicon, and the doped chemical now in doping semiconductor layer 60 can be boron.When substrate 10 is n type single crystal silicon, be N-type polycrystalline silicon in doping semiconductor layer 60, the doped chemical now in doping semiconductor layer 60 can be phosphorus or arsenic.
In above-mentioned nonvolatile memory, the structure of source electrode 30 and drain electrode 20 has a variety of, in a preferred embodiment, drain electrode 20 comprises lightly doped drain 21 and is formed at the heavy doping drain electrode 23 in lightly doped drain 21, the heavy doping source electrode 33 that source electrode 30 comprises light dope source electrode 31 and is formed in light dope source electrode 31.Now, doping semiconductor layer 60 is arranged in lightly doped drain 21.Preferably, the concentration of the doped chemical in lightly doped drain 21 is 1E+14 ~ 1E+16atoms/cm
3, the concentration of the doped chemical in doping semiconductor layer 60 is 1E+15 ~ 1E+18atoms/cm
3.
In above-mentioned nonvolatile memory, those skilled in the art can set the material of each layer according to the instruction of the application and prior art.Preferably, tunneling medium layer 41 is SiO
2layer, catch charge layer 42 for SiN layer, top dielectric layer 43 is SiO
2layer, gate material layers 44 is N-type polycrystalline silicon layer or P type polysilicon layer.
Simultaneously, present invention also provides a kind of manufacture method of nonvolatile memory, be included in and substrate formed by the tunneling medium layer be formed at successively on substrate, catch the grid structure that charge layer, top dielectric layer and gate material layers form, and in the substrate of the both sides of grid structure, form the step of the conduction type source electrode contrary with the conduction type of substrate and drain electrode, wherein, this manufacture method is also included in drain electrode the step forming the doping semiconductor layer contrary with the conduction type of catching that charge layer is connected, conduction type and drain electrode.
Above-mentioned manufacture method by formed in drain electrode with catch charge layer be connected and with the contrary doping semiconductor layer of conduction type of drain electrode, and utilize the bandwidth of doping semiconductor layer to be significantly less than the character of the bandwidth of tunneling medium layer, thus form tunnelling passage to enable electronics by tunnelling passage generation tunnelling catching between charge layer and substrate, and then decrease the operating voltage of nonvolatile memory, and further increase the read or write speed of nonvolatile memory.
In above-mentioned nonvolatile memory, the structure of source electrode and drain electrode has a variety of, in a preferred embodiment, drain electrode comprises lightly doped drain and is formed at the heavy doping drain electrode in lightly doped drain, and source electrode comprises light dope source electrode and is formed at the heavy doping source electrode in light dope source electrode.Now, in the step forming doping semiconductor layer, the doping semiconductor layer of the lightly doped drain be arranged in below grid structure can be formed.Certainly, source electrode and drain electrode can also adopt other structures, and such as source electrode and drain electrode are by formation of once adulterating.Now, the step forming nonvolatile memory and formation have the step of the nonvolatile memory of source electrode that above-mentioned preferred implementation provides and drain electrode can be slightly different, but those skilled in the art can complete the making of nonvolatile memory according to the instruction of the application.
When forming the nonvolatile memory with source electrode that above-mentioned preferred implementation provides and drain electrode, as shown in Figure 3, this manufacture method comprises the following steps: form basal body structure, comprise substrate, be formed at the lightly doped drain in substrate and light dope source electrode, and be formed on substrate and there is the Tunnel dielectric preparation layers of the through hole corresponding to the position for forming doping semiconductor layer; In through-holes or the substrate be arranged in below through hole form doping semiconductor layer; Formed successively cover Tunnel dielectric preparation layers and doping semiconductor layer catch electric charge preparation layers, top medium preparation layers and grid material preparation layers; Successively etching grid material preparation layer, top medium preparation layers, catch electric charge preparation layers, Tunnel dielectric preparation layers to exposing substrate, to form grid structure; Ion implantation is carried out to the substrate of the both sides being positioned at grid structure, to form heavy doping drain electrode and heavy doping source electrode.
Formed in the step of above-mentioned nonvolatile memory, the forming position of doping semiconductor layer has a variety of.In a preferred embodiment, the upper surface of doping semiconductor layer is not less than the upper surface of tunneling medium layer, and doping semiconductor layer runs through tunneling medium layer setting.In another kind of preferred implementation, the upper surface of doping semiconductor layer not higher than the surface of substrate, and catch charge layer run through tunneling medium layer arrange.To the manufacture method forming the nonvolatile memory that these two kinds of preferred implementations provide be described respectively below.
Fig. 4 to Fig. 9 shows in the manufacture method of the nonvolatile memory that a kind of preferred implementation (namely doping semiconductor layer runs through the preferred implementation of tunneling medium layer) of the application provides, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Fig. 4 to Fig. 9, the manufacture method of the nonvolatile memory that above-mentioned preferred implementation provides is described.
First, form basal body structure, this basal body structure comprises substrate 10, is formed at the lightly doped drain 21 in substrate 10 and light dope source electrode 31, and to be formed on substrate 10 and to have the Tunnel dielectric preparation layers 41 ' of the through hole 50 corresponding to the position for forming doping semiconductor layer 60.Particularly, the step forming basal body structure comprises: in substrate 10, form lightly doped drain 21 and light dope source electrode 31; Form Tunnel dielectric preparation layers 41 ' over the substrate 10; Etching runs through Tunnel dielectric preparation layers 41 ' to form through hole 50.Further, etching runs through Tunnel dielectric preparation layers 41 ' afterwards, can also continue etched substrate 10 and extend in substrate 10 to make through hole 50, and then forms basal body structure as shown in Figure 4.
In this step, the material of substrate 10 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carbonization SiC), also can be silicon-on-insulator (SOI), germanium on insulator (GOI), or can also be other material, the III-V such as such as GaAs.The concentration of the assorted element in lightly doped drain 21 and light dope source electrode 31 can with reference to prior art, such as, can be 1E+14 ~ 1E+16atoms/cm
3.The material of Tunnel dielectric preparation layers 41 ' can be silicon dioxide, and the technique forming Tunnel dielectric preparation layers 41 ' can be chemical vapour deposition (CVD) etc.
The step that above-mentioned etching runs through Tunnel dielectric preparation layers 41 ' and etched substrate 10 comprises: in Tunnel dielectric preparation layers 41 ', form photoresist layer; Photoetching photoresist layer to form the opening corresponding to the position of through hole 50 in photoresist layer; Along opening etching Tunnel dielectric preparation layers 41 ' and substrate 10, to form through hole 50.Wherein, the step forming photoresist and photoetching can with reference to prior art; The technique of etching Tunnel dielectric preparation layers 41 ' and substrate 10 can be dry etching, and its concrete technology parameter can with reference to prior art.
Complete formation and comprise substrate 10, be formed at the lightly doped drain 21 in substrate 10 and light dope source electrode 31, and to be formed on substrate 10 and after there is the step of the basal body structure of the Tunnel dielectric preparation layers 41 ' of the through hole 50 corresponding to the position for forming doping semiconductor layer 60, in through hole 50, to form doping semiconductor layer 60.Preferably, this step comprises: form the doped semiconductor preparation layers 60 ' covering through hole 50 and Tunnel dielectric preparation layers 41 ', and then forms basal body structure as shown in Figure 5; Planarization doped semiconductor preparation layers 60 ' to exposing Tunnel dielectric preparation layers 41 ', and will remain doped semiconductor preparation layers 60 ' as doping semiconductor layer 60, and then form basal body structure as shown in Figure 6.
Above-mentioned doped semiconductor preparation layers 60 ' is preferably doped polysilicon layer etc.Now, the step forming doped semiconductor preparation layers 60 ' comprises: first deposition of polysilicon layer, then carries out ion implantation to form doped polysilicon layer to polysilicon layer; Or in deposition of polysilicon layer process, pass into Doped ions to carry out in-situ doped to polysilicon layer.The concentration of the doped chemical in doping semiconductor layer 60 can set according to process requirements, such as, can be 1E+15 ~ 1E+18atoms/cm
3.The technique of planarization doped semiconductor preparation layers 60 ' can be chemico-mechanical polishing or dry etching etc., and its concrete technology parameter with reference to prior art, can not repeat them here.
Complete in through hole 50 or after the substrate 10 be arranged in below through hole 50 forms the step of doping semiconductor layer 60, formed successively cover Tunnel dielectric preparation layers 41 ' and doping semiconductor layer 60 catch electric charge preparation layers 42 ', top medium preparation layers 43 ' and grid material preparation layers 44 ', and then form basal body structure as shown in Figure 7.Wherein, the material of catching electric charge preparation layers 42 ' can be silicon nitride, the material of top medium preparation layers 43 ' can be silicon dioxide, the material of grid material preparation layers 44 ' can be N-type or P type polysilicon, electric charge preparation layers 42 ' is caught in formation, the technique of top medium preparation layers 43 ' can be plasma reinforced chemical vapour deposition etc., and its concrete technology parameter can with reference to prior art.
Complete formed successively cover Tunnel dielectric preparation layers 41 ' and doping semiconductor layer 60 catch the step of electric charge preparation layers 42 ', top medium preparation layers 43 ' and grid material preparation layers 44 ' after, successively etching grid material preparation layer 44 ', top medium preparation layers 43 ', catch electric charge preparation layers 42 ', Tunnel dielectric preparation layers 41 ' to exposing substrate 10, to form grid structure 40, and then form basal body structure as shown in Figure 8.Particularly, this step comprises: first, and grid material preparation layers 44 ' forms photoresist layer; Then, photoetching photoresist layer, covers for forming grid structure 40 to make remaining photoresist layer; Next, etching grid material preparation layer 44 ', top medium preparation layers 43 ', catch electric charge preparation layers 42 ', Tunnel dielectric preparation layers 41 ' to exposing substrate 10 to form grid structure 40; Finally, photoresist layer is removed.
In this step, the step forming photoresist and photoetching can with reference to prior art; Etching grid material preparation layer 44 ', top medium preparation layers 43 ', catch electric charge preparation layers 42 ', the technique of Tunnel dielectric preparation layers 41 ' can for dry etching, its concrete technology parameter can with reference to prior art.
Complete etching grid material preparation layer 44 ' successively, top medium preparation layers 43 ', catch electric charge preparation layers 42 ', Tunnel dielectric preparation layers 41 ' is to exposing substrate 10 with after the step forming grid structure 40, ion implantation is carried out to the substrate 10 of the both sides being positioned at grid structure 40, to form heavy doping drain electrode 23 and heavy doping source electrode 33, and then form basal body structure as shown in Figure 9.The doping content that above-mentioned heavy doping drains in 23 and heavy doping source electrode 33 can set according to actual process demand, such as, can be 1E+15 ~ 1E+18atoms/cm
3.
The type of above-mentioned injection ion is relevant to the conduction type of substrate 10.When substrate 10 is N-type silicon, inject ion and be preferably boron ion.When substrate 10 is p type single crystal silicon, inject ion and be preferably phosphonium ion or arsenic ion.Certainly, the type injecting ion is not limited in above-mentioned optimal way.Those skilled in the art can according to the dosage of the above-mentioned injection ion of actual process requirements set and energy, and such as, the dosage injecting ion is 1E+11 ~ 1E+13atoms/cm
2, the energy injecting ion is 40 ~ 80KeV.
Figure 10 to Figure 14 shows in the manufacture method of the nonvolatile memory that the another kind of preferred implementation (namely catching the preferred implementation that charge layer 42 runs through tunneling medium layer 41) of the application provides, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Figure 10 to Figure 14, the manufacture method of the nonvolatile memory that above-mentioned preferred implementation provides is described.
First, form basal body structure, this basal body structure comprises substrate 10, is formed at the lightly doped drain 21 in substrate 10 and light dope source electrode 31, and to be formed on substrate 10 and to have the Tunnel dielectric preparation layers 41 ' of the through hole 50 corresponding to the position for forming doping semiconductor layer 60.Particularly, the step forming basal body structure comprises: in substrate 10, form lightly doped drain 21 and light dope source electrode 31; Form Tunnel dielectric preparation layers 41 ' over the substrate 10; Etching runs through Tunnel dielectric preparation layers 41 ' to form through hole 50.Further, etching runs through Tunnel dielectric preparation layers 41 ' afterwards, can also continue etched substrate 10 and extend in substrate 10 to make through hole 50, and then forms basal body structure as shown in Figure 10.
In this step, the material of substrate 10 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carbonization SiC), also can be silicon-on-insulator (SOI), germanium on insulator (GOI), or can also be other material, the III-V such as such as GaAs.The concentration of the doped chemical in lightly doped drain 21 and light dope source electrode 31 can with reference to prior art, such as, can be 1E+14 ~ 1E+16atoms/cm
3.The material of Tunnel dielectric preparation layers 41 ' can be silicon dioxide, and the technique forming Tunnel dielectric preparation layers 41 ' can be chemical vapour deposition (CVD) etc.
The step that above-mentioned etching runs through Tunnel dielectric preparation layers 41 ' and etched substrate 10 comprises: in Tunnel dielectric preparation layers 41 ', form photoresist layer; Photoetching photoresist layer to form the opening corresponding to the position of through hole 50 in photoresist layer; Along opening etching Tunnel dielectric preparation layers 41 ' and substrate 10, to form through hole 50.Wherein, the step forming photoresist and photoetching can with reference to prior art; The technique of etching Tunnel dielectric preparation layers 41 ' and substrate 10 can be dry etching, and its concrete technology parameter can with reference to prior art.
Complete formation and comprise substrate 10, be formed at the lightly doped drain 21 in substrate 10 and light dope source electrode 31, and to be formed on substrate 10 and after there is the step of the basal body structure of the Tunnel dielectric preparation layers 41 ' of the through hole 50 corresponding to the position for forming doping semiconductor layer 60, form doping semiconductor layer 60 at the substrate 10 be arranged in below through hole 50, and then form basal body structure as shown in figure 11.This step comprises: carry out ion implantation to form doping semiconductor layer 60 at the substrate 10 be arranged in below through hole 50, and then forms basal body structure as shown in figure 11.
Those skilled in the art can according to the dosage of the above-mentioned injection ion of actual process requirements set and energy, and such as, the dosage injecting ion is 1E+11 ~ 1E+13atoms/cm
2, the energy injecting ion is 40 ~ 80KeV, and the concentration of the doped chemical in the doping semiconductor layer 60 formed can be 1E+15 ~ 1E+18atoms/cm
3.
Complete in through hole 50 or after the substrate 10 be arranged in below through hole 50 forms the step of doping semiconductor layer 60, formed successively cover Tunnel dielectric preparation layers 41 ' and doping semiconductor layer 60 catch electric charge preparation layers 42 ', top medium preparation layers 43 ' and grid material preparation layers 44 ', and then form basal body structure as shown in figure 12.Wherein, the material of catching electric charge preparation layers 42 ' can be silicon nitride, the material of top medium preparation layers 43 ' can be silicon dioxide, the material of grid material preparation layers 44 ' can be N-type or P type polysilicon, electric charge preparation layers 42 ' is caught in formation, the technique of top medium preparation layers 43 ' can be plasma reinforced chemical vapour deposition etc., and its concrete technology parameter can with reference to prior art.
Complete formed successively cover Tunnel dielectric preparation layers 41 ' and doping semiconductor layer 60 catch the step of electric charge preparation layers 42 ', top medium preparation layers 43 ' and grid material preparation layers 44 ' after, successively etching grid material preparation layer 44 ', top medium preparation layers 43 ', catch electric charge preparation layers 42 ', Tunnel dielectric preparation layers 41 ' to exposing substrate 10, to form grid structure 40, and then form basal body structure as shown in fig. 13 that.Particularly, this step comprises: first, and grid material preparation layers 44 ' forms photoresist layer; Then, photoetching photoresist layer, covers for forming grid structure 40 to make remaining photoresist layer; Next, etching grid material preparation layer 44 ', top medium preparation layers 43 ', catch electric charge preparation layers 42 ', Tunnel dielectric preparation layers 41 ' to exposing substrate 10 to form grid structure 40; Finally, photoresist layer is removed.
In this step, the step forming photoresist and photoetching can with reference to prior art; Etching grid material preparation layer 44 ', top medium preparation layers 43 ', catch electric charge preparation layers 42 ', the technique of Tunnel dielectric preparation layers 41 ' can for dry etching, its concrete technology parameter can with reference to prior art.
Complete etching grid material preparation layer 44 ' successively, top medium preparation layers 43 ', catch electric charge preparation layers 42 ', Tunnel dielectric preparation layers 41 ' is to exposing substrate 10 with after the step forming grid structure 40, ion implantation is carried out to the substrate 10 of the both sides being positioned at grid structure 40, to form heavy doping drain electrode 23 and heavy doping source electrode 33, and then form basal body structure as shown in figure 14.The doping content that above-mentioned heavy doping drains in 23 and heavy doping source electrode 33 can set according to actual process demand, such as, can be 1E+15 ~ 1E+18atoms/cm
3.
The type of above-mentioned injection ion is relevant to the conduction type of substrate 10.When substrate 10 is N-type silicon, inject ion and be preferably boron ion.When substrate 10 is p type single crystal silicon, inject ion and be preferably phosphonium ion or arsenic ion.Certainly, the type injecting ion is not limited in above-mentioned optimal way.Those skilled in the art can according to the dosage of the above-mentioned injection ion of actual process requirements set and energy, and such as, the dosage injecting ion is 1E+11 ~ 1E+13atoms/cm
2, the energy injecting ion is 40 ~ 80KeV.
From above description, can find out, the application's the above embodiments achieve following technique effect: the application by arrange in drain electrode with catch charge layer be connected and with the contrary doping semiconductor layer of conduction type of drain electrode, and utilize the bandwidth of doping semiconductor layer to be significantly less than the character of the bandwidth of tunneling medium layer, thus form tunnelling passage to enable electronics by tunnelling passage generation tunnelling catching between charge layer and substrate, and then decrease the operating voltage of nonvolatile memory, and further increase the read or write speed of nonvolatile memory.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (16)
1. a nonvolatile memory, is characterized in that, described nonvolatile memory comprises:
Substrate;
Grid structure, comprises the tunneling medium layer be set in turn on described substrate, catches charge layer, top dielectric layer and gate material layers;
Source electrode and drain electrode, be arranged in the described substrate of the both sides of described grid structure, and the conduction type of described source electrode and described drain electrode is contrary with the conduction type of described substrate;
Doping semiconductor layer, to be arranged in described drain electrode and to be connected with described charge layer of catching, and the conduction type of described doping semiconductor layer is contrary with the conduction type of described drain electrode.
2. nonvolatile memory according to claim 1, is characterized in that, described doping semiconductor layer is positioned at the below of described grid structure, and the upper surface of described doping semiconductor layer and described lower surface of catching charge layer overlap.
3. nonvolatile memory according to claim 2, is characterized in that, the upper surface of described doping semiconductor layer is not less than the upper surface of described tunneling medium layer, and described doping semiconductor layer runs through the setting of described tunneling medium layer.
4. nonvolatile memory according to claim 2, is characterized in that, the upper surface of described doping semiconductor layer not higher than the surface of described substrate, and described in catch charge layer run through described tunneling medium layer arrange.
5. nonvolatile memory according to any one of claim 1 to 4, is characterized in that,
The conduction type of described substrate is P type, and the conduction type of described source electrode and described drain electrode is N-type, and the conduction type of described doping semiconductor layer is P type; Or
The conduction type of described substrate is N-type, and the conduction type of described source electrode and described drain electrode is P type, and the conduction type of described doping semiconductor layer is N-type.
6. nonvolatile memory according to claim 5, is characterized in that,
Described substrate is p type single crystal silicon, and described doping semiconductor layer is P type polysilicon, and the doped chemical in described doping semiconductor layer is boron; Or
Described substrate is n type single crystal silicon, is N-type polycrystalline silicon in described doping semiconductor layer, and the doped chemical in described doping semiconductor layer is phosphorus or arsenic.
7. nonvolatile memory according to claim 5, is characterized in that, described drain electrode comprises lightly doped drain and is formed at the heavy doping drain electrode in described lightly doped drain, and described doping semiconductor layer is arranged in lightly doped drain.
8. nonvolatile memory according to claim 7, is characterized in that, the concentration of the doped chemical in described lightly doped drain is 1E+14 ~ 1E+16atoms/cm
3, the concentration of the doped chemical in described doping semiconductor layer is 1E+15 ~ 1E+18atoms/cm
3.
9. nonvolatile memory according to claim 5, is characterized in that, described tunneling medium layer is SiO
2layer, described in catch charge layer be SiN layer, described top dielectric layer is SiO
2layer, described gate material layers is N-type polycrystalline silicon layer or P type polysilicon layer.
10. the manufacture method of a nonvolatile memory, be included in and substrate formed by the tunneling medium layer be formed at successively on described substrate, catch the grid structure that charge layer, top dielectric layer and gate material layers form, and in the described substrate of the both sides of described grid structure, form the step of the conduction type source electrode contrary with the conduction type of described substrate and drain electrode
It is characterized in that, described manufacture method is also included in described drain electrode the step forming the doping semiconductor layer contrary with described conduction type of catching that charge layer is connected, conduction type and described drain electrode.
11. manufacture methods according to claim 10, is characterized in that,
Described drain electrode comprises lightly doped drain and is formed at the heavy doping drain electrode in described lightly doped drain, and described source electrode comprises light dope source electrode and is formed at the heavy doping source electrode in described light dope source electrode;
In the step forming described doping semiconductor layer, form the described doping semiconductor layer of the described lightly doped drain be arranged in below described grid structure.
12. manufacture methods according to claim 11, is characterized in that, described manufacture method comprises the following steps:
Form basal body structure, comprise substrate, be formed at the described lightly doped drain in described substrate and described light dope source electrode, and to be formed on described substrate and there is the Tunnel dielectric preparation layers of the through hole corresponding to the position for forming described doping semiconductor layer;
In described through hole or the described substrate be arranged in below described through hole form described doping semiconductor layer;
Formed successively cover described Tunnel dielectric preparation layers and described doping semiconductor layer catch electric charge preparation layers, top medium preparation layers and grid material preparation layers;
Etch described grid material preparation layers, top medium preparation layers successively, catch electric charge preparation layers, Tunnel dielectric preparation layers to exposing described substrate, to form described grid structure;
Ion implantation is carried out to the described substrate of the both sides being positioned at described grid structure, to form described heavy doping drain electrode and described heavy doping source electrode.
13. manufacture methods according to claim 12, is characterized in that, the step forming described doping semiconductor layer in described through hole comprises:
Form the doped semiconductor preparation layers covering described through hole and described Tunnel dielectric preparation layers;
Doped semiconductor preparation layers described in planarization to exposing described Tunnel dielectric preparation layers, and will remain described doped semiconductor preparation layers as described doping semiconductor layer.
14. manufacture methods according to claim 12, it is characterized in that, comprise in the step being arranged in the described substrate below described through hole and being formed described doping semiconductor layer: carry out ion implantation to form described doping semiconductor layer being arranged in the described substrate below described through hole.
15. manufacture methods according to claim 12, is characterized in that, the step forming described basal body structure comprises:
Described lightly doped drain and described light dope source electrode is formed in described substrate;
Form described Tunnel dielectric preparation layers over the substrate;
Etching runs through described Tunnel dielectric preparation layers to form described through hole.
16. manufacture methods according to claim 15, is characterized in that, after etching runs through described Tunnel dielectric preparation layers, continue the described substrate of etching and extend in described substrate to make described through hole.
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