CN110098125A - The forming method of SONOS device - Google Patents
The forming method of SONOS device Download PDFInfo
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- CN110098125A CN110098125A CN201910314856.9A CN201910314856A CN110098125A CN 110098125 A CN110098125 A CN 110098125A CN 201910314856 A CN201910314856 A CN 201910314856A CN 110098125 A CN110098125 A CN 110098125A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 230000008569 process Effects 0.000 claims abstract description 29
- 238000002347 injection Methods 0.000 claims abstract description 20
- 239000007924 injection Substances 0.000 claims abstract description 20
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- 239000010703 silicon Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 238000005516 engineering process Methods 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 13
- 230000008859 change Effects 0.000 claims description 7
- 238000000407 epitaxy Methods 0.000 claims description 7
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of forming method of SONOS device, comprising: successively forms ONO layer, polysilicon layer and hard mask layer on a semiconductor substrate；Form the first side wall for covering the side surface of the polysilicon layer and the hard mask layer；The ONO layer being exposed is etched using anisotropic etch process, removes the barrier oxide layer and charge storage layer of the ONO layer being exposed；Then LDD injection is executed, ion lightly doped district is formed；And form the side surface of the first side wall of covering and the second side wall of remaining ONO layer.The forming method of SONOS device provided by the invention protects the charge storage layer under polysilicon layer using the second side wall; subsequent etching is helped avoid in the process to the over etching of charge storage layer; the reliability of device is improved, and reduces technique controlling difficulty；In addition, followed by executing LDD injection performing etching to the ONO layer being exposed, no longer needs to re-start photoetching, simplify technique, control process costs.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially a kind of forming method of SONOS device.
Background technique
With the rise of technology of Internet of things and the development of portable wearable device, demand of the people to low-power consumption product
It gradually increases, this just needs to research and develop a large amount of low-power chip, and the operation voltage for reducing chip can effectively reduce power consumption.
Based on FDSOI (Fully Depleted Silicon-On-Insulator, fully- depleted silicon-on-insulator) technology
Wafer used in technique has silicon on one layer of buried sio (buried oxide, BOX) and one layer of ultrathin insulating body, by wafer
Silicon substrate be known as body silicon layer, the buried sio for being formed in body silicon surface is known as buried oxide layer, is formed on buried oxide layer surface super
Thin silicon, that is, SOI is known as top layer silicon.Due to the presence of buried oxide layer, on the one hand there is preferable isolation characteristic, on the other hand can lead to
Cross the modulation that change body-bias (body bias) carries out threshold voltage.In addition, can directly continue to use body based on FDSOI technique
The design architecture of CMOS.Ultrathin crystal pipe is formed in ultra-thin top layer silicon in FDSOI can control short-channel effect well,
And then supply voltage can be reduced, it is operated by flexible backgate, operating voltage can drop to 0.4V, the electric leakage of MOS device
Stream is less than 0.1pA/ μm, is very suitable to the exploitation of low-power consumption product.
SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) embedded flash memory have simple process, with patrol
The advantageous characteristics such as processing compatibility is good, power consumption is lower and ductility is strong are collected, by FDSOI technology and SONOS embedded flash memory
Technology combines, such as logic element is arranged on FDSOI substrate, develops the embedded flash memory product of mixing, in power consumption and
The great competitiveness of aspect of performance.
In the preparation process of existing SONOS device, it is initially formed the gate structure of SONOS, is included in substrate surface successively
ONO (Oxide-Nitride-Oxide, the tunnel oxide-nitration case-barrier oxide layer) layer and polysilicon layer of superposition, polycrystalline
Silicon layer covers the part of the surface of ONO layer, the side wall (spacer) of covering polysilicon layer side surface is then formed, followed by wet process
The outermost layer (usually silicon nitride) of etching removal side wall, finally carries out that injection (LDD) is lightly doped.However, due to wet etching
Have the characteristics that isotropism, is easy to cause in ONO layer in the outermost process using wet etching removal side wall for storing up
The charge storage layer (usually silicon nitride) for depositing electronics is also laterally etched.And then the reliability for making product is caused to reduce, if
It is laterally etched serious, so that being also corroded below polysilicon gate, SONOS component failure will be caused.In prior art, usually
Strict control is carried out to the process of wet etching, to avoid charge storage layer laterally etched, but it is higher and usual to control difficulty
It is difficult to reach preferable effect.Therefore, there is still a need for improvement for the existing SONOS technique based on FDSOI technology.
Summary of the invention
The present invention provides a kind of forming method of SONOS device, laterally etched to solve the charge storage layer in ONO layer
Caused by properties of product the problem of being affected.
The forming method of the SONOS device includes:
It forms the ONO layer being located on semiconductor base, the polysilicon layer on the ONO layer and is located at the polycrystalline
Hard mask layer on silicon layer, the ONO layer include the tunnelling oxygen being sequentially overlapped along the direction far from the semiconductor substrate surface
Change layer, charge storage layer and barrier oxide layer, the width of the ONO layer is greater than the width of the polysilicon layer；
Form the first side wall for covering the side surface of the polysilicon layer and the hard mask layer, the width of the ONO layer
Greater than the sum of first side wall and width of the polysilicon layer；
The ONO layer being exposed is etched, using anisotropic etch process to remove in the ONO layer being exposed
Barrier oxide layer and charge storage layer；
Then LDD injection is executed, forms ion lightly doped district in the semiconductor base of the polysilicon layer two sides；And
Form the second side wall, second side wall cover first side wall side surface and the remaining ONO layer.
Optionally, when etching the ONO layer being exposed, the tunnelling oxygen in the ONO layer being exposed also is removed
Change layer.
Optionally, after etching the ONO layer being exposed, before executing LDD injection, thermal anneal process is carried out, in institute
It states semiconductor substrate surface and forms protective oxide film.
Optionally, second side wall includes side wall oxide layer and side wall nitride layer, described in the side wall oxide layer covering
The side surface of first side wall and the remaining ONO layer, the side wall nitride layer cover the side wall oxide layer.
Optionally, the forming method of the SONOS device further includes, using wet-etching technology, removing the side wall nitrogen
Change layer and the hard mask layer.
Optionally, the semiconductor substrate surface definition has memory block and logic area, and the ONO layer is located at the storage
Area, the logic area are used to form logical device, and the semiconductor base corresponding to the logic area is FDSOI structure.
Optionally, the logical device includes logic rhythmic structure of the fence and covering logic rhythmic structure of the fence side surface
Logic gate side wall, be formed with silicon epitaxy structure on the semiconductor base of logic gate side wall two sides.
Optionally, the logic gate side wall is formed by side wall technique three times, the technique of side wall three times respectively with it is described
The side wall nitride layer of first side wall, the side wall oxide layer of second side wall and second side wall is same technique；Removal institute
When stating side wall nitride layer and the hard mask layer, the outermost layer of the logic gate side wall is also removed.
Optionally, it is also formed on the semiconductor base positioned at the selection rhythmic structure of the fence of the memory block and covering
The selection grid side wall of the selection rhythmic structure of the fence side surface.
Optionally, selection grid side wall formation formed by side wall technique three times, the technique of side wall three times respectively with it is described
The side wall nitride layer of first side wall, the side wall oxide layer of second side wall and second side wall is same technique；Removal institute
When stating side wall nitride layer and the hard mask layer, the outermost layer of the selection grid side wall is also removed.
Optionally, the material of the side wall nitride layer is silicon nitride, and the material of the side wall oxide layer is silica.
The forming method of SONOS device provided by the invention includes the ONO layer to be formed on the semiconductor base, position
In the polysilicon layer on the ONO layer and the hard mask layer on the polysilicon layer, the ONO layer includes along far from institute
Tunnel oxide, charge storage layer and barrier oxide layer that the direction of semiconductor substrate surface is sequentially overlapped are stated, is then formed
The first side wall of the side surface of the polysilicon layer and the hard mask layer is covered, and etches quilt using anisotropic etch process
The exposed ONO layer, with remove corresponding region the barrier oxide layer and the charge storage layer, then execute LDD note
Enter, eventually forms the second side wall of the side surface and the remaining ONO layer that cover first side wall.
Wherein, after forming the first side wall, the ONO layer that is exposed is etched using anisotropic etch process, and utilizes the
Two side walls cover remaining ONO layer, so that for storing the charge storage layer of charge by the second side wall below the polysilicon layer
It protects, helps avoid subsequent etching in the process to the over etching of charge storage layer, improve the reliability of device；And by
It is protected in the charge storage layer by the second side wall, the difficulty of technology controlling and process when can reduce subsequent etching.
In addition, the etching carried out to the ONO layer that is exposed and the LDD then executed inject, be all to the same area into
Row processing, therefore, the photolithographic reticle needed when performing etching to the ONO layer being exposed can be using LDD injections in prior art
When light shield, do not increase the forming method of SONOS device provided by the invention by light shield referring now to prior art additionally, control
Process costs；Also, LDD injection is followed by executed performing etching to the ONO layer being exposed, no longer needs to inject in LDD and advance
Row photoetching, simplifies production technology.
Finally, the forming method of SONOS device provided by the invention is before forming the second side wall to the ONO layer being exposed
It is etched, so that the second side wall produces protective effect to charge storage layer, is not related to its in prior art
The influence of his region technique is conducive to the stability for maintaining production technology.
Detailed description of the invention
Fig. 1 is the flow diagram of the forming method of SONOS device provided in an embodiment of the present invention.
Fig. 2A is the cross-section structure signal after executing step S1 in the forming method of the SONOS device of the embodiment of the present invention
Figure.
Fig. 2 B is the cross-section structure signal after executing step S2 in the forming method of the SONOS device of the embodiment of the present invention
Figure.
Fig. 2 C is the cross-section structure signal after executing step S3 in the forming method of the SONOS device of the embodiment of the present invention
Figure.
Fig. 2 D is the cross-section structure signal after executing step S5 in the forming method of the SONOS device of the embodiment of the present invention
Figure.
Fig. 2 E is the cross-section structure signal after executing step S6 in the forming method of the SONOS device of the embodiment of the present invention
Figure.
Fig. 3 A is that the logic area of the embodiment of the present invention executes the schematic diagram of the section structure after step P1.
Fig. 3 B is that the logic area of the embodiment of the present invention executes the schematic diagram of the section structure after step P2.
Fig. 3 C is that the logic area of the embodiment of the present invention executes the schematic diagram of the section structure after step P3.
Fig. 3 D is that the logic area of the embodiment of the present invention executes the schematic diagram of the section structure after step P4.
Fig. 3 E is that the logic area of the embodiment of the present invention executes the schematic diagram of the section structure after step P5.
Drawing reference numeral is described as follows:
I-selection area under control；II-storage area under control；III-logic area；
4-photoresists；10,30-semiconductor base；11-ONO layers；12-polysilicon layers；13-hard mask layers；14—
The first side wall of storage tube；15-the second side walls of storage tube；21-selection grid oxide layers；22-selection grid layer；23-selection grid masks
Layer；24-the first side walls of selection grid；25-the second side walls of selection grid；31-logic grid oxide layers；32-logic grid layer；33-logics
Grid mask layer；34-the first side walls of logic gate；35-the second side walls of logic gate；36-silicon epitaxy structures；37-oxidation film layers；
111-tunnel oxides；112-charge storage layers；113-barrier oxide layers；151-storage tube side wall oxide layers；152-deposit
Store up pipe side wall nitride layer；251-selection grid side wall oxide layers；252-selection grid side wall nitride layers；301-body silicon layers；302—
Buried oxide layer；303-top layer silicons；351-logic gate side wall oxide layers；352-logic gate side wall nitride layers.
Specific embodiment
A specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following description,
Advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate
Ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
In the forming method of existing SONOS device, when the silicon nitride to side wall carries out wet etching, due to isotropism
The characteristics of, will lead in ONO layer for store electronics charge storage layer it is also laterally etched, the reliability of product drops
It is low, or even cause SONOS component failure.In view of the above technical problems, the embodiment of the present invention proposes a kind of shape of SONOS device
At method, Fig. 1 is the flow diagram of the forming method of SONOS device provided in an embodiment of the present invention.As shown in Figure 1, described
The forming method of SONOS device the following steps are included:
Step S1: the ONO layer being located on semiconductor base, the polysilicon layer on the ONO layer are formed and is located at
Hard mask layer on the polysilicon layer, the ONO layer include being sequentially overlapped along the direction far from the semiconductor substrate surface
Tunnel oxide, charge storage layer and barrier oxide layer, the width of the ONO layer is greater than the width of the polysilicon layer；
Step S2: the first side wall for covering the side surface of the polysilicon layer and the hard mask layer, the ONO layer are formed
Width be greater than the sum of first side wall and width of the polysilicon layer；
Step S3: etching the ONO layer that is exposed using anisotropic etch process, be exposed with removal described in
Barrier oxide layer and charge storage layer in ONO layer；
Step S4: then executing LDD injection, forms ion in the semiconductor base of the polysilicon layer two sides and is lightly doped
Area；
Step S5: forming the second side wall, and second side wall covers the side surface of first side wall and remaining described
ONO layer.
The forming method of SONOS device provided in an embodiment of the present invention is carved after forming the first side wall using anisotropy
The ONO layer of etching technique etching exposure, and the remaining ONO layer is covered using the second side wall, so that the electricity for storing charge
Lotus accumulation layer is protected by the second side wall, is helped avoid subsequent etching process over etching charge storage layer, is improved device
Reliability, and the difficulty of technology controlling and process when reducing subsequent etching.
It describes in detail with reference to the accompanying drawing to the forming method of the SONOS device of the present embodiment.
Fig. 2A is the cross-section structure signal after executing step S1 in the forming method of the SONOS device of the embodiment of the present invention
Figure.In conjunction with Fig. 1 and Fig. 2A, step S1 is first carried out, forms the ONO layer 11 being located on semiconductor base 10, be located at the ONO layer
Polysilicon layer 12 on 11 and the hard mask layer 13 on the polysilicon layer 12, the ONO layer 11 include along far from institute
State tunnel oxide 111, charge storage layer 112 and barrier oxide layer that the direction on 10 surface of semiconductor base is sequentially overlapped
113, the width of the ONO layer 11 is greater than the width of the polysilicon layer 12.
In the present embodiment, semiconductor substrate surface definition has memory block and logic area III.The memory block includes selection again
Area under control I and storage area under control II, are for respectively forming the selecting pipe structure and storage tube structure of the SONOS device；The logic
Area III is used to form logical device.
Semiconductor base 10 is the semiconductor base of memory block, and surface definition has selection area under control I and storage area under control II.Partly lead
The material of body substrate 10 can be silicon, germanium, SiGe or silicon carbide etc., be also possible to cover silicon (SOI) or insulator on insulator
On cover germanium (GOI), or can also be III, V compounds of group such as other materials, such as GaAs.Semiconductor base 10 may be used also
To inject certain Doped ions according to design requirement to change electrical parameter.
As shown in Figure 2 A, in the present embodiment, it is partly led on the semiconductor base 10 in the selection area under control I along far from described
The direction of body substrate 10 is sequentially formed with including selection grid oxide layer 21 and the selection grid structure of grid layer 22 and selection grid is selected to cover
Mold layer 23.The width of the selection grid oxide layer 21 is greater than the width of the selection grid layer 22.
Fig. 3 A is that logic area executes the schematic diagram of the section structure after step P1, as shown in Figure 3A, executes step in memory block
Before S1, the present embodiment also performs step P1 in logic area III: formed be located at 30 31 layers of logic grid oxygen on semiconductor base,
Logic grid layer 32 and formation on the logic grid oxide layer 31 are located at the logic gate mask layer in the logic grid layer 32
33。
The semiconductor base 30 of the logic area III is FDSOI structure, has one layer of buried sio and one layer of ultrathin insulating
Silicon on body, body silicon layer 301, the buried oxide layer 302 positioned at middle part and the top layer silicon 303 positioned at top including being located at bottom.Due to
The presence of buried oxide layer 302, so that on the one hand the device with FDSOI structure has preferable isolation characteristic, it on the other hand can be with
The modulation of threshold voltage is carried out by changing body-bias.In addition, being formed in ultra-thin top layer silicon 303 in FDSOI structure ultra-thin
Transistor can control short-channel effect well, and then can reduce supply voltage, be operated by flexible backgate, work electricity
Pressure can drop to 0.4V, and the leakage current of MOS device is less than 0.1pA/ μm, is very suitable to the exploitation of low-power consumption product.The present invention is real
Mixing can be formed in conjunction with the SONOS device that memory block is formed by applying manufacture of the example by FDSOI technical application in logical device
Embedded flash memory product, in power consumption and the great competitiveness of aspect of performance.
In the present embodiment, the logic grid oxide layer 31 and logic grid layer 32 form logic gate structures, the logic gate
The width of oxygen layer 31 is greater than the width of the logic grid layer 32.
In the present embodiment, the tunnel oxide 111, barrier oxide layer 113, selection grid oxide layer 21, buried oxide layer 302 with
And the material of logic grid oxide layer 31 is, for example, silica, the charge storage layer 112, hard mask layer 13, selection grid mask layer 23
And the material of logic gate mask layer 33 is, for example, silicon nitride.
Fig. 2 B is the cross-section structure signal after executing step S2 in the forming method of the SONOS device of the embodiment of the present invention
Figure.In conjunction with Fig. 1 and Fig. 2 B, step S2 is executed, form the covering polysilicon layer 12 in the storage area under control II and described is covered firmly
The width of the first side wall of storage tube 14 of the side surface of mold layer 13, the ONO layer 11 is greater than 14 He of the first side wall of storage tube
The sum of the width of the polysilicon layer 13.In the present embodiment, in the forming method flow diagram of SONOS device shown in Fig. 1
" the first side wall " refer to is exactly the first side wall of storage tube 14.
By step S2, first side wall of storage tube 14 is formed in 12 upper surface of ONO layer, and in the storage tube
The two sides of first side wall 14 respectively expose a part of ONO layer 11.
It as shown in Figure 2 B, can be simultaneously in selection area under control I when storage area under control II forms first side wall 14 of storage tube
The first side wall of selection grid 24 of the covering selection grid layer 22 and selection grid mask layer 23 is formed, it is in the present embodiment, selected
The width for selecting grid oxide layer 21 is greater than the sum of the width of first side wall of selection grid 24 and the selection grid layer 22, therefore selects
The first side wall of grid 24 is formed in 21 upper surface of selection grid oxide layer, and in each exposure in two sides of first side wall of selection grid 24
A part selection grid oxide layer 21 out.
Fig. 3 B is that logic area executes the schematic diagram of the section structure after step P2.As shown in Figure 3B, step is executed in memory block
Step P2 is executed in logic area III while S2: forming the logic gate for covering the logic grid layer 32 and logic gate mask layer 33
First side wall 34.
In the present embodiment, the width of institute's logic grid oxide layer 31 is greater than first side wall of logic gate 34 and described patrols
The sum of the width of grid layer 32 is collected, therefore the first side wall of logic gate 34 is formed in 31 upper surface of logic grid oxide layer, and patrols described
The two sides for collecting the first side wall of grid 34 respectively expose a part of logic grid oxide layer 31.
Specifically, the material of first side wall of storage tube 14, the first side wall of selection grid 24 and the first side wall of logic gate 34
Material is, for example, carbon containing silicon nitride, helps to make first side wall of storage tube 14, the first side wall of selection grid 24 and logic gate
The structure of first side wall 34 is finer and close, subsequent etching hard mask layer 13, selection grid mask layer 23, logic gate mask layer 33 and
When the silicon nitride material being additionally formed, the first side wall of storage tube 14, the first side wall of selection grid 24 and the first side wall of logic gate 34
It is not easy the destruction that is etched.Form first side wall of storage tube 14, the first side wall of the first side wall of selection grid 24 and logic gate
34 method is, for example, atomic layer deposition (ALD).
Fig. 2 C is the cross-section structure signal after executing step S3 in the forming method of the SONOS device of the embodiment of the present invention
Figure.In conjunction with Fig. 1 and Fig. 2 C, step S3 is executed, etches the ONO layer 11 being exposed, using anisotropic etch process to go
Except the barrier oxide layer 113 and charge storage layer 112 in the ONO layer 11 being exposed.
As shown in Figure 2 C, before etching, photoetching is carried out, so that photoresist 4 is covered memory block and logic area III, and pass through exposure
Open storage area under control II.
The anisotropic etch process used in the present embodiment is dry etching.Generally when carrying out dry etching, Chang Cai
With stopping and the arrival time stopping two ways of reaching home.Stopping mode of reaching home is to be not provided with etch period, but sharp
Stop etching again after the completion of the material that will be etched all etches with the terminal detecting function of dry etching equipment.Arrival time stops
Mode is setting etch period, and etches in setting etch period.In the present embodiment, it needs that storage tube first will be exposed to
Charge storage layer 112 in the ONO layer 11 of 14 two sides of side wall etches removal, due in ONO layer 11 for example including silica and nitrogen
The mixing lamination of SiClx, if be difficult to through the selection to material by the way of stopping of reaching home so that plasma
Bottom is stopped at after etching barrier oxide layer 113 (for example, silica) and charge storage layer 112 (for example, silicon nitride) simultaneously
Tunnel oxide (for example, silica) on.Therefore, it preferably performs etching, etches in such a way that arrival time stops here
Dwell time is preferably after etched charge storage layer 112 to tunneling through before oxide layer 111 etched.Retain part
On the one hand tunnel oxide 111 makes etching process convenient for control, prevents etching from having an impact to semiconductor base 10；In addition have
Help protect semiconductor base 10 in the subsequent process, prevents its exposed.In another embodiment of the invention, when etching stopping
Between be also possible to tunnel through when the etching of oxide layer 111 completes, at this point, in order to protect exposed semiconductor base 10, Ke Yi
Thermal anneal process is carried out after having etched tunnel oxide 111, forms protective oxide film on 10 surface of semiconductor base.
In etching process, the region other than 4 pairs of photoresist storage areas under control II stops, and hard mask layer 13 is to polysilicon
Layer 12 is stopped.Although the hard mask layer 13 and the first side wall of storage tube 14 that expose also will receive etching, due to
ONO layer 11 is relatively thin relative to hard mask layer 13 and storage tube the first side wall 14, etching is easy, therefore, by certain time
Etching, hard mask layer 13 and the first side wall of storage tube 14 are etched away sub-fraction, and remaining hard mask layer 13 still can be used as
Barrier layer prevents plasma from having an impact to polysilicon layer 12.
By step S3, by the charge storage layer in the extra ONO layer 11 for being exposed to 14 two sides of the first side wall of storage tube
112 etching removals.
Then C referring to Figures 1 and 2 executes step S4, then execute LDD injection, the half of 12 two sides of polysilicon layer
Ion lightly doped district is formed in conductor substrate 10.
Under the blocking of photoresist 4, continue to execute the storage area under control II exposed LDD injection, LDD injects under this step
Region it is identical as the region that step S3 plasma etches, that is, be storage area under control II.Thus, before carrying out LDD injection,
It no longer needs to carry out section of the photoetching to redefine LDD injection, simplifies production technology；In addition, region and the step of LDD injection
The region of S3 plasma etching is identical, therefore, the photoetching needed when being performed etching in step S3 to the ONO layer 11 being exposed
Light shield when light shield can be using LDD injection, makes the forming method of SONOS device provided in an embodiment of the present invention referring now to existing
Technique does not increase light shield additionally, controls process costs.
After having executed LDD injection, photoresist 4 is removed.
Fig. 2 D is the cross-section structure signal after executing step S5 in the forming method of the SONOS device of the embodiment of the present invention
Figure.D referring to Figures 1 and 2 executes step S5, forms the second side wall of storage tube 15, described storage tube second side in storage area under control II
Wall 15 cover first side wall of storage tube 14 side surface and the remaining ONO layer 11.In the present embodiment, shown in Fig. 1
What " the second side wall " in the forming method flow diagram of SONOS device referred to is exactly the second side wall of storage tube 15.
In the present embodiment, second side wall of storage tube 15 includes storage tube side wall oxide layer 151 and storage tube side wall nitrogen
Change layer 152, the storage tube side wall oxide layer 151 covers the side surface of first side wall of storage tube 14 and remaining described
ONO layer 11, the storage tube side wall nitride layer 152 cover the storage tube side wall oxide layer 151.Specifically, in the present embodiment
In, the section of the storage tube side wall oxide layer 151 is, for example, L shape, i.e., the described storage tube side wall oxide layer 151, which is both covered on, deposits
The side surface for storing up the first side wall of pipe 14, remaining charge storage layer 112 and barrier oxide layer 113 is also covered on storage tube the
The upper surface for the tunnel oxide 111 exposed of one side wall, 14 two sides not being etched.In another embodiment of the present invention, deposit
Storing up pipe side wall oxide layer 151 is the upper surface for being covered on protective oxide film.The section example of the storage tube side wall nitride layer 152
The triangle for for example filling the L shape opening of the storage tube side wall oxide layer 151, covers the storage tube side wall oxide layer 151
Side surface and upper surface.Second side wall of storage tube 15 has wrapped the charge storage layer of 12 lower part of polysilicon layer from two sides
112, so that charge storage layer 112 is protected, to help avoid charge storage layer in subsequent carry out wet etching
112 etching by etching liquid improves device reliability.
As shown in Figure 2 D, while forming the second side wall of storage tube 15, selection can also be formed in selection area under control I
The second side wall of grid 25, second side wall of selection grid 25 cover first side wall of selection grid 24 side surface and the choosing
Select the upper surface of the selection grid oxide layer 21 of 24 two sides of the first side wall of grid.Second side wall of selection grid 25 includes covering positioned inside
Cover the selection grid side wall oxide layer of the side surface of first side wall of selection grid 24 and the upper surface of the selection grid oxide layer 21
251, and the selection grid side wall nitride layer 252 of the covering selection grid side wall oxide layer 251 positioned at outside.
In addition, Fig. 3 C is that logic area executes the schematic diagram of the section structure after step P3, before memory block executes step S5,
Step P3 also is performed in logic area III: forming the second side wall of logic gate 35 in logic area III.
Second side wall of logic gate 35 covers side surface and the logic gate of first side wall of logic gate 35
The upper surface of the logic grid oxide layer 31 of one side wall, 34 two sides.Second side wall of logic gate 35 includes described in the covering positioned inside
The logic gate side wall oxide layer 351 of the side surface of the first side wall of logic gate 34 and the upper surface of the logic grid oxide layer 31, with
And the logic gate side wall nitride layer 352 of the covering logic gate side wall oxide layer 351 positioned at outside.
In the present embodiment, the storage tube side wall oxide layer 151, selection grid side wall oxide layer 251 and logic gate side wall
The material of oxide layer 351 is, for example, silica, the storage tube side wall nitride layer 152, selection grid side wall nitride layer 252 and is patrolled
Collecting grid side wall nitride layer 352 is, for example, silicon nitride.
Form the storage tube side wall oxide layer 151, selection grid side wall oxide layer 251 and logic gate side wall oxide layer
351 can be used chemical vapor deposition (CVD), formed the storage tube side wall nitride layer 152, selection grid side wall nitride layer 252 with
And it is hallow cathode deposition, HCD (HCD) that logic gate side wall nitride layer 352, which can be used, and certainly, the storage tube side wall oxide layer
151, selection grid side wall oxide layer 251, logic gate side wall oxide layer 351, the storage tube side wall nitride layer 152, selection grid side
Other public technologies that wall nitration case 252 and logic gate side wall nitride layer 352 also can use this field are formed.
In addition, Fig. 3 D is that logic area III executes the schematic diagram of the section structure after step P4, step is performed in logic area III
After P3, logic area also performs step P4: forming silicon epitaxy on the semiconductor base of 35 two sides of the second side wall of logic gate
Structure 36.
Specifically, removing outermost the second side wall of part logic gate 35 first with such as dry etching, part is exposed
Then logic grid oxide layer 31 is removed the logic grid oxide layer 31 being exposed using such as wet etching, exposes Portions of top layer silicon
303, epitaxial growth then is carried out to top layer silicon 303, obtains silicon epitaxy structure 36, finally utilizes wet-cleaning, rapid thermal oxidation
Technique is to protect exposed silicon epitaxy structure 36, so that 36 surface of silicon epitaxy structure forms oxidation film layer 37.
Fig. 2 D is the cross-section structure signal after executing step S6 in the forming method of the SONOS device of the embodiment of the present invention
Scheme, referring to Figures 1 and 2 D, after forming the second side wall of storage tube 15, the SONOS device forming method of the present embodiment can also be wrapped
It includes step S6: removing the hard mask layer 13 and storage tube side wall nitride layer 152.
In the present embodiment, the material of the hard mask layer 13 and storage tube side wall nitride layer 152 is silicon nitride, therefore,
It can be using wet-etching technology removal hard mask layer 13 and storage tube side wall nitride layer 152, when carrying out wet etching, preferably
Use the etching selection ratio to silicon nitride for high wet etching liquid, such as silicon nitride etch liquid, to prevent from producing other structures
It is raw to influence.Since the second side wall of storage tube 15 has wrapped from two sides the charge storage layer 112 of 12 lower part of polysilicon layer, thus
When carrying out silicon nitride wet etching, technique control can be reduced to avoid charge storage layer 112 also by the laterally etched of etching liquid
The difficulty of system, and improve the reliability of device.
In the hard mask layer 13 and storage tube side wall nitride layer 152 in removal storage area under control II, also removal selects area under control I
Selection grid mask layer 23 and selection grid side wall nitride layer 252.
In Fig. 3 E logic area execute step P5 after the schematic diagram of the section structure, memory block execute step S6 simultaneously as
Wet etching be it is isotropic, the logic area III also performs step P5: the logic gate mask layer 33 of removal logic area III
And logic gate side wall nitride layer 352.
In the present embodiment, first side wall of storage tube 14, the first side wall of the first side wall of selection grid 24 and logic gate
34 be carbon containing silicon nitride, so that the first side wall of storage tube 14, the first side wall of selection grid 24 and the first side wall of logic gate 34 are not
It is easily etched and removes by silicon nitride etch liquid.
Meanwhile in memory block execution step S6 and after logic area III executes P5, to selection area under control I and logic area III
LDD injection is carried out respectively, can form the SONOS device and logical device in conjunction with FDSOI technology and SONOS technique.
The embodiment of the present invention after forming the first side wall of storage tube, utilizes anisotropy when carrying out the technique in storage area under control
Etching technics etches the ONO layer being exposed, and covers remaining ONO layer using the second side wall of storage tube, so that the polysilicon
Layer lower section is protected for storing the charge storage layer of charge by the second side wall of storage tube, is helped avoid subsequent wet process and is carved
To the laterally etched of charge storage layer during erosion, the reliability of SONOS device is improved；And due to the charge storage layer quilt
The second side wall of storage tube protects, and can reduce the difficulty of technology controlling and process when subsequent wet etches.
In addition, the etching carried out to the ONO layer that is exposed and the LDD then executed inject, be all to the same area into
Row processing, therefore, the photolithographic reticle needed when performing etching to the ONO layer being exposed can be using LDD injections in prior art
When light shield, do not increase the forming method of SONOS device provided by the invention by light shield referring now to prior art additionally, control
Process costs；Also, LDD injection is followed by executed performing etching to the ONO layer being exposed, no longer needs to inject in LDD and advance
Row photoetching, simplifies production technology.
Finally, the forming method of SONOS device provided in an embodiment of the present invention is right before forming the second side wall of storage tube
The ONO layer being exposed is etched, so that the second side wall of storage tube produces protective effect to charge storage layer, not
It is related to the influence to area under control and logic area technique is selected in prior art, is conducive to the stability for maintaining production technology.
The above is only a preferred embodiment of the present invention, not to the restriction of interest field of the present invention.Any art technology
The technical staff in field, without departing from the spirit and scope of the present invention, can to the invention discloses technical solution and skill
Art content makes the variation such as any type of equivalent replacement or modification.Therefore, anything that does not depart from the technical scheme of the invention, according to
According to technical spirit any simple modifications, equivalents, and modifications to the above embodiments of the invention, the present invention is belonged to
Protection scope within.
Claims (11)
1. a kind of forming method of SONOS device characterized by comprising
It forms the ONO layer being located on semiconductor base, the polysilicon layer on the ONO layer and is located at the polysilicon layer
On hard mask layer, the ONO layer include along far from the semiconductor substrate surface direction be sequentially overlapped tunnel oxide,
Charge storage layer and barrier oxide layer, the width of the ONO layer are greater than the width of the polysilicon layer；
The first side wall for covering the side surface of the polysilicon layer and the hard mask layer is formed, the width of the ONO layer is greater than
The sum of first side wall and the width of the polysilicon layer；
The ONO layer being exposed is etched, using anisotropic etch process to remove the blocking in the ONO layer being exposed
Oxide layer and charge storage layer；
Then LDD injection is executed, forms ion lightly doped district in the semiconductor base of the polysilicon layer two sides；And
Form the second side wall, second side wall cover first side wall side surface and the remaining ONO layer.
2. the forming method of SONOS device as described in claim 1, which is characterized in that etch the ONO layer being exposed
When, also remove the tunnel oxide in the ONO layer being exposed.
3. the forming method of SONOS device as claimed in claim 2, which is characterized in that etch the ONO layer that is exposed it
Afterwards, before executing LDD injection, thermal anneal process is carried out, forms protective oxide film in the semiconductor substrate surface.
4. the forming method of SONOS device as described in claim 1, which is characterized in that second side wall includes side wall oxygen
Change layer and side wall nitride layer, the side wall oxide layer cover first side wall side surface and the remaining ONO layer, it is described
Side wall nitride layer covers the side wall oxide layer.
5. the forming method of SONOS device as claimed in claim 4, which is characterized in that it further include utilizing wet-etching technology,
Remove the side wall nitride layer and the hard mask layer.
6. the forming method of SONOS device as claimed in claim 5, which is characterized in that the semiconductor substrate surface definition
There are memory block and logic area, the ONO layer is located at the memory block, and the logic area is used to form logical device, corresponds to institute
The semiconductor base for stating logic area is FDSOI structure.
7. the forming method of SONOS device as claimed in claim 6, which is characterized in that the logical device includes logic gate stack
Structure and cover logic rhythmic structure of the fence side surface logic gate side wall, logic gate side wall two sides it is semiconductor-based
Silicon epitaxy structure is formed on bottom.
8. the forming method of SONOS device as claimed in claim 7, which is characterized in that the logic gate side wall passes through side wall three times
Technique is formed, the technique of side wall three times respectively with first side wall, the side wall oxide layer of second side wall and described
The side wall nitride layer of two side walls is same technique；When removing the side wall nitride layer and the hard mask layer, also patrolled described in removal
Collect the outermost layer of grid side wall.
9. the forming method of SONOS device as claimed in claim 6, which is characterized in that be also formed with position on the semiconductor base
Selection grid side wall in the selection rhythmic structure of the fence of the memory block and the covering selection rhythmic structure of the fence side surface.
10. the forming method of SONOS device as claimed in claim 9, which is characterized in that selection grid side wall is formed by three times
Side wall technique is formed, the technique of side wall three times respectively with first side wall, the side wall oxide layer of second side wall and institute
The side wall nitride layer for stating the second side wall is same technique；When removing the side wall nitride layer and the hard mask layer, institute is also removed
State the outermost layer of selection grid side wall.
11. such as the forming method of the described in any item SONOS devices of claim 4 to 10, which is characterized in that the side wall nitride
The material of layer is silicon nitride, and the material of the side wall oxide layer is silica.
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| CN110867380A (en) * | 2019-11-27 | 2020-03-06 | 上海华力微电子有限公司 | Method for forming semiconductor device |
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