CN105511591B - Algorithm is adjusted based on the adaptive DVFS of dual threshold power consumption - Google Patents
Algorithm is adjusted based on the adaptive DVFS of dual threshold power consumption Download PDFInfo
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- G06F1/26—Power supply means, e.g. regulation thereof
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- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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Abstract
The present invention provides a kind of DVFS adjusting algorithm adaptive based on dual threshold power consumption, including obtains the utilization rate and power consumption of processing unit value of processor in real time；Whether the utilization rate of decision processor is within first order threshold value；If so, maintaining working frequency constant；And if it is not, then execute following steps：Whether the utilization rate of decision processor exceeds second level threshold value；If it is not, then adjusting frequency by the way of frequency dividing, and if so, execute following steps：Whether decision processor utilization rate is less than the lower limit of second level threshold value or the upper limit beyond second level threshold value and power consumption threshold value；If it is not, then adjusting frequency by the way of frequency dividing；If so, adjusting frequency by the way of phaselocked loop, while changing voltage value.The beneficial effects of the invention are as follows rationally utilize processor performance, reduction power consumption of processing unit.
Description
Technical field
The invention belongs to computerized algorithm technical fields, more particularly, to a kind of DVFS adaptive based on dual threshold power consumption
Adjust algorithm.
Background technology
DVFS technologies be it is a kind of for power consumption of processing unit optimization technology, mainly by adjust processor frequency with
Voltage by processor handle different loads task when under different performance levels.This technology had both needed processor hard
The support of part is also required to being used cooperatively for software.
In the processor for supporting DVFS, there are two types of modes for the voltage adjusting of hardware supported：It adjusts outside piece and is adjusted in piece.
Using the processor of adjuster outside piece when adjusting voltage, the stabilization time needed is long, and it is delicate to several to generally require tens
Ten milliseconds, still, advantage is also obvious, is exactly that power supply conversion efficiency is relatively high, maximum can reach 90%.But
It is that this relatively high power supply conversion efficiency has much relations with load, when output power is larger, power supply conversion efficiency phase
It is relatively high for.Exactly because the voltage regulative mode stabilization time outside piece is long, so using piece transferring machine
Unsuitable overfrequency when processor up-regulation section voltage.The time that voltage switches can be shortened to nanosecond by the mode adjusted in another piece
Grade provides very favorable condition for voltage switching time shorter in processor to realizing quickly to adjust.Although being adjusted in piece
Section device required switching time greatly reduces for adjuster outside piece, and still, power supply conversion ratio is comparatively
Want lower, usually between 70% to 80%.Moreover, the silicon area expense that regulative mode occupies inside processor in piece
It is bigger, about every watt 2mm2。
In the processor for supporting DVFS, there are two types of modes for the frequency adjusting of hardware supported：Frequency divider adjusts and phaselocked loop
It adjusts.Phaselocked loop adjusts both modes with frequency divider also respective advantage and disadvantage respectively.For phaselocked loop, from starting to adjust
Whole to need the time of a locking, also, within this time to finally settling out, clock signal output is likely to result in
Execute mistake.Therefore, in the processor for adjusting frequency using phaselocked loop, when adjusting frequency clock can be closed to go for a period of time
Wait for clock stable.And this time is generally more than tens microseconds.Therefore, when adjusting frequency using phaselocked loop, be not suitable for
It frequently adjusts, this also causes to be not suitable for fine granularity adjusting when designing DVFS algorithms.Frequency is adjusted relative to phaselocked loop, with frequency dividing
The mode that device is adjusted is then fast very much.Also, do not have locking time, it from receive signal to generate stablize output only need it is several
Clock cycle can complete.It is thereby achieved that more quick frequency is adjusted, still, acquired in this regulative mode
Frequency is possible to not 50% duty ratio.
Have on hardware after support DVFS technologies in processor, it is also necessary to which the related algorithm cooperation of software is adjusted.At present
The idle moment of processor is mainly detected in software adjustment, and the frequency of reduction processor is come with voltage at this moment
The power consumption of processor is reduced, and greater loss will not be caused to performance.DVFS is broadly divided into two major classes in software adjustment：One
Kind is the DVFS of closed loop, and another kind is the DVFS of open loop.When adjusting using the DVFS of open loop, can generally consider specifically to work
Situation.Need the matching status meeting point of the voltage that better work is previously set and frequency.When processor is running certain answer
When with program, some necessary information are acquired in real time, and combine relevant control and regulation algorithm, finally selected according to the result of algorithm
Take a preset proper operation state.However, in the DVFS of closed loop is adjusted, mainly a kind of adaptive voltage frequency
It adjusts, there are one the Network Performance Monitor of delay sampling, this monitor and power supply control voltage module and places inside processor
Manage the system that device frequency control module forms a closed loop.When running program, Network Performance Monitor acquires some necessary information
The final suitable operating voltage of processor and frequency are determined to integrate.Open loop adjusts maximum area with closed loop DVFS in processor
It is not, either with or without the value of pre-set voltage and frequency.It, can pre-set a series of voltage in open cycle system
Frequency values, by the processor information of acquisition, reasonably select pre-set frequency and voltage when running program.So
And in closed-loop system, there is no pre-set frequencies and voltage value, are all to pass through performance monitoring when processor works
Device collects information, to predict and judge the most suitable running frequency of current processor and operating voltage, then further according to corresponding
Algorithm be adjusted.This is the process of a Hardware/Software Collaborative Design, and is designed considerably complicated.There are one non-at present
Often perfect being capable of the general DVFS methods adjusted using closed loop.So most of DVFS are still based on open loop.
Invention content
The purpose of the invention is to overcome the shortage of prior art, a kind of DVFS adaptive based on dual threshold power consumption is provided
Algorithm is adjusted, processor performance is rationally utilized, reduces power consumption of processing unit.
The technical scheme is that：A kind of DVFS adjusting algorithm adaptive based on dual threshold power consumption, including：
The utilization rate and power consumption of processing unit value of processor are obtained in real time；
Whether the utilization rate of decision processor is within first order threshold value；
If so, maintaining working frequency constant；And if it is not, then execute following steps：
Whether the utilization rate of decision processor exceeds second level threshold value；
If it is not, then adjusting frequency by the way of frequency dividing, and if so, execute following steps：
Whether decision processor utilization rate is less than the lower limit of second level threshold value or the upper limit beyond second level threshold value and work(
Consume threshold value；
If it is not, then adjusting frequency by the way of frequency dividing；If so, frequency is adjusted by the way of phaselocked loop, same to time-varying
More voltage value.
Further, the utilization rate and working frequency of the processor are proportionate.
Further, the first order threshold value, second level threshold value and power consumption threshold value are by the adjusting interval division of the processor
For six, when the utilization rate of processor is in first order threshold value, then maintain working frequency constant, if processor utilization
When between first order bottom threshold and second level bottom threshold, just frequency is reduced rapidly by the way of frequency dividing；If place
When managing device utilization rate between first order upper threshold and second level upper threshold, the mode that frequency dividing is adjusted just is taken to rise rapidly
High-frequency.
Further, when the upper limit of the processor utilization beyond second level threshold value but power consumption will be taken less than power consumption threshold value
The mode that frequency dividing adjusts frequency increases frequency, if being the highest frequency under the voltage at this time, continues to maintain this
Frequency.
Further, if processor utilization exceeds second level threshold value, and the power consumption of processor has exceeded power consumption at this time
Threshold value then takes the mode of phaselocked loop to increase processor reference frequency, and needs before adjusting frequency first to increase voltage, protects
The voltage of card at this time can normally support required new frequency.
Further, it if processor utilization is less than the lower limit of second level threshold value, is reduced by the way of phaselocked loop
Processor reference frequency, and processor voltage is reduced again after reducing frequency.
Further, the first order threshold value is included in the second level threshold value, and the power consumption threshold value is more than second level threshold
It is worth the upper limit.
Further, when the processor is multinuclear, the processor can be divided into multiple clusters, include in each cluster
Single or multiple cores, if multiple cores of the processor need frequency modulation simultaneously, in the cluster that multinuclear is formed, once have
The processor utilization of one core is more than first order threshold value, the upper limit value of second level threshold value or power consumption threshold value, then by the core
The entire cluster frequency upgrading at place is to reference frequency.
The invention has the advantages and positive effects that：Due to the adoption of the above technical scheme, using processor utilization
Bipolar threshold controls, and processor performance can be allowed to get the more reasonable use under dual limitation.Relative to traditional single threshold
For algorithm, this dual threshold can start frequency modulation mechanism when processor utilization is more than first order threshold value, can be as soon as possible
The Properties Control of processor in rational range.When more than second level threshold value, second set of frequency modulation scheme can also be started
Control processor performance again.Therefore, the regulative mode of this dual threshold has and controls in advance, the double compression subsequently coordinated
Feature can achieve the purpose that preferably to utilize processor performance.
Description of the drawings
Fig. 1 is that the DVFS adaptive based on dual threshold power consumption of the present invention adjusts the flow chart of algorithm；
Fig. 2 is that the processor of the present invention adjusts section structural schematic diagram.
Specific implementation mode
It elaborates below in conjunction with the accompanying drawings to the present invention.
If the DVFS adaptive based on dual threshold power consumption of Fig. 1 present invention is adjusted shown in the flow chart of algorithm, the present invention carries
Algorithm is adjusted for a kind of DVFS adaptive based on dual threshold power consumption, including：
Step 101, the utilization rate and power consumption of processing unit value of processor are obtained in real time.
Step 102, whether the utilization rate of decision processor is within first order threshold value；If so, maintaining working frequency not
Become；And if it is not, then execute following steps：
Step 103, whether the utilization rate of decision processor exceeds second level threshold value；If it is not, then using frequency dividing by the way of tune
Frequency is saved, and if so, executes following steps：
Step 104, whether decision processor utilization rate is less than the lower limit of second level threshold value or beyond second level threshold value
The upper limit and power consumption threshold value；If it is not, then adjusting frequency by the way of frequency dividing.
Step 105, if so, adjusting frequency by the way of phaselocked loop, while voltage value is changed.
The utilization rate and working frequency of the processor are proportionate.
Working frequency can be increased with the raising of utilization rate, and be reduced with the decline of utilization rate.In general,
When processor executes the application program of the low utilization rates such as word processing, web browsing or other 2D drawing, it is only necessary to lower
Working frequency can satisfy the use demand to run.On the contrary, when processor executes 3D drawing, video code conversion, decompression or trip
When the application program of high utilization rate such as software of playing, then must greatly improve working frequency could meet use under high load condition
Demand.Therefore, there is corresponding relationship, that is to say, that according to utilization rate model between the working frequency and utilization rate of processor
The difference enclosed, processor can be operated with corresponding working frequency respectively, appropriate to provide under different utilization rates
Working frequency, whole energy consumption when processor being made to run reduce.Namely processor, can under the use state of different utilization rates
With the preferred working frequency of use, to high-effect be operated under energy-efficient pattern having both.Wherein, working frequency and use
The matching relationship of rate can be but be not limited to：37.5% working frequency corresponds to 10% utilization rate below, 62.5%
Working frequency correspond to the utilization rate of 10-40%, 75% working frequency correspond to the utilization rate of 41-60%, 87.5% work frequency
Rate corresponds to the utilization rate of 61-80% and 100% working frequency corresponds to the utilization rate etc. of 81-100%.
The adjusting section of the processor has been divided into six by the first order threshold value, second level threshold value and power consumption threshold value
It is a, when the utilization rate of processor is in first order threshold value, then maintain working frequency constant, if processor utilization is between
When between level-one bottom threshold and second level bottom threshold, just frequency is reduced rapidly by the way of frequency dividing；If processor is sharp
When with rate between first order upper threshold and second level upper threshold, the mode that frequency dividing is adjusted just is taken to increase frequency rapidly
Rate.
When the upper limit of the processor utilization beyond second level threshold value but power consumption will be less than power consumption threshold value, and frequency dividing is taken to adjust
The mode of frequency increases frequency, if being the highest frequency under the voltage at this time, continues to maintain this frequency.
If processor utilization exceeds second level threshold value, and the power consumption of processor has exceeded power consumption threshold value at this time, then
It takes the mode of phaselocked loop to increase processor reference frequency, and needs before adjusting frequency first to increase voltage, ensure at this time
Voltage can normally support required new frequency.
If processor utilization is less than the lower limit of second level threshold value, processor base is reduced by the way of phaselocked loop
Quasi- frequency, and processor voltage is reduced again after reducing frequency.
The first order threshold value is included in the second level threshold value, and the power consumption threshold value is more than second level upper threshold.
When the processor is multinuclear, the processor can be divided into multiple clusters, in each cluster comprising single or
The multiple cores of person, if multiple cores of the processor need frequency modulation simultaneously, in the cluster that multinuclear is formed, once there are one cores
Processor utilization be more than first order threshold value, the upper limit value of second level threshold value or power consumption threshold value, then by where the core
Entire cluster frequency upgrading is to reference frequency.
By taking 16 core processors as an example.Its 16 cores are averagely divided into 4 parts, each partly account for 4 cores, this 4
A karyomorphism is at a cluster, when adjusting frequency, can be adjusted into the frequency dividing of line frequency as unit of cluster.Voltage and reference frequency
Adjusting is using entire chip as granularity.
When the processor is multinuclear, the present embodiment adjusts the implementation of algorithm based on the adaptive DVFS of dual threshold power consumption
Steps are as follows：
Step 201, the adaptive DVFS of dual threshold power consumption is opened to adjust.
Step 202, the utilization rate of each core and the power consumption number of current processor are obtained, and calculates the place inside each cluster
Manage device utilization rate average value.Search whether that the utilization rate of some core is more than preset value.If so, just will be where the core
Cluster rises to reference frequency by way of dividing and adjusting.If there is not the case where monokaryon utilization rate is more than preset value,
It is carried out in next step.
The preset value can be set with processor performance, can be set as 95% herein.
Step 203, judge each cluster, if the average utilization for some cluster inner core occur is more than first order threshold value
Section, the section of first order threshold value if more than, but it is not above the section of second level threshold value, then, just using frequency dividing
The mode of adjusting carries out frequency reducing to the cluster or raising frequency is handled.If the average utilization of cluster inner core is less than first order threshold
The section of value then maintaining the frequency of the cluster constant, but if having exceeded second level threshold value, is carried out in next step.
Step 204, if the average utilization of all clusters is below the lower limit of second level threshold value, pass through phaselocked loop first
Regulative mode reduces the reference frequency of processor, then reduces the voltage of processor again, and so that new voltage is in one can tie up
Hold the minimum of reference frequency operation.If the average utilization of all clusters has been above the upper limit of second level threshold value and has worked as
Preceding power consumption of processing unit has been more than preset power consumption threshold value, increases the voltage of processor first, then passes through phaselocked loop
Regulative mode increases the reference frequency of processor.If the average utilization of all clusters has been above the upper limit of second level threshold value,
But the power consumption of current processor is not above preset power consumption threshold value, then just the frequency of cluster is maintained at this time
The reference frequency of Primary regulation.
It is controlled using the bipolar threshold of processor utilization, processor performance can be allowed to obtain more rationally under dual limitation
Utilization.For traditional single threshold algorithm, this dual threshold can be more than first order threshold value in processor utilization
Shi Qidong frequency modulation mechanism, can be as soon as possible the Properties Control of processor in rational range.When more than second level threshold value,
Second set of frequency modulation scheme control processor performance again can also be started.Therefore, the regulative mode of this dual threshold has in advance
The characteristics of control, the double compression subsequently coordinated, can achieve the purpose that preferably to utilize processor performance.
The limitation for adding power consumption threshold value effectively limits processor performance surplus.Processor is relied solely on original
Utilization rate on the basis of adjusting frequency, adds real time power consumption detection, when needing to be adjusted up reference frequency, not only needs
It is more than second level threshold value to want processor utilization, it is also necessary to which the power consumption threshold value for being more than processor therefore can be by processor performance
Control is within the scope of a comparison is rational.
Additional hardware supported is not needed, can be realized on original hardware foundation.Processor is only needed to support frequency dividing
Device adjusts frequency, phaselocked loop adjusts frequency and also has voltage adjusting.Most of processor for supporting that DVFS is adjusted all props up at present
Hold these functions.
Algorithm realization is uncomplicated, portable strong.Entire algorithm is inserted into kernel by way of load driver
, so, there is stronger portability, can directly by compiled module loading to any one system kernel,
This province of algorithm is also and uncomplicated, can be suitably adjusted according to the structure of processor.
One embodiment of the present invention has been described in detail above, but the content be only the present invention preferable implementation
Example should not be construed as limiting the practical range of the present invention.It is all according to all the changes and improvements made by the present patent application range
Deng should all still fall within the scope of the patent of the present invention.
Claims (8)
1. a kind of DVFS adaptive based on dual threshold power consumption adjusts algorithm, which is characterized in that including：
The utilization rate and power consumption of processing unit value of processor are obtained in real time；
Whether the utilization rate of decision processor is within first order threshold value；
If so, maintaining working frequency constant；And if it is not, then execute following steps：
Whether the utilization rate of decision processor exceeds second level threshold value；
If it is not, then adjusting frequency by the way of frequency dividing, and if so, execute following steps：
Decision processor utilization rate whether less than second level threshold value lower limit or whether not only exceed second level threshold value the upper limit but also
Beyond power consumption threshold value；
If so, adjusting frequency by the way of phaselocked loop, while changing voltage value；Otherwise, frequency is adjusted by the way of frequency dividing
Rate.
2. the DVFS adaptive based on dual threshold power consumption according to claim 1 adjusts algorithm, which is characterized in that
The utilization rate and working frequency of the processor are proportionate.
3. the DVFS adaptive based on dual threshold power consumption according to claim 1 adjusts algorithm, which is characterized in that
The adjusting section of the processor has been divided into six by the first order threshold value, second level threshold value and power consumption threshold value, when
When the utilization rate of processor is in first order threshold value, then maintain working frequency constant, if processor utilization is between the first order
When between bottom threshold and second level bottom threshold, just frequency is reduced rapidly by the way of frequency dividing；If processor utilization
When between first order upper threshold and second level upper threshold, the mode that frequency dividing is adjusted just is taken to increase frequency rapidly.
4. the DVFS adaptive based on dual threshold power consumption according to claim 1 adjusts algorithm, which is characterized in that
When the upper limit of the processor utilization beyond second level threshold value but power consumption will be less than power consumption threshold value, and frequency dividing is taken to adjust frequency
Mode increase frequency, if being the highest frequency under the voltage at this time, continue to maintain this frequency.
5. the DVFS adaptive based on dual threshold power consumption according to claim 1 adjusts algorithm, which is characterized in that
If processor utilization exceeds second level threshold value, and the power consumption of processor has exceeded power consumption threshold value at this time, then takes
The mode of phaselocked loop increases processor reference frequency, and needs first to increase voltage before adjusting frequency, ensures electricity at this time
Pressure energy is enough normally to support required new frequency.
6. the DVFS adaptive based on dual threshold power consumption according to claim 1 adjusts algorithm, which is characterized in that
If processor utilization is less than the lower limit of second level threshold value, processor benchmark frequency is reduced by the way of phaselocked loop
Rate, and processor voltage is reduced again after reducing frequency.
7. the DVFS adaptive based on dual threshold power consumption according to claim 1 adjusts algorithm, which is characterized in that described the
Level-one threshold value is included in the second level threshold range, and the power consumption threshold value is more than the upper limit of the second level threshold value.
8. the DVFS adaptive based on dual threshold power consumption according to claim 1 adjusts algorithm, which is characterized in that
When the processor is multinuclear, the processor can be divided into multiple clusters, include single or more in each cluster
A core, if multiple cores of the processor need frequency modulation simultaneously, in the cluster that multinuclear is formed, when cluster inner core
Average utilization is more than the section of first order threshold value and is not above the section of second level threshold value, and frequency dividing adjusts the cluster and carries out raising frequency
Or frequency reducing；
When the average utilization of a cluster inner core is less than the section of first order threshold value, maintain the cluster frequency constant；
When the inner core average utilization of all clusters is below the lower limit of second level threshold value, then by the way of phaselocked loop at reduction
Device reference frequency is managed, and processor voltage is reduced again after reducing frequency；
When the inner core average utilization of all clusters is more than the upper limit of second level threshold value, and current power consumption of processing unit is more than
Power threshold then first increases the voltage of processor, then the reference frequency of processor is increased by way of phaselocked loop；
When the inner core average utilization of all clusters is more than the upper limit of second level threshold value, and current power consumption of processing unit is less than
Power threshold then maintains the frequency of cluster in the upper reference frequency once adjusted.
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| US10956220B2 (en) | 2017-06-04 | 2021-03-23 | Apple Inc. | Scheduler for amp architecture using a closed loop performance and thermal controller |
| CN107635277B (en) * | 2017-07-28 | 2020-09-25 | 深圳市盛路物联通讯技术有限公司 | Power saving management method of terminal equipment of Internet of things and terminal equipment of Internet of things |
| CN108958649B (en) * | 2018-05-17 | 2021-03-23 | 天津飞腾信息技术有限公司 | Security isolation method and device for storage system |
| CN108984360B (en) * | 2018-06-06 | 2022-06-21 | 北京嘉楠捷思信息技术有限公司 | Chip frequency modulation method and device of computing equipment, computing force board, computing equipment and storage medium |
| CN112015259B (en) * | 2019-05-29 | 2022-06-21 | 芯原微电子(上海)股份有限公司 | Method and system for controlling peak power consumption |
| CN117296022A (en) * | 2021-05-13 | 2023-12-26 | 华为技术有限公司 | Power consumption adjusting method and device |
| CN113641550B (en) * | 2021-06-16 | 2024-03-22 | 无锡江南计算技术研究所 | Processor power consumption management and control method and device |
| CN113821834B (en) * | 2021-11-24 | 2022-02-15 | 飞腾信息技术有限公司 | Data processing method, security architecture system and computing device |
| CN117472165A (en) * | 2023-12-27 | 2024-01-30 | 中诚华隆计算机技术有限公司 | Method for reducing power consumption of multi-core chip, soC chip and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1359041A (en) * | 2000-12-18 | 2002-07-17 | 联想(北京)有限公司 | Method for adjusting CPU frequency according to CPU availability |
| CN101641866A (en) * | 2007-03-23 | 2010-02-03 | 晶像股份有限公司 | Power-saving clocking technique |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005052820A1 (en) * | 2003-10-31 | 2005-06-09 | International Business Machines Corporation | Method and apparatus for dynamic system-level frequency scaling |
| CN103246340A (en) * | 2012-02-06 | 2013-08-14 | 索尼公司 | Device and method for dynamically adjusting frequency of central processing unit |
-
2015
- 2015-12-31 CN CN201511034909.XA patent/CN105511591B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1359041A (en) * | 2000-12-18 | 2002-07-17 | 联想(北京)有限公司 | Method for adjusting CPU frequency according to CPU availability |
| CN101641866A (en) * | 2007-03-23 | 2010-02-03 | 晶像股份有限公司 | Power-saving clocking technique |
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