CN105511591A - DVFS (Dynamic Voltage and Frequency Scaling) algorithm based on dual-threshold power consumption self-adaptation - Google Patents
DVFS (Dynamic Voltage and Frequency Scaling) algorithm based on dual-threshold power consumption self-adaptation Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
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- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
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Abstract
The invention provides a DVFS (Dynamic Voltage and Frequency Scaling) algorithm based on dual-threshold power consumption self-adaptation. The DVFS algorithm based on dual-threshold power consumption self-adaptation comprises the following steps: acquiring a utilization rate of a processor and a power consumption valve of the processor in real time; judging whether the utilization rate of the processor is within a first-level threshold; if so, maintaining working frequency to be unchanged; if not, executing the following steps: judging whether the utilization rate of the processor exceeds a second-level threshold; if not, regulating the frequency by adopting a frequency division method, and if so, executing the following steps: judging whether the utilization rate of the processor is lower than a lower limit of the second-level threshold or exceeds an upper limit of the second-level threshold and a power consumption threshold; if not, regulating the frequency by adopting the frequency division method; if so, regulating the frequency by adopting a phase-locked loop method, and simultaneously changing a voltage valve. The DVFS algorithm based on dual-threshold power consumption self-adaptation has the beneficial effects that the performance of the processor is reasonably utilized and the power consumption of the processor is reduced.
Description
Technical field
The invention belongs to computerized algorithm technical field, especially relate to a kind of based on dual threshold power consumption adaptive DVFS adjustment algorithm.
Background technology
DVFS technology is a kind of technology optimized for power consumption of processing unit, under it is mainly in different performance levels by processor when processing unequally loaded task from voltage by the frequency of adjustment processor.This technology both needed the support of processor hardware also need software with the use of.
Support DVFS processor in, the voltage-regulation of hardware supported has two kinds of modes: sheet regulate outward with sheet in regulate.Adopt the processor of the outer regulator of sheet when regulation voltage, the stabilization time of needs is long, general need tens delicate to a few tens of milliseconds, but its advantage is also obvious, is exactly that power supply conversion efficiency is relatively high, maximumly can reach 90%.But this relatively high power supply conversion efficiency and load have much relations, when output power is larger, power supply conversion efficiency is higher comparatively speaking.Exactly because the voltage-regulation mode outside sheet is long for stabilization time, so unsuitable overfrequency during regulation voltage on the processor adopting sheet investigation mission outside the city or town machine.The mode regulated in another kind of sheet can by the time shorten of voltage switching to nanosecond, for the voltage switching time shorter in processor provides very favorable condition to realizing quick adjustment.Although the switching time required for sheet internal adjuster greatly reduces relative to the outer regulator of sheet, its Power convert rate is lower comparatively speaking, usually between 70% to 80%.And the silicon area expense that in sheet, regulative mode takies in processor inside is larger, about every watt of 2mm
2.
In the processor supporting DVFS, the frequency adjustment of hardware supported has two kinds of modes: frequency divider regulates and regulates with phaselocked loop.Phaselocked loop and frequency divider regulate these two kinds of modes also to have respective relative merits respectively.For phaselocked loop, from adjust to and finally settle out, need the time locked, and within this time, clock signal exports may cause execution error.Therefore, in the processor adopting phaselocked loop regulating frequency, clock a period of time can be closed during regulating frequency and go to wait for clock stable.And this time is generally more than tens microseconds.Therefore, when adopting phaselocked loop regulating frequency, be not suitable for frequent adjustment, this also causes being not suitable for fine granularity when designing DVFS algorithm and regulates.Relative to phaselocked loop regulating frequency, the mode regulated with frequency divider is then fast a lot.Further, do not have locking time, it is stablized output from receiving signal only need several clock period just can complete to generation.Therefore, frequency adjustment more fast can be realized, but the frequency that this regulative mode obtains is not likely 50% dutycycle.
After processor has had hardware supports DVFS technology, also need the related algorithm of software to coordinate and regulated.In software adjustment, the idle moment of processor mainly detected at present, and reduce in this moment the power consumption that the frequency of processor and voltage reduce processor, and greater loss can not be caused to performance.In software adjustment, DVFS is mainly divided into two large classes: a kind of is the DVFS of closed loop, and another kind is the DVFS of open loop.When using the DVFS of open loop to regulate, generally concrete working condition can be considered.Need to set the voltage of a few thing and the matching status meeting point of frequency in advance.When processor is when running some application program, the information of some necessity of Real-time Collection, and combine relevant regulating and controlling algorithm, finally choose a proper operation state preset according to the result of algorithm.But, in the DVFS of closed loop regulates, a mainly adaptive voltage frequency adjustment, has the Network Performance Monitor of time delay sampling in processor inside, this watch-dog and power supply control voltage module and processor frequencies control module form the system of a closed loop.When working procedure, the information that Network Performance Monitor gathers some necessity comprehensively determines the operating voltage that final processor is suitable and frequency.In processor, open loop and closed loop DVFS regulate maximum difference to be, have and do not have pre-set voltage and the value of frequency.In open cycle system, the pre-set a series of electric voltage frequency value of meeting, when working procedure, by the processor information obtained, reasonably selects pre-set frequency and voltage.But, in closed-loop system, not pre-set frequency and magnitude of voltage, all when processor works, collect information by Network Performance Monitor, predict and judge the most suitable running frequency of current processor and operating voltage, and then regulating according to corresponding algorithm.This is the process of a Hardware/Software Collaborative Design, and design is quite complicated.At present not one very perfect can be general the DVFS method of employing closed loop adjustment.So most of DVFS is still based on open loop.
Summary of the invention
The object of the invention is to overcome prior art deficiency, providing a kind of and regulating algorithm based on the adaptive DVFS of dual threshold power consumption, Appropriate application processor performance, reduction power consumption of processing unit.
Technical scheme of the present invention is: a kind of based on dual threshold power consumption adaptive DVFS adjustment algorithm, comprising:
The utilization factor of Real-time Obtaining processor and power consumption of processing unit value;
Whether the utilization factor of decision processor is within first order threshold value;
If so, then maintenance work frequency is constant; And if not, then perform following steps:
Whether the utilization factor of decision processor exceeds second level threshold value;
If not, then adopt the mode regulating frequency of frequency division, and if so, perform following steps:
Decision processor utilization factor whether lower than second level threshold value lower limit or exceed the upper limit and the power consumption threshold value of second level threshold value;
If not, then the mode regulating frequency of frequency division is adopted; If so, then adopt the mode regulating frequency of phaselocked loop, change magnitude of voltage simultaneously.
Further, the utilization factor of described processor and frequency of operation are proportionate.
Further, described first order threshold value, second level threshold value and power consumption threshold value will divide in order to six between the regulatory region of described processor, when the utilization factor of processor is in first order threshold value, then maintenance work frequency is constant, if when processor utilization is between first order bottom threshold and second level bottom threshold, the mode of frequency division is just adopted to reduce frequency rapidly; If when processor utilization is between first order upper threshold and second level upper threshold, the rapid elevated frequencies of the mode just taking frequency division to regulate.
Further, but the upper limit power consumption exceeding second level threshold value when processor utilization lower than power consumption threshold value, will take the mode elevated frequencies of frequency division regulating frequency, if be now the highest frequency under this voltage, so just continues to maintain this frequency.
Further, if processor utilization exceeds second level threshold value, and now the power consumption of processor is beyond power consumption threshold value, the mode of phaselocked loop is then taked to raise processor reference frequency, and before regulating frequency, need first boosted voltage, ensure that voltage now normally can support required new frequency.
Further, if processor utilization then adopts the mode of phaselocked loop to reduce processor reference frequency lower than the lower of second level threshold value, and processor voltage is reduced again in limited time after reduction frequency.
Further, described first order threshold value is included in the threshold value of the described second level, and described power consumption threshold value is greater than second level upper threshold.
Further, when described processor is multinuclear, described processor can be divided into multiple bunches, single or multiple core is comprised in each bunch, if multiple cores of described processor need frequency modulation simultaneously, multinuclear formed one bunch in, once there be the processor utilization of a core to exceed the higher limit of first order threshold value, second level threshold value or power consumption threshold value, so by the whole bunch of frequency upgrading at this core place to reference frequency.
The advantage that the present invention has and good effect are: owing to adopting technique scheme, adopt the bipolar threshold of processor utilization to control, can processor performance be allowed to get the more reasonable use under dual restriction.Relative to traditional single threshold algorithm, this dual threshold can start when processor utilization exceedes the first order threshold value frequency modulation mechanism, can as soon as possible the Properties Control of processor in rational scope.Once exceed second level threshold value, the second cover frequency modulation scheme control processor performance again can also be started.Therefore, the regulative mode of this dual threshold has and controls in advance, and the feature of the double compression of follow-up coordination, can reach the object utilizing processor performance better.
Accompanying drawing explanation
Fig. 1 is the process flow diagram regulating algorithm based on the adaptive DVFS of dual threshold power consumption of the present invention;
Fig. 2 is structural representation between processor regulatory region of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is elaborated.
Shown in the process flow diagram regulating algorithm based on the adaptive DVFS of dual threshold power consumption as of the present invention in Fig. 1, the invention provides and a kind ofly regulate algorithm based on the adaptive DVFS of dual threshold power consumption, comprising:
Step 101, the utilization factor of Real-time Obtaining processor and power consumption of processing unit value.
Step 102, whether the utilization factor of decision processor is within first order threshold value; If so, then maintenance work frequency is constant; And if not, then perform following steps:
Step 103, whether the utilization factor of decision processor exceeds second level threshold value; If not, then adopt the mode regulating frequency of frequency division, and if so, perform following steps:
Step 104, decision processor utilization factor whether lower than second level threshold value lower limit or exceed the upper limit and the power consumption threshold value of second level threshold value; If not, then the mode regulating frequency of frequency division is adopted.
Step 105, if so, then adopts the mode regulating frequency of phaselocked loop, changes magnitude of voltage simultaneously.
Utilization factor and the frequency of operation of described processor are proportionate.
Frequency of operation can raise along with the rising of utilization rate, and reduces along with the decline of utilization rate.Generally speaking, when performing the application program of the low utilization rates such as word processing, network browsing or other 2D drawing when processor, only need to run can meet user demand with lower frequency of operation.On the contrary, when processor perform 3D drawing, video code conversion, decompression or the contour utilization rate of Games Software application program time, then must significantly improve frequency of operation could meet high load condition under user demand.Therefore, between the frequency of operation of processor and utilization rate, there is corresponding relation, that is, according to the difference of utilization rate scope, processor can operate with corresponding frequency of operation respectively, thus suitable frequency of operation is provided under different utilization rates, overall energy consumption when processor is run reduces.Namely processor is under the using state of different utilization rate, the preferred frequency of operation that can adopt, thus can with energy-conservation mode at combining efficient.Wherein, frequency of operation can be with the matching relationship of utilization rate but be not limited to: the utilization rate etc. of the utilization rate of frequency of operation corresponding less than 10% of 37.5%, the utilization rate of the corresponding 10-40% of frequency of operation of 62.5%, the utilization rate of the corresponding 41-60% of frequency of operation of 75%, the utilization rate of the corresponding 61-80% of frequency of operation of 87.5% and the corresponding 81-100% of frequency of operation of 100%.
Described first order threshold value, second level threshold value and power consumption threshold value will divide in order to six between the regulatory region of described processor, when the utilization factor of processor is in first order threshold value, then maintenance work frequency is constant, if when processor utilization is between first order bottom threshold and second level bottom threshold, the mode of frequency division is just adopted to reduce frequency rapidly; If when processor utilization is between first order upper threshold and second level upper threshold, the rapid elevated frequencies of the mode just taking frequency division to regulate.
But the upper limit power consumption exceeding second level threshold value when processor utilization lower than power consumption threshold value, will take the mode elevated frequencies of frequency division regulating frequency, if be now the highest frequency under this voltage, so just continue to maintain this frequency.
If processor utilization exceeds second level threshold value, and now the power consumption of processor is beyond power consumption threshold value, then take the mode of phaselocked loop to raise processor reference frequency, and before regulating frequency, need first boosted voltage, ensure that voltage now normally can support required new frequency.
If processor utilization then adopts the mode of phaselocked loop to reduce processor reference frequency lower than the lower of second level threshold value, and reduce processor voltage more in limited time after reduction frequency.
Described first order threshold value is included in the threshold value of the described second level, and described power consumption threshold value is greater than second level upper threshold.
When described processor is multinuclear, described processor can be divided into multiple bunches, single or multiple core is comprised in each bunch, if multiple cores of described processor need frequency modulation simultaneously, in one bunch of multinuclear formation, once there be the processor utilization of a core to exceed the higher limit of first order threshold value, second level threshold value or power consumption threshold value, so by the whole bunch of frequency upgrading at this core place to reference frequency.
For 16 core processors.Its 16 cores are on average divided into 4 parts, and each part accounts for 4 cores, and these 4 karyomorphisms become one bunch, when regulating frequency, by bunch in units of can carry out frequency frequency division regulate.The adjustment of voltage and reference frequency is for granularity with whole chip.
When described processor is multinuclear, the present embodiment regulates the implementation step of algorithm as follows based on the adaptive DVFS of dual threshold power consumption:
Step 201, opens the adaptive DVFS of dual threshold power consumption and regulates.
Step 202, obtains the utilization factor of each core and the power consumption number of current processor, and calculates the processor utilization mean value of each bunch of the inside.Search and whether have the utilization factor of some core to exceed preset value.If had, just bunch mode regulated by frequency division at this core place is risen to reference frequency.If do not occur that monokaryon utilization factor exceedes the situation of preset value, so just perform next step.
Described preset value can set by processor performance, can be set as 95% here.
Step 203, judge each bunch, whether occur that the average utilization of some bunch of inner core exceedes the interval of first order threshold value, if exceeded the interval of first order threshold value, but do not exceed the interval of second level threshold value, so, the mode with regard to adopting frequency division to regulate carries out frequency reducing or raising frequency process to this bunch.If the average utilization of bunch inner core does not exceed the interval of first order threshold value, and the frequency so maintaining this bunch is constant, but if exceeded second level threshold value, so just performs next step.
Step 204, if the average utilization of all bunches is all lower than the lower limit of second level threshold value, first reduced the reference frequency of processor by the regulative mode of phaselocked loop, and then reduce the voltage of processor, make new voltage be in a minimum that can maintain this reference frequency and run.If the average utilization of all bunches has all exceeded the upper limit of second level threshold value and current power consumption of processing unit has exceeded the power consumption threshold value preset, first raise the voltage of processor, then raised the reference frequency of processor by the regulative mode of phaselocked loop.If the average utilization of all bunches has all exceeded the upper limit of second level threshold value, but the power consumption of current processor does not exceed the power consumption threshold value preset, so now just by bunch frequency maintain the last reference frequency regulated.
Adopt the bipolar threshold of processor utilization to control, can processor performance be allowed to get the more reasonable use under dual restriction.Relative to traditional single threshold algorithm, this dual threshold can start when processor utilization exceedes the first order threshold value frequency modulation mechanism, can as soon as possible the Properties Control of processor in rational scope.Once exceed second level threshold value, the second cover frequency modulation scheme control processor performance again can also be started.Therefore, the regulative mode of this dual threshold has and controls in advance, and the feature of the double compression of follow-up coordination, can reach the object utilizing processor performance better.
The restriction adding power consumption threshold value effectively limits processor performance surplus.Come on the basis of regulating frequency at original processor utilization that only relies on, add real time power consumption to detect, when needs upwards regulate reference frequency, processor utilization is not only needed to exceed second level threshold value, also need the power consumption threshold value exceeding processor, therefore, processor performance can be controlled within a more rational scope.
Do not need extra hardware supported, can realize on original hardware foundation.Only need that frequency divider regulating frequency supported by processor, phaselocked loop regulating frequency also has voltage-regulation.Current major part supports that these functions all supported by the processor that DVFS regulates.
Algorithm realization is uncomplicated, portable strong.Whole algorithm is inserted in kernel by the mode of load driver to go, so, there is stronger portability, can directly by compiled module loading in any one system kernel, this province of algorithm also and uncomplicated, suitably can adjust according to the structure of processor.
Above one embodiment of the present of invention have been described in detail, but described content being only preferred embodiment of the present invention, can not being considered to for limiting practical range of the present invention.All equalizations done according to the present patent application scope change and improve, and all should still belong within patent covering scope of the present invention.
Claims (8)
1. regulate an algorithm based on the adaptive DVFS of dual threshold power consumption, it is characterized in that, comprising:
The utilization factor of Real-time Obtaining processor and power consumption of processing unit value;
Whether the utilization factor of decision processor is within first order threshold value;
If so, then maintenance work frequency is constant; And if not, then perform following steps:
Whether the utilization factor of decision processor exceeds second level threshold value;
If not, then adopt the mode regulating frequency of frequency division, and if so, perform following steps:
Decision processor utilization factor whether lower than second level threshold value lower limit or exceed the upper limit and the power consumption threshold value of second level threshold value;
If not, then the mode regulating frequency of frequency division is adopted; If so, then adopt the mode regulating frequency of phaselocked loop, change magnitude of voltage simultaneously.
2. according to claim 1 based on dual threshold power consumption adaptive DVFS adjustment algorithm, it is characterized in that, utilization factor and the frequency of operation of described processor are proportionate.
3. according to claim 1 based on dual threshold power consumption adaptive DVFS adjustment algorithm, it is characterized in that, described first order threshold value, second level threshold value and power consumption threshold value will divide in order to six between the regulatory region of described processor, when the utilization factor of processor is in first order threshold value, then maintenance work frequency is constant, if when processor utilization is between first order bottom threshold and second level bottom threshold, the mode of frequency division is just adopted to reduce frequency rapidly; If when processor utilization is between first order upper threshold and second level upper threshold, the rapid elevated frequencies of the mode just taking frequency division to regulate.
4. according to claim 1 based on dual threshold power consumption adaptive DVFS adjustment algorithm, it is characterized in that, but the upper limit power consumption exceeding second level threshold value when processor utilization will lower than power consumption threshold value, take the mode elevated frequencies of frequency division regulating frequency, if be now the highest frequency under this voltage, so just continue to maintain this frequency.
5. according to claim 1 based on dual threshold power consumption adaptive DVFS adjustment algorithm, it is characterized in that, if processor utilization exceeds second level threshold value, and now the power consumption of processor is beyond power consumption threshold value, the mode of phaselocked loop is then taked to raise processor reference frequency, and before regulating frequency, need first boosted voltage, ensure that voltage now normally can support required new frequency.
6. according to claim 1 based on dual threshold power consumption adaptive DVFS adjustment algorithm, it is characterized in that, if processor utilization then adopts the mode of phaselocked loop to reduce processor reference frequency lower than the lower of second level threshold value, and reduce processor voltage more in limited time after reduction frequency.
7. according to claim 1 based on dual threshold power consumption adaptive DVFS adjustment algorithm, it is characterized in that, described first order threshold value is included in the threshold value of the described second level, and described power consumption threshold value is greater than second level upper threshold.
8. according to claim 1 based on dual threshold power consumption adaptive DVFS adjustment algorithm, it is characterized in that, when described processor is multinuclear, described processor can be divided into multiple bunches, single or multiple core is comprised in each bunch, if multiple cores of described processor need frequency modulation simultaneously, in one bunch of multinuclear formation, once there be the processor utilization of a core to exceed the higher limit of first order threshold value, second level threshold value or power consumption threshold value, so by the whole bunch of frequency upgrading at this core place to reference frequency.
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| CN113821834A (en) * | 2021-11-24 | 2021-12-21 | 飞腾信息技术有限公司 | Data processing method, security architecture system and computing device |
| CN117472165A (en) * | 2023-12-27 | 2024-01-30 | 中诚华隆计算机技术有限公司 | Method for reducing power consumption of multi-core chip, soC chip and electronic equipment |
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