CN105487990A - Method and device for transmitting information messages between CPU and chip - Google Patents
Method and device for transmitting information messages between CPU and chip Download PDFInfo
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- CN105487990A CN105487990A CN201410483733.5A CN201410483733A CN105487990A CN 105487990 A CN105487990 A CN 105487990A CN 201410483733 A CN201410483733 A CN 201410483733A CN 105487990 A CN105487990 A CN 105487990A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The invention provides a method and a device for transmitting information messages between a CPU and a chip. The method comprises the steps that the CPU correspondingly distributes a plurality of shared memories for establishing relationship channels with virtual devices according to a plurality of preset configuration spaces, used for configuring PCIE virtual devices, of a chip, and the shared memory is the memory of the CPU used for interacting information with the chip; and the CPU sends the data information messages to the chip in a burst data transmission DMA manner through the corresponding relationship channels established with the chip. The method and device for transmitting the information messages between the CPU and the chip, the data information messages can be sequentially and efficiently transmitted between the CPU and the chip.
Description
Technical field
The present invention relates to communication field, particularly the method for message transfer message and device between a kind of CPU and chip.
Background technology
PCIE (PCI-Express) continues to use PCI programming concept and communication standard, adopts the Physical layer of high speed serialization, realizes point-to-point binary channels high bandwidth transmission.In switch and hardware firewall field, the process of message completes primarily of network processing unit, and CPU mainly completes the function of management and net control processor, and PCIE is the medium of both high-speed communications.
Information spinner mutual between chip and CPU wants the reporting of protocols having message, the reporting of MAC Address message (study, aging, migration etc.), stream table aging information issue, upper strata message issues, also have other functional module interaction messages on send and issue.Message categories is various, priority also has dividing of height, in addition, message content also has how many dividing, some message just may play the effect of a trigger event, few of substantial content, some message just needs containing a lot of content, as IP, the information such as MAC, some message also needs containing whole message, as can be seen from the These characteristics of message, the communication of CPU and chip is not the simple receipt message of energy, designs the key that communication channel is only CPU and chip communication problem in order, efficiently.
Summary of the invention
The technical problem to be solved in the present invention is to provide method and the device of message transfer message between a kind of CPU and chip, between CPU and chip in order, message transfer efficiently.
In order to solve the problems of the technologies described above, the invention provides the method for message transfer message between a kind of CPU and chip, being applied to CPU, comprising:
Multiple configuration spaces for PCI allocation E virtual unit that described CPU presets according to a chip, corresponding distribution is multiple for the shared drive with described virtual unit opening relationships passage, and described shared drive is that described CPU is for the internal memory mutual with described chip information;
The corresponding relation passage of described CPU by setting up with described chip, sends to described chip by data-message message by burst data transmission dma mode.
Wherein, the method for message transfer message between described CPU and chip, also comprises:
Obtain the address information of the memory headroom in described shared drive after the multiple virtual unit of corresponding distribution, and be sent to described chip.
Wherein, described address information comprises: the base address of memory headroom and queue length.
Wherein, multiple configuration spaces for configuration virtual equipment that described CPU presets according to a chip, the multiple step for the shared drive with described virtual unit opening relationships passage of corresponding distribution comprises:
According to the origin identification in described chip being the space that multiple described virtual unit configures, obtain the quantity of described multiple virtual unit, the configuration sequence of corresponding described multiple virtual unit in described chip memory headroom, is followed successively by each described virtual unit and distributes a memory headroom in described shared drive.
Wherein, in described shared drive, each virtual unit all comprises respective multiple messages queue and queue pointer, and described queue pointer indicates described message queue to enter or be moved to described chip.
Wherein, described data-message message comprises: type of message numbering, internal memory zone bit, transmission node number, size of data, memory address and offset in memory address.
Present invention also offers the device of message transfer message between a kind of CPU and chip, be applied to CPU, comprising:
Distribution module, for multiple configuration spaces for PCI allocation E virtual unit that described CPU presets according to a chip, corresponding distribution is multiple for the shared drive with described virtual unit opening relationships passage, and described shared drive is that described CPU is for the internal memory mutual with described chip information;
Transport module, for the corresponding relation passage of described CPU by setting up with described chip, sends to described chip by data-message message by burst data transmission dma mode.
Wherein, the device of message transfer message between described CPU and chip, also comprises:
Sending module, for obtaining corresponding address information of distributing the memory headroom after multiple virtual unit in described shared drive, and is sent to described chip.
Wherein, multiple configuration spaces for configuration virtual equipment that CPU described in described distribution module presets according to a chip, the multiple step for the shared memory space with described virtual unit opening relationships passage of corresponding distribution comprises:
According to the origin identification in described chip being the space that multiple described virtual unit configures, obtain the quantity of described multiple virtual unit, the configuration sequence of corresponding described multiple virtual unit in described chip memory headroom, is followed successively by each described virtual unit and distributes a memory headroom in described shared drive.
Wherein, in described shared drive, each virtual unit all comprises respective multiple messages queue and queue pointer, and described queue pointer indicates described message queue to enter or be moved to described chip.
Wherein, described data-message message comprises: type of message numbering, internal memory zone bit, transmission node number, size of data, memory address and offset in memory address.
In addition, present invention also offers the method for message transfer message between a kind of CPU and chip, be applied to chip, comprising:
In the memory headroom of chip, configure multiple PCIE virtual unit, and the configuration information of described multiple virtual unit is stored in this memory headroom;
Receive the information of the memory headroom in the shared drive of described CPU transmission after multiple virtual unit distribution.
Wherein, described configuration information comprises: the version number of chip microcode, the origin identification of configuration space, the skew of configuration space in described internal memory, the size of configuration space.
Present invention also offers the device of message transfer message between a kind of CPU and chip, be applied to chip, comprising:
Configuration module, for configuring multiple PCIE virtual unit in the memory headroom of chip, and is stored in this memory headroom by the configuration information of described multiple virtual unit;
Receiver module, for receive multiple virtual unit in shared drive that described CPU sends distribute after the information of memory headroom.
The beneficial effect of technique scheme of the present invention is as follows:
In such scheme, multiple PCIE virtual unit is configured in the memory headroom of chip, and the configuration information of multiple virtual unit is stored in this memory headroom, CPU correspondence is distributed multiple for the shared drive with virtual unit opening relationships passage, by the corresponding relation passage that CPU and chip are set up, data-message message can transmit in order, efficiently between CPU and chip.
Accompanying drawing explanation
Fig. 1 represents that the method for message transfer message between CPU and chip in the embodiment of the present invention is applied to the process flow diagram of CPU;
Fig. 2 represents that the application of installation of message transfer message between CPU and chip in the embodiment of the present invention is in the block diagram of CPU;
Fig. 3 represents that the method for message transfer message between CPU and chip in the embodiment of the present invention is applied to the process flow diagram of chip;
Fig. 4 represents that the application of installation of message transfer message between CPU and chip in the embodiment of the present invention is in the block diagram of chip;
Fig. 5 represents the treatment scheme of message kernel in the embodiment of the present invention;
Fig. 6 represents the configuration block diagram of information in virtual unit in the embodiment of the present invention;
Fig. 7 represents the Memory Allocation block diagram of each virtual unit in CPU shared drive in the embodiment of the present invention.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
The present invention is directed to current CPU and chip chamber communication channel can not in order, the problem of high efficiency of transmission, provide method and the device of message transfer message between a kind of CPU and chip.
As shown in Figure 1, embodiments provide the method for message transfer message between a kind of CPU and chip, be applied to CPU, comprising:
Step S11: the described CPU multiple configuration spaces for PCI allocation E virtual unit preset according to a chip, corresponding distribution is multiple for the shared drive with described virtual unit opening relationships passage, and described shared drive is that described CPU is for the internal memory mutual with described chip information;
Step S12: described CPU corresponding relation passage by setting up with described chip, sends to described chip by data-message message by burst data transmission dma mode.
Further, the method for message transfer message between described CPU and chip, also comprises:
Obtain the address information of the memory headroom in described shared drive after the multiple virtual unit of corresponding distribution, and be sent to described chip, particularly, described address information comprises: the base address of memory headroom and queue length.
Particularly, multiple configuration spaces for configuration virtual equipment that described CPU presets according to a chip, the multiple step for the shared drive with described virtual unit opening relationships passage of corresponding distribution comprises:
According to the origin identification in described chip being the space that multiple described virtual unit configures, obtain the quantity of described multiple virtual unit, the configuration sequence of corresponding described multiple virtual unit in described chip memory headroom, is followed successively by each described virtual unit and distributes a memory headroom in described shared drive.
Particularly, in described shared drive, each virtual unit all comprises respective multiple messages queue and queue pointer, and described queue pointer indicates described message queue to enter or be moved to described chip.
Particularly, described data-message message comprises: type of message numbering, internal memory zone bit, transmission node number, size of data, memory address and offset in memory address.
In such scheme, in CPU, reserve some shared drives, for dma operation between CPU and chip; Also distribute one piece of internal memory in chip, as the configuration space of multiple PCIE virtual unit, and by after this spatial mappings to the shared drive of CPU core, just directly can be accessed by CPU.
As shown in Figure 2, present invention also offers the device of message transfer message between a kind of CPU and chip, be applied to CPU, comprising:
Distribution module S21, for multiple configuration spaces for PCI allocation E virtual unit that described CPU presets according to a chip, corresponding distribution is multiple for the shared drive with described virtual unit opening relationships passage, and described shared drive is that described CPU is for the internal memory mutual with described chip information;
Transport module S22, for the corresponding relation passage of described CPU by setting up with described chip, sends to described chip by data-message message by burst data transmission dma mode.
Further, the device of message transfer message between described CPU and chip, also comprises:
Sending module, for obtaining corresponding address information of distributing the memory headroom after multiple virtual unit in described shared drive, and is sent to described chip.
Particularly, described distribution module S21 is used for the origin identification according to the space in described chip being multiple described virtual unit configuration, obtain the quantity of described multiple virtual unit, the configuration sequence of corresponding described multiple virtual unit in described chip memory headroom, is followed successively by each described virtual unit and distributes a memory headroom in described shared drive.
Particularly, in described shared drive, each virtual unit all comprises respective multiple messages queue and queue pointer, and described queue pointer indicates described message queue to enter or be moved to described chip.Described data-message message comprises: type of message numbering, internal memory zone bit, transmission node number, size of data, memory address and offset in memory address.
As shown in Figure 3, the embodiment of the present invention additionally provides the method for message transfer message between a kind of CPU and chip, is applied to chip, comprising:
Step S31: configure multiple PCIE virtual unit in the memory headroom of chip, and the configuration information of described multiple virtual unit is stored in this memory headroom;
Step S32: the information receiving the memory headroom in the shared drive of described CPU transmission after multiple virtual unit distribution.
As shown in Figure 4, present invention also offers the device of message transfer message between a kind of CPU and chip, be applied to chip, comprising:
Configuration module S41, for configuring multiple PCIE virtual unit in the memory headroom of chip, and is stored in this memory headroom by the configuration information of described multiple virtual unit;
Receiver module S42, for receive multiple virtual unit in shared drive that described CPU sends distribute after the information of memory headroom.
In such scheme, in chip internal memory, allocation space creates PCIE virtual unit, each virtual unit has independently communication channel as the transmission terminal of PCIE, do not interfere with each other, can for each independently passage configure the kind of transmission information and priority etc. neatly, greatly facilitate program design.
Further, the embodiment of the present invention is described as follows in conjunction with concrete applicable cases, as shown in Figure 5:
System start time CPU dynamic RAM dram in reserve shared drive, for dma operation between CPU and chip; Meanwhile, in the dynamic RAM dram of chip, also distribute one piece of internal memory, as the configuration space of multiple PCIE virtual unit, and by after this spatial mappings to the shared drive of CPU core, just directly can be accessed by CPU.
Particularly, linux kernel in CPU judges there are how many virtual units according to configuration space origin identification in chip, virtual unit and transmission node ep, then be each virtual unit storage allocation space in order in shared drive, memory headroom base address after distribution and queue length write back to configuration space, such chip microcode just can arrange dma controller according to these information, carries out the information interaction of CPU and chip.
The main configuration information of virtual unit as shown in Figure 6, comprises the general information such as version, compilation tool version that chip microcode uses, and also has the cpu physical address at each virtual unit queue place, the interactive information that the pcie communications such as queue length are used.This memory chip and cpu can access, and are used for transmitting interactive information very convenient.
In CPU, each virtual unit distribution condition in shared drive as shown in Figure 7, lines up to form with buffer pond primarily of multiple circulation.Linux message kernel connects user application and chip in whole message communication, plays a part to form a connecting link, so queue divides two kinds substantially: kernel and the mutual queue of user application and kernel and the mutual queue of chip.Interaction queue has mutual message queue, mutual buffer queue.
The message of CPU and chip chamber transmission has fixing message format, containing a lot of important information, as: type of message numbering, the zone bit whether carrying buffer, No. ep, buffer address and the skew in buffer address and size of data etc.
The message that CPU and chip chamber transmit can be selected the need of buffer according to actual conditions.If transmission of information is many, needs to carry buffer, then by the buffer zone bit set in information, in buffer pond, select suitable buffer, buffer address is inserted in message.
Buffer is selected to go out group buffer than needing according to the order of sequence in the large minimum buffer queue of the information of transmission in Buffer pond.
It should be noted that linux message kernel also can the whole ep queue of poll, if find unread message in queue, then process, as follows respectively:
1. chip is to core message queue
Resolve queue message, if issue the message of user, then this message is put into the message queue of kernel to user; If in message, a certain bit shows buffer contained in this message is the buffer treating that kernel discharges, this Buffer discharges by kernel, is recovered into buffer pond.
2. user is to the message queue of kernel
Resolve queue message, if issue the message of chip, then this message is put into the message queue of kernel to chip.
3. the Buffer queue that discharges to the needs of kernel of user
Discharge the buffer in this buffer queue, be recovered into buffer pond.
The above embodiment of the present invention, in chip internal memory, allocation space creates PCIE virtual unit, in CPU, corresponding distribution is multiple for the shared drive with described virtual unit opening relationships passage simultaneously, and the exchanges data of CPU and chip just can be transmitted by dma mode.In addition, each virtual unit has independently communication channel as the transmission terminal of PCIE, can for each independently passage configure kind and the priority of transmission information neatly, greatly facilitate program design.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (14)
1. the method for message transfer message between CPU and chip, is applied to CPU, it is characterized in that, comprising:
Multiple configuration spaces for PCI allocation E virtual unit that described CPU presets according to a chip, corresponding distribution is multiple for the shared drive with described virtual unit opening relationships passage, and described shared drive is that described CPU is for the internal memory mutual with described chip information;
The corresponding relation passage of described CPU by setting up with described chip, sends to described chip by data-message message by burst data transmission dma mode.
2. the method for message transfer message between CPU according to claim 1 and chip, is characterized in that, also comprise:
Obtain the address information of the memory headroom in described shared drive after the multiple virtual unit of corresponding distribution, and be sent to described chip.
3. the method for message transfer message between CPU according to claim 2 and chip, it is characterized in that, described address information comprises: the base address of memory headroom and queue length.
4. the method for message transfer message between CPU according to claim 1 and chip, it is characterized in that, multiple configuration spaces for configuration virtual equipment that described CPU presets according to a chip, the multiple step for the shared drive with described virtual unit opening relationships passage of corresponding distribution comprises:
According to the origin identification in described chip being the space that multiple described virtual unit configures, obtain the quantity of described multiple virtual unit, the configuration sequence of corresponding described multiple virtual unit in described chip memory headroom, is followed successively by each described virtual unit and distributes a memory headroom in described shared drive.
5. the method for message transfer message between CPU according to claim 1 and chip, it is characterized in that, in described shared drive, each virtual unit all comprises respective multiple messages queue and queue pointer, and described queue pointer indicates described message queue to enter or be moved to described chip.
6. the method for message transfer message between CPU according to claim 1 and chip, it is characterized in that, described data-message message comprises: type of message numbering, internal memory zone bit, transmission node number, size of data, memory address and offset in memory address.
7. the device of message transfer message between CPU and chip, is applied to CPU, it is characterized in that, comprising:
Distribution module, for multiple configuration spaces for PCI allocation E virtual unit that described CPU presets according to a chip, corresponding distribution is multiple for the shared drive with described virtual unit opening relationships passage, and described shared drive is that described CPU is for the internal memory mutual with described chip information;
Transport module, for the corresponding relation passage of described CPU by setting up with described chip, sends to described chip by data-message message by burst data transmission dma mode.
8. the device of message transfer message between CPU according to claim 7 and chip, is characterized in that, also comprise:
Sending module, for obtaining corresponding address information of distributing the memory headroom after multiple virtual unit in described shared drive, and is sent to described chip.
9. the device of message transfer message between CPU according to claim 7 and chip, it is characterized in that, multiple configuration spaces for configuration virtual equipment that CPU described in described distribution module presets according to a chip, the multiple step for the shared memory space with described virtual unit opening relationships passage of corresponding distribution comprises:
According to the origin identification in described chip being the space that multiple described virtual unit configures, obtain the quantity of described multiple virtual unit, the configuration sequence of corresponding described multiple virtual unit in described chip memory headroom, is followed successively by each described virtual unit and distributes a memory headroom in described shared drive.
10. the device of message transfer message between CPU according to claim 7 and chip, it is characterized in that, in described shared drive, each virtual unit all comprises respective multiple messages queue and queue pointer, and described queue pointer indicates described message queue to enter or be moved to described chip.
The device of message transfer message between 11. CPU according to claim 7 and chip, it is characterized in that, described data-message message comprises: type of message numbering, internal memory zone bit, transmission node number, size of data, memory address and offset in memory address.
The method of 12. 1 kinds of messages of message transfer between CPU and chip, is applied to chip, it is characterized in that, comprising:
In the memory headroom of chip, configure multiple PCIE virtual unit, and the configuration information of described multiple virtual unit is stored in this memory headroom;
Receive the information of the memory headroom in the shared drive of described CPU transmission after multiple virtual unit distribution.
The method of message transfer message between 13. CPU according to claim 12 and chip, it is characterized in that, described configuration information comprises: the version number of chip microcode, the origin identification of configuration space, the skew of configuration space in described internal memory, the size of configuration space.
The device of 14. 1 kinds of messages of message transfer between CPU and chip, is applied to chip, it is characterized in that, comprising:
Configuration module, for configuring multiple PCIE virtual unit in the memory headroom of chip, and is stored in this memory headroom by the configuration information of described multiple virtual unit;
Receiver module, for receive multiple virtual unit in shared drive that described CPU sends distribute after the information of memory headroom.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410483733.5A CN105487990A (en) | 2014-09-19 | 2014-09-19 | Method and device for transmitting information messages between CPU and chip |
| PCT/CN2015/079743 WO2016041375A1 (en) | 2014-09-19 | 2015-05-25 | Method and device for transmitting message packet between cpu and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410483733.5A CN105487990A (en) | 2014-09-19 | 2014-09-19 | Method and device for transmitting information messages between CPU and chip |
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| CN105487990A true CN105487990A (en) | 2016-04-13 |
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| CN201410483733.5A Withdrawn CN105487990A (en) | 2014-09-19 | 2014-09-19 | Method and device for transmitting information messages between CPU and chip |
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| CN (1) | CN105487990A (en) |
| WO (1) | WO2016041375A1 (en) |
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| CN108777634A (en) * | 2018-05-24 | 2018-11-09 | 许继电气股份有限公司 | A kind of PCIe switch and its end-point addresses space allocation method |
| CN109753462A (en) * | 2017-11-08 | 2019-05-14 | 山东超越数控电子股份有限公司 | A kind of DMA data transfer method based on FT server PCIE interface card |
| CN111143258A (en) * | 2019-12-29 | 2020-05-12 | 苏州浪潮智能科技有限公司 | Method, system, device and medium for accessing FPGA (field programmable Gate array) by system based on Opencl |
| CN111274176A (en) * | 2020-01-15 | 2020-06-12 | 联想(北京)有限公司 | Information processing method, electronic equipment, system and storage medium |
| CN111737176A (en) * | 2020-05-11 | 2020-10-02 | 福州瑞芯微电子股份有限公司 | PCIE data-based synchronization device and driving method |
| CN112631969A (en) * | 2020-12-30 | 2021-04-09 | 凌云光技术股份有限公司 | Virtual multichannel data transmission method and system based on PCIE interface |
| WO2022063185A1 (en) * | 2020-09-27 | 2022-03-31 | 中兴通讯股份有限公司 | Data acquisition method and system, data reporting method and system, chip, cpu, and storage medium |
| CN114327865A (en) * | 2021-11-30 | 2022-04-12 | 浪潮电子信息产业股份有限公司 | Network card communication method, system, device and computer readable storage medium |
| CN116089130A (en) * | 2023-04-06 | 2023-05-09 | 西安热工研究院有限公司 | Storage structure, working method, equipment and storage medium of data pipeline |
| CN116107843A (en) * | 2023-04-06 | 2023-05-12 | 阿里云计算有限公司 | Method for determining performance of operating system, task scheduling method and equipment |
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| CN114371945A (en) * | 2022-01-10 | 2022-04-19 | 中国民航信息网络股份有限公司 | Message transmission method and device, electronic equipment and computer storage medium |
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| CN112631969A (en) * | 2020-12-30 | 2021-04-09 | 凌云光技术股份有限公司 | Virtual multichannel data transmission method and system based on PCIE interface |
| CN112631969B (en) * | 2020-12-30 | 2024-01-30 | 凌云光技术股份有限公司 | Virtual multichannel data transmission method and system based on PCIE interface |
| CN114327865A (en) * | 2021-11-30 | 2022-04-12 | 浪潮电子信息产业股份有限公司 | Network card communication method, system, device and computer readable storage medium |
| CN116089130A (en) * | 2023-04-06 | 2023-05-09 | 西安热工研究院有限公司 | Storage structure, working method, equipment and storage medium of data pipeline |
| CN116107843A (en) * | 2023-04-06 | 2023-05-12 | 阿里云计算有限公司 | Method for determining performance of operating system, task scheduling method and equipment |
| CN116107843B (en) * | 2023-04-06 | 2023-09-26 | 阿里云计算有限公司 | Method for determining performance of operating system, task scheduling method and equipment |
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