CN105470159A - Method for monitoring fuse burning yield rate in chip test - Google Patents
Method for monitoring fuse burning yield rate in chip test Download PDFInfo
- Publication number
- CN105470159A CN105470159A CN201510790708.6A CN201510790708A CN105470159A CN 105470159 A CN105470159 A CN 105470159A CN 201510790708 A CN201510790708 A CN 201510790708A CN 105470159 A CN105470159 A CN 105470159A
- Authority
- CN
- China
- Prior art keywords
- reference voltage
- fuse
- chip
- measured value
- voltage measured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Fuses (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a method for monitoring the fuse burning yield rate in chip test, comprising the following steps: S1, a fuse truth table is established, wherein the fuse truth table contains the corresponding relation between the reference voltage measured value ranges of chips and fuses needing to be burnt out; S2, a chip is tested, and the reference voltage measured value of the chip is monitored; S3, the reference voltage measured value falls into a specific reference voltage measured value range, the chip is qualified if the reference voltage measured value falls into a reference voltage target range to which the reference voltage standard value belongs, and the chip fuses corresponding to the specific reference voltage measured value range are burnt out according to the corresponding relation between the reference voltage measured value ranges and the fuses needing to be burnt out in the fuse truth table if the reference voltage measured value is beyond the reference voltage target range; and S4, the fuses are burnt again if the fuses are not burnt out. By using the method of the invention, the fuse burning adjustment process in chip test can be monitored in real time.
Description
Technical field
The present invention is scorification silk delivery rate in the test of a kind of monitoring ic, and processes in real time in test process and cause because contact resistance is bigger than normal fuse scorification silk not exclusively to cause the low good situation of test, thus improves a kind of method of scorification silk quality.
Background technology
The development of integrated circuit is had higher requirement to the precision of circuit and programmability.Along with more and more higher to the requirement of integrated circuit high performance index, it is day by day obvious that integrated circuit faces high-precision requirement, and the technology of trimming is the necessary means realizing high-precision integrated circuit.Fuse trims in the digital circuit of traditional analog circuit and high-precision requirement, serve more and more higher status, at AC-DC, DC-DC, be widely used in the integrated circuit (IC) of the types such as LDO (low pressure difference linear voltage regulator), it is so simple that scorification silk does not just trim output voltage, depend on design and determine, its cardinal principle blows short circuit aluminum strip in the resistor network in IC chip to reach the effect changing network resistor, the parameter that fuse can trim also depends on the effect in circuit of this resistance certainly, output voltage, reference voltage the most common trims parameter, in addition as reference frequency, electric currents etc. also can accomplish very high precision by trimming.
Usually should be noted that these two indexs of electric current, voltage in the process of scorification silk, for trim electric current, voltage all can not be too high.Otherwise light then affect test result, even can cause time serious damaging IC.Be below the introduction of fuse:
Traditional burning fusing schemes mainly contains 3 kinds, blows metal fuse with laser, or blows metal fuse and polysilicon fuse with big current.In integrated circuit design, fuse, as the key part in electronic product, is mainly used in resistance and the capacitance characteristic of adjustment IC inside, or among radio circuit.
As shown in Figure 1, common metal fuse is generally be made up of other resistance such as a rule metallic resistance or films.The plain conductor of normally middle narrow two head breadths of fuse, probe is utilized to draw to connect big current (general control is at about 200mA) to trim point (TPAD in Fig. 1) fusing to fuse, irrecoverable after fusing (due to acupuncture treatment problem, may exist and burn the generation of continuous situation).
As shown in Figure 2, general fuse trims, employing be that the fuse opening being parallel to resistance (or electric capacity) two ends is reached the object trimmed by voltage source (current source).The resistance adopting this kind of scheme to trim can only adjust to the direction that resistance is large (electric capacity is to the adjustment of little direction).What the schematic diagram of Fig. 2 adopted is resistant series network; When A point connects a supply power voltage, B point ground connection, when any one in blown fuse F0 ~ Fn or multiple time, the resistance of the R0 ~ Rn of series connection can become large, thus the voltage rise of adjusting resistance Rc right-hand member node.Also can use resistance parallel network or series-parallel network, thus blow the fuse in integrated circuit, the lifting of adjusting reference voltage.
Blow out fuse needs larger immediate current.Concrete required electric current, the wide and thickness according to actual bar and being not quite similar is commonly hundreds of milliampere.Traditional fuse method for repairing and regulating utilizes power supply or electric capacity to make fuse failure by relay to applying the larger immediate current of voltage generation between fuse usually.But in the test event trimmed needing fuse, because the change (such as: contact resistance of probe becomes large) of ambient conditions causes the low IC of the making circuit reference of the fusing rate of fuse not reach job requirement.Fuse due to some product causes electrical quantity to be changed to amphicheirality, if first time fuse burn meeting not in place and cause irreversible loss.This just requires the abnormal conditions will paying close attention to yield in test process the moment.Because the board producing line is numerous, operating personnel can not pay close attention to the situation of a certain test machine in real time, so just may cause in this course the irreversible loss of test products.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of method monitoring scorification silk delivery rate in chip testing is provided, the test chip kind trimmed for needing fuse can well be paid close attention to and trim situation in test process, thus makes corresponding adjustment pointedly; Scorification silk process again can be carried out, and when occurring continuously needing to reburn fuse situation, send alarm in time, remind operating personnel to adjust burning fuse operation.The technical solution used in the present invention is:
Monitor a method for scorification silk delivery rate in chip testing, comprise the steps:
Step S1, sets up a fuse truth table, contains each reference voltage measured value scope of chip and the corresponding relation needing the fuse blown in fuse truth table; Described fuse quantity more than at least two sections, wherein portions of fusing filaments can cause reference voltage to rise after blowing, and reference voltage can be caused after portions of fusing filaments blows to decline, an all corresponding reference voltage variable quantity after each fuse opening; Reference voltage standard value is also provided with in fuse truth table;
The minimum reference value of reference voltage and the highest reference value is provided with in fuse truth table;
Step S2, carries out the test of a chip, the reference voltage measured value of monitoring chip; When the minimum reference value of reference voltage measured value≤reference voltage, or >=the highest the reference value of reference voltage, directly judge that current chip is bad sheet; When the highest reference value of reference voltage minimum reference value < reference voltage measured value < reference voltage, then continue subsequent step;
Step S3, reference voltage measured value falls into a concrete reference voltage measured value scope, if reference voltage measured value drops in a reference voltage target zone at reference voltage standard value place, then chip is qualified, if reference voltage measured value is outside reference voltage target zone, then according to each reference voltage measured value scope in fuse truth table and the corresponding relation needing the fuse blown, each fuse of chip corresponding for this concrete reference voltage measured value scope is blown;
Step S4, measures chip reference voltage measured value again, if the reference voltage measured value obtained drops in a reference voltage target zone at reference voltage standard value place, then chip scorification silk success, performs the test of next chip or the test of other project;
Otherwise, judge that the fuse of correspondent section does not blow according to the theoretical variable quantity of reference voltage actual change amount and reference voltage blowing each section of fuse, then return step S3, carry out scorification silk process again.
More preferably, monitor in described chip testing in the method for scorification silk delivery rate, the fuse counting how many times variable that reburns is set, and a fuse number of times higher limit of reburning; The fuse counting how many times variable initial value that reburns is 0;
Need when carrying out reburning fuse process, the fuse counting how many times variable that reburns cumulative, whether the fuse counting how many times variable that judges to reburn is less than or equal to fuse number of times higher limit of reburning, and if so, just carries out current chip scorification silk process next time, then stops scorification silk if not.
More preferably, the method of scorification silk delivery rate is monitored in described chip testing, each chip carries out in test process successively, add up the accumulated value of the fuse counting how many times variable that reburns, the ratio of the reburn accumulated value of fuse counting how many times variable and the sum of chip is burnt the probability of continuous situation as chip fuse, if this probability is higher than set point, alarm.
The invention has the advantages that: process is trimmed to scorification silk in chip testing and carries out Real-Time Monitoring, can the abnormal conditions of Timeliness coverage chip yield, avoid because fuse first time fuse burns not in place and irreversible loss that is that cause.Alarm can be provided in time when an appearance scorification silk cannot put situation in place continuously.
Accompanying drawing explanation
Fig. 1 is the fuse-wires structure schematic diagram in chip.
Fig. 2 is that chip Internal fuse trims schematic diagram.
Fig. 3 is scorification silk electrical schematic diagram of the present invention.
Fig. 4 is embodiments of the invention flow chart.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
In the present embodiment, monitor the method for scorification silk delivery rate in chip testing, comprise the steps:
Step S1, sets up a fuse truth table, as shown in the table;
In this example, fuse quantity is four sections, after blowing certain section of fuse, the reference voltage variable quantity of chip has been beforehand with relevant regulations in fuse design process, in this example, the reference voltage variable quantity caused after each section of fuse opening is respectively :-12.5mV (T3-GND) ,-25mV (T2-GND) ,-50mV (T1-GND) ,+100mV (T0-GND); T0-GND, T1-GND, T2-GND, T3-GND represent four sections of fuses;
Reference voltage minimum reference value 500mv and the highest reference value 700mv is provided with in fuse truth table; Reference voltage standard value 600mv is also provided with in fuse truth table; In chip testing, if reference voltage measured value Vcs drops in a reference voltage target zone (600mv ~ 612.5mv) at reference voltage standard value place, then chip is qualified, trims without the need to carrying out scorification silk;
Each reference voltage measured value scope of chip and the corresponding relation needing the fuse blown is contained in fuse truth table; In upper table, Digital Logic 1 represents needs this section of fuse opening, and 0 represents that the fuse of corresponding section does not deal with; Such as, in the first row 1 (T0-GND) needs the fuse opening of T0-GND to make the voltage of Vcs be lifted to reference voltage target zone (600mv ~ 612.5mv) when representing that reference voltage measured value Vcs is between 500mV ~ 512mV.
Fig. 3 is IC chip internal scorification silk electrical schematic diagram; TrimPower is scorification filament voltage; K0 ~ K3 is relay switch; Before scorification silk, probe contacts with the point (TPAD) that trims of fuse; Relay switch closes, then scorification filament voltage is applied on corresponding fuse; If probe and fuse to trim point cantact bad; the failure of scorification silk might be caused.
It is as follows that chip testing and scorification silk trim process:
Step S2, carries out the test of a chip, drops on 562.5mV-575mV scope to monitor this chip reference voltage measured value Vcs (hereinafter referred Vcs) recorded; Need the fuse of fusing T0-GND, T1-GND, T3-GND;
Because Vcs is not lower than the minimum reference value 500mv of reference voltage, also not higher than the highest reference value 700mv of reference voltage, therefore this chip can not be judged to be bad sheet at once, when other is possible, if there is the minimum reference value of Vcs≤reference voltage, or Vcs >=the highest reference value of reference voltage, directly judge that current chip is bad sheet; When the highest reference value of the minimum reference value <Vcs< reference voltage of reference voltage, then continue subsequent step;
Step S3, because Vcs is in a concrete reference voltage measured value scope 562.5mV-575mV, but does not drop in reference voltage target zone 600mv ~ 612.5mv, trims because this chip needs to carry out scorification silk; When other is possible, when Vcs is in a reference voltage target zone 600mv ~ 612.5mv at reference voltage standard value place, then chip is qualified; If reference voltage measured value Vcs is outside reference voltage target zone, then according to each reference voltage measured value scope in fuse truth table and the corresponding relation needing the fuse blown, each fuse of chip corresponding for this concrete reference voltage measured value scope is blown;
In this example, the fuse that the needs that reference voltage measured value scope 562.5mV-575mV is corresponding blow is T0-GND, T1-GND, T3-GND; Therefore, closing relay K switch 0, K1 and K3, in order to blow the fuse of T0-GND, T1-GND, T3-GND;
Step S4, after scorification silk, again measure chip reference voltage measured value Vcs, if Vcs is in a reference voltage target zone 600mv ~ 612.5mv at reference voltage standard value place, the success of chip scorification silk, performs the test of next chip or the test of other project;
If Vcs is not in reference voltage target zone 600mv ~ 612.5mv, so need to carry out fuse process of reburning; Now judge that the fuse of correspondent section does not blow according to the theoretical variable quantity of reference voltage actual change amount and reference voltage blowing each section of fuse, then return step S3, carry out scorification silk process again;
For example, if the primary value of Vcs is 570mv, be in 562.5mV-575mV scope, to in requisition for the fuse blowing T0-GND, T1-GND, T3-GND, so the theoretical variable quantity of reference voltage is 100-50-12.5=37.5mv, if these three sections of fuses all normally blow, then the value of Vcs can become 570+37.5=607.5mv, be in reference voltage target zone 600mv ~ 612.5mv, chip is just qualified through once trimming;
And if T1-GND does not blow, so reference voltage actual change amount is exactly 100-12.5v=87.5mv; From the difference 50mv of reference voltage actual change amount 87.5mv and the theoretical variable quantity 37.5mv of reference voltage, from fuse truth table, can judge it is that T1-GND fuse does not blow, thus start fuse process of reburning.
Return step S3, Vcs value is now 570+87.5=657.5mv, falls into a concrete reference voltage measured value scope 650-662.5mv, in requisition for blowing T1-GND fuse.
Be written in a program during said method specific implementation, endless loop is entered in order to prevent program code, in the scorification silk Real-Time Monitoring module of program in the diagram, the fuse counting how many times variable that reburns can be set, and a fuse number of times higher limit (such as 10 times) of reburning; The fuse counting how many times variable initial value that reburns is 0; Need when carrying out reburning fuse process, the fuse counting how many times variable that reburns cumulative, whether the fuse counting how many times variable that judges to reburn is less than or equal to fuse number of times higher limit of reburning, and if so, just carries out current chip scorification silk process next time, then stops scorification silk if not.
Each chip carries out in test process successively, add up the accumulated value of the fuse counting how many times variable that reburns, the ratio of the reburn accumulated value of fuse counting how many times variable and the sum of chip is burnt the probability of continuous situation as chip fuse, if this probability is higher than set point, alarm.Prompting prompting staff confirms probe needle trace and contact resistance and processes accordingly.
If fruit chip is all a scorification silk success, the fuse counting how many times variable that so reburns can keep 0; If 100 chips, wherein had 5 chips to carry out once to reburn fuse process, 2 chips have carried out each fuse process of reburning for 2 times, and so above-mentioned probability is exactly 9%; The probability set point of alarm can fix on 10%, carries out alarm higher than 10%.
Claims (3)
1. monitor a method for scorification silk delivery rate in chip testing, comprise the steps:
Step S1, sets up a fuse truth table, contains each reference voltage measured value scope of chip and the corresponding relation needing the fuse blown in fuse truth table; Described fuse quantity more than at least two sections, wherein portions of fusing filaments can cause reference voltage to rise after blowing, and reference voltage can be caused after portions of fusing filaments blows to decline, an all corresponding reference voltage variable quantity after each fuse opening; Reference voltage standard value is also provided with in fuse truth table;
The minimum reference value of reference voltage and the highest reference value is provided with in fuse truth table;
Step S2, carries out the test of a chip, the reference voltage measured value of monitoring chip; When the minimum reference value of reference voltage measured value≤reference voltage, or >=the highest the reference value of reference voltage, directly judge that current chip is bad sheet; When the highest reference value of reference voltage minimum reference value < reference voltage measured value < reference voltage, then continue subsequent step;
Step S3, reference voltage measured value falls into a concrete reference voltage measured value scope, if reference voltage measured value drops in a reference voltage target zone at reference voltage standard value place, then chip is qualified, if reference voltage measured value is outside reference voltage target zone, then according to each reference voltage measured value scope in fuse truth table and the corresponding relation needing the fuse blown, each fuse of chip corresponding for this concrete reference voltage measured value scope is blown;
Step S4, measures chip reference voltage measured value again, if the reference voltage measured value obtained drops in a reference voltage target zone at reference voltage standard value place, then chip scorification silk success, performs the test of next chip or the test of other project;
Otherwise, judge that the fuse of correspondent section does not blow according to the theoretical variable quantity of reference voltage actual change amount and reference voltage blowing each section of fuse, then return step S3, carry out scorification silk process again.
2. monitor the method for scorification silk delivery rate in chip testing as claimed in claim 1, it is characterized in that:
The fuse counting how many times variable that reburns is set, and a fuse number of times higher limit of reburning; The fuse counting how many times variable initial value that reburns is 0;
Need when carrying out reburning fuse process, the fuse counting how many times variable that reburns cumulative, whether the fuse counting how many times variable that judges to reburn is less than or equal to fuse number of times higher limit of reburning, and if so, just carries out current chip scorification silk process next time, then stops scorification silk if not.
3. monitor the method for scorification silk delivery rate in chip testing as claimed in claim 2, it is characterized in that:
Each chip carries out in test process successively, add up the accumulated value of the fuse counting how many times variable that reburns, the ratio of the reburn accumulated value of fuse counting how many times variable and the sum of chip is burnt the probability of continuous situation as chip fuse, if this probability is higher than set point, alarm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510790708.6A CN105470159B (en) | 2015-11-17 | 2015-11-17 | The method that scorification silk delivery rate is monitored in chip testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510790708.6A CN105470159B (en) | 2015-11-17 | 2015-11-17 | The method that scorification silk delivery rate is monitored in chip testing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105470159A true CN105470159A (en) | 2016-04-06 |
| CN105470159B CN105470159B (en) | 2018-08-10 |
Family
ID=55607732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510790708.6A Active CN105470159B (en) | 2015-11-17 | 2015-11-17 | The method that scorification silk delivery rate is monitored in chip testing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105470159B (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106093755A (en) * | 2016-08-12 | 2016-11-09 | 上海宝司芯微电子有限公司 | Circuit and power management chip are tested in trimming of a kind of power management chip |
| CN106370996A (en) * | 2016-08-30 | 2017-02-01 | 无锡中微腾芯电子有限公司 | Fuse trimming realization method through iteration method |
| CN106405374A (en) * | 2016-08-30 | 2017-02-15 | 无锡中微腾芯电子有限公司 | Fuse burning method for reducing test error |
| CN107276151A (en) * | 2017-06-14 | 2017-10-20 | 南京中感微电子有限公司 | One kind trims circuit and battery protection chip |
| CN107544010A (en) * | 2016-06-28 | 2018-01-05 | 中芯国际集成电路制造(上海)有限公司 | Test equipment and method of testing |
| CN107785306A (en) * | 2016-08-30 | 2018-03-09 | 无锡华润上华科技有限公司 | Fuse trims the manufacture method of chip |
| CN109450433A (en) * | 2018-08-02 | 2019-03-08 | 上海芯哲微电子科技股份有限公司 | A kind of two-way integrated circuit trims device |
| CN111562806A (en) * | 2020-05-18 | 2020-08-21 | 西安拓尔微电子有限责任公司 | Reference source circuit for realizing low temperature coefficient voltage and current on CMOS (complementary metal oxide semiconductor) process |
| CN112630628A (en) * | 2021-03-08 | 2021-04-09 | 上海伟测半导体科技股份有限公司 | Fuse device and method for polysilicon process fuse |
| CN113448599A (en) * | 2021-06-16 | 2021-09-28 | 深圳天狼芯半导体有限公司 | Detection method, detection device, electronic equipment and readable storage medium |
| CN114002588A (en) * | 2022-01-04 | 2022-02-01 | 苏州贝克微电子股份有限公司 | High-precision semiconductor chip trimming test method |
| CN114428204A (en) * | 2020-10-29 | 2022-05-03 | 长鑫存储技术有限公司 | Method and device for adjusting chip output characteristics |
| US12002751B2 (en) | 2020-10-29 | 2024-06-04 | Changxin Memory Technologies, Inc. | Adjustment method and device for chip output characteristics |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133333A (en) * | 1987-11-18 | 1989-05-25 | Mitsubishi Electric Corp | Semiconductor device with redundant circuit |
| KR20060066500A (en) * | 2004-12-13 | 2006-06-16 | 삼성전자주식회사 | Semiconductor devices |
| CN1967806A (en) * | 2005-11-16 | 2007-05-23 | 台湾积体电路制造股份有限公司 | Integrated circuit manufacturing method and method for reducing erosion of fuse structure |
| US20090045400A1 (en) * | 2007-08-13 | 2009-02-19 | Broadcom Corporation | Method for monitoring fuse integrity in a semiconductor die and related structure |
| CN101908524A (en) * | 2010-06-30 | 2010-12-08 | 上海华岭集成电路技术有限责任公司 | Antioxidation method for finishing fuse |
-
2015
- 2015-11-17 CN CN201510790708.6A patent/CN105470159B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133333A (en) * | 1987-11-18 | 1989-05-25 | Mitsubishi Electric Corp | Semiconductor device with redundant circuit |
| KR20060066500A (en) * | 2004-12-13 | 2006-06-16 | 삼성전자주식회사 | Semiconductor devices |
| CN1967806A (en) * | 2005-11-16 | 2007-05-23 | 台湾积体电路制造股份有限公司 | Integrated circuit manufacturing method and method for reducing erosion of fuse structure |
| US20090045400A1 (en) * | 2007-08-13 | 2009-02-19 | Broadcom Corporation | Method for monitoring fuse integrity in a semiconductor die and related structure |
| CN101908524A (en) * | 2010-06-30 | 2010-12-08 | 上海华岭集成电路技术有限责任公司 | Antioxidation method for finishing fuse |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107544010B (en) * | 2016-06-28 | 2020-05-01 | 中芯国际集成电路制造(上海)有限公司 | Test equipment and test method |
| CN107544010A (en) * | 2016-06-28 | 2018-01-05 | 中芯国际集成电路制造(上海)有限公司 | Test equipment and method of testing |
| CN106093755A (en) * | 2016-08-12 | 2016-11-09 | 上海宝司芯微电子有限公司 | Circuit and power management chip are tested in trimming of a kind of power management chip |
| CN106370996A (en) * | 2016-08-30 | 2017-02-01 | 无锡中微腾芯电子有限公司 | Fuse trimming realization method through iteration method |
| CN106405374A (en) * | 2016-08-30 | 2017-02-15 | 无锡中微腾芯电子有限公司 | Fuse burning method for reducing test error |
| CN107785306A (en) * | 2016-08-30 | 2018-03-09 | 无锡华润上华科技有限公司 | Fuse trims the manufacture method of chip |
| CN107276151A (en) * | 2017-06-14 | 2017-10-20 | 南京中感微电子有限公司 | One kind trims circuit and battery protection chip |
| CN107276151B (en) * | 2017-06-14 | 2019-09-13 | 南京中感微电子有限公司 | One kind trimming circuit and battery protection chip |
| CN109450433B (en) * | 2018-08-02 | 2022-08-05 | 上海芯哲微电子科技股份有限公司 | Double-circuit integrated circuit trimming device |
| CN109450433A (en) * | 2018-08-02 | 2019-03-08 | 上海芯哲微电子科技股份有限公司 | A kind of two-way integrated circuit trims device |
| CN111562806A (en) * | 2020-05-18 | 2020-08-21 | 西安拓尔微电子有限责任公司 | Reference source circuit for realizing low temperature coefficient voltage and current on CMOS (complementary metal oxide semiconductor) process |
| CN111562806B (en) * | 2020-05-18 | 2024-06-04 | 拓尔微电子股份有限公司 | Reference source circuit for realizing low temperature coefficient voltage and current in CMOS process |
| CN114428204A (en) * | 2020-10-29 | 2022-05-03 | 长鑫存储技术有限公司 | Method and device for adjusting chip output characteristics |
| CN114428204B (en) * | 2020-10-29 | 2023-09-01 | 长鑫存储技术有限公司 | Chip output characteristic adjusting method and device |
| US12002751B2 (en) | 2020-10-29 | 2024-06-04 | Changxin Memory Technologies, Inc. | Adjustment method and device for chip output characteristics |
| CN112630628A (en) * | 2021-03-08 | 2021-04-09 | 上海伟测半导体科技股份有限公司 | Fuse device and method for polysilicon process fuse |
| CN113448599A (en) * | 2021-06-16 | 2021-09-28 | 深圳天狼芯半导体有限公司 | Detection method, detection device, electronic equipment and readable storage medium |
| CN113448599B (en) * | 2021-06-16 | 2024-12-06 | 深圳天狼芯半导体有限公司 | A detection method, device, electronic device and readable storage medium |
| CN114002588A (en) * | 2022-01-04 | 2022-02-01 | 苏州贝克微电子股份有限公司 | High-precision semiconductor chip trimming test method |
| CN114002588B (en) * | 2022-01-04 | 2022-04-29 | 苏州贝克微电子股份有限公司 | High-precision semiconductor chip trimming test method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105470159B (en) | 2018-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105470159A (en) | Method for monitoring fuse burning yield rate in chip test | |
| DE112007001293B4 (en) | Power supply controller | |
| CN201392350Y (en) | Probe card for anti-interference asynchronous trimming wafer test | |
| CN114137916B (en) | Supervision and control system for circuit board production based on data analysis | |
| CN106370996B (en) | A method of realizing that fuse trims using iterative method | |
| CN106708155B (en) | Integrated circuit and circuit characteristic adjusting method thereof | |
| DE102009017989A1 (en) | Monitoring device for LED arrangement of lighting system, has detection unit monitoring time response of detected electric variable to detect LED error, where error signal is produced when LED error is present | |
| US20230411087A1 (en) | Power contact electrode surface plasma therapy | |
| CN108320235B (en) | Monitoring management system | |
| CN103364690A (en) | Testing system and method for safety | |
| CN106405374A (en) | Fuse burning method for reducing test error | |
| CN105182249A (en) | Fault diagnosis method of high-power switching power supply | |
| CN107450786A (en) | Touch control controller including its contact panel and the method for detecting fault | |
| CN207851191U (en) | A kind of detection circuit for signal ground failure | |
| CN110625220A (en) | Intelligent testing and debugging device and method for electric welding machine | |
| CN112670950B (en) | Self-repairing method of PT intelligent blocking device | |
| CN109872853A (en) | A kind of CrSi2Film resistor and its laser trimming method | |
| US2602586A (en) | Quality control indicator | |
| KR200427418Y1 (en) | Pin state checking device of junction box | |
| CN115373462B (en) | Chip trimming detection circuit, chip and electronic equipment | |
| CN117741410B (en) | High-power hybrid integrated circuit aging system | |
| JPH10135286A (en) | Method and system for sorting high temperature detect product | |
| CN219201822U (en) | Constant current diode array reliability test circuit | |
| CN218443398U (en) | Temperature control device and heating furnace | |
| CN114707102B (en) | Test method and system for relay protection device with inverse time limit characteristic |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |