CN105468164A - Matrix keyboard scanning and encoding circuit - Google Patents
Matrix keyboard scanning and encoding circuit Download PDFInfo
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- CN105468164A CN105468164A CN201610003604.0A CN201610003604A CN105468164A CN 105468164 A CN105468164 A CN 105468164A CN 201610003604 A CN201610003604 A CN 201610003604A CN 105468164 A CN105468164 A CN 105468164A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
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Abstract
A matrix keyboard scanning and encoding circuit is composed of a matrix keyboard, a first buffer register, a second buffer register, a condition code register, an encoder and a data combination unit. The matrix keyboard scanning and encoding circuit is controlled by clock pulses, scanning pulses and sampling pulses to convert location of single-key operations, combination-key operations and keyboard maintenance condition operations into valid state codes and invalid state codes of the same binary system length. The codes are encoded through an encoder, and valid key numbers in one-to-one correspondence to the valid state codes and invalid key numbers in one-to-one correspondence to the invalid state codes are output. Different single-key operations, combination-key operations and keyboard maintenance condition operations are only represented to different state codes. If key operation functions are increased or decreased, or key operation functions are adjusted, only the encoder is changed according to the correspondence between the increased or decreased state codes and the key numbers instead of modifying the structure of the keyboard scanning circuit. According to the circuit, programs are not needed to be written and operated, and work is reliable.
Description
Technical field
The present invention relates to a kind of sweep circuit of keyboard, especially a kind of matrix keyboard scanner uni coding circuit.
Background technology
Along with the development of embedded technology, current each electronic product generally adopts microcontroller as control core, and keyboard, as main input equipment, is widely used.
Current keyboard scan controlled primarily of microcontroller, needs to be undertaken by the program run in microcontroller, and run into interference, cause program to run fast, scanning sequence is by cisco unity malfunction.
Application number is the Scan orientation process that mode that the patent of invention " a kind of fast scanning and positioning method of matrix keyboard " of CN201010153560.2 adopts keyboard interrupt to trigger enters keyboard, whether button is effective to adopt the method repeatedly repeating keyboard scan step to judge, and carries out condition adjudgement to obtained key assignments; If multiple repairing weld state is identical, be then in steady state (SS), key assignments is effective; If multiple repairing weld state is different, key assignments is invalid.Single key stroke or Macintosh action need judge that separately single key stroke in this way then enters singly-bound tupe; Macintosh operation in this way, then enter Macintosh tupe.Method described in this patent solves keyboard shake that the mechanical property due to keyboard self causes and causes the Problem-Errors such as wrong key, continuously touching, and the support issue to Macintosh and repeat key.But described method single key stroke and Macintosh action need process respectively; Do not consider that keyboard state maintains a period of time to the rear keyboard operation function just performing valid function; When increase and decrease button operation function or adjustment button operation function, need amendment keyboard scan finder structure.
Summary of the invention
In order to solve the above-mentioned technical matters that existing keyboard scan localization method exists, the invention provides a kind of matrix keyboard scanner uni coding circuit, be made up of matrix keyboard, the first buffer register, the second buffer register, status code register, scrambler, data combination unit.
Described matrix keyboard scanner uni coding circuit carries out synchro control by scanning impulse, time clock and sampling pulse.
Described matrix keyboard has that X is capable, Y row, is provided with N bit keyboard status signal output; Described N bit keyboard status signal is level signal; Described N=X+Y.
Described first buffer register and the second buffer register equal N position binary register; The N bit data input end of described first buffer register is connected to N bit keyboard status signal output successively; The N bit data input end of described second buffer register is connected to N bit keyboard status signal output successively.
The received pulse input end of described first buffer register and the second buffer register is connected to scanning impulse.
Described data combination unit is provided with first via N bit data input end, the second road N bit data input end and 2 × N bit data output terminal; Described first via N bit data input end is connected to the N bit data output terminal of the first buffer register successively, and the second road N bit data input end is connected to the N bit data output terminal of the second buffer register successively.
Described data combination unit is also provided with data select signal end; Described data select signal end is connected to scanning impulse; In 2 × N bit data output of data combination unit, when described scanning impulse is low level, first via N bit data is front, and the second road N bit data is rear; When described scanning impulse is high level, first via N bit data is rear, and the second road N bit data is front; Or in 2 × N bit data output of data combination unit, when described scanning impulse is low level, first via N bit data is rear, and the second road N bit data is front; When described scanning impulse is high level, first via N bit data is front, and the second road N bit data is rear.
Described status code register is 2 × N position binary register; 2 × N bit data input end of status code register is connected to 2 × N bit data output terminal of data combination unit.
The received pulse input end of described status code register is connected to time clock; Described matrix keyboard is controlled to obtain N bit keyboard status signal by sampling pulse;
Described scrambler has 2 × N position coding input end, and described 2 × N position coding input end is connected to 2 × N bit data output terminal of status code register.
The cycle of described time clock is 20 ~ 100ms; Described scanning impulse is the two divided-frequency signal of time clock; The cycle of described sampling pulse is not more than the cycle of described time clock.
The invalid triggering edge of described time clock gated sweep pulse upset is called state latch edge; Described status code register carries out latches data on the state latch edge of time clock; Described first buffer register is when the rising edge of scanning impulse carries out latches data, and the second buffer register carries out latches data at the negative edge of scanning impulse; Or described first buffer register is when the negative edge of scanning impulse carries out latches data, and the second buffer register carries out latches data at the rising edge of scanning impulse.
2 × N bit data output terminal of described status code register exports the status code of 2 × N position; Described status code is made up of effective status code and disarmed state code; The key number that described scrambler exports is made up of with invalid key number effective key number; Described effective status code is produced by effective keyboard operation or state, correspondingly when scrambler inputs each effective status code exports corresponding effectively key number; Described disarmed state code is produced by invalid keyboard operation or state, all correspondingly when scrambler inputs all disarmed state codes exports invalid key number.
Described scrambler has M position key output terminal, and the selection of M value should meet 2
mbe more than or equal to the quantity sum of effective key number and invalid key number.
Described matrix keyboard scanner uni coding circuit also comprises keyboard state change pulse generation unit, and whether the key number exported for judgment matrix formula keyboard changes, and when the key number that matrix keyboard exports changes, exports keyboard state change pulse.
Described keyboard state change pulse generation unit by M position delay buffer, a M XOR gate and or door form; The M position key number that M position delay buffer is used for matrix keyboard exports carries out signal delay respectively; The input of M XOR gate is respectively input, the output signal of M position delay buffer; The output of M XOR gate is connected to or the input end of door respectively; Or the output terminal of door exports keyboard state change pulse.
Described matrix keyboard scanner uni coding circuit also comprises oscillator; The pulse of described oscillator output clock, scanning impulse and sampling pulse.
Described matrix keyboard is made up of X capable-Y row key-press matrix, row three-state buffer, row three-state buffer, row status register, column-shaped state register; The line of all key-press matrixs is connected to the output terminal of row three-state buffer respectively, and the alignment of all key-press matrixs is connected to the output terminal of row three-state buffer respectively; All input ends of row three-state buffer and row three-state buffer are connected to low level; The line of all key-press matrixs is connected to the input end of row status register respectively, and the alignment of all key-press matrixs is connected to the input end of row status register respectively; The output terminal of described row status register and the output terminal of row status register form keyboard state signal output part jointly.
Described row three-state buffer the low level of sampling pulse enable effective time, latches data, row three-state buffer are enable effectively at the high level of sampling pulse, row status register carries out latches data at the negative edge of sampling pulse to require row status register to carry out at the rising edge of sampling pulse; Or, row three-state buffer the high level of sampling pulse enable effective time, latches data, row three-state buffer are enable effectively in the low level of sampling pulse, row status register carries out latches data at the rising edge of sampling pulse to require row status register to carry out at the negative edge of sampling pulse.
Described N position, 2 × N position, M position all refer to binary digit data.
The invention has the beneficial effects as follows: by the location of the single key stroke to matrix keyboard, Macintosh operation, keyboard maintenance state of operation, the status code converting same binary length to is controlled by time clock, scanning impulse, adopt the mode of Unified coding to process, the operation of single key stroke, Macintosh, keyboard maintain state of operation and are only embodied in the not the same of status code; If need increase and decrease button operation function or adjustment button operation function, do not need amendment keyboard scanning circuit structure, only need change scrambler according to the corresponding relation between the status code after increase and decrease and key number, namely re-write the storage content of ROM (read-only memory).Described invention circuit does not use the microcontroller such as single-chip microcomputer, ARM, without working procedure, and reliable operation.
Accompanying drawing explanation
Fig. 1 is matrix keyboard scanner uni coding circuit theory diagram;
Fig. 2 is the matrix keyboard circuit diagram of the embodiment of the present invention;
Fig. 3 is the Scan orientation circuit diagram of the embodiment of the present invention;
Fig. 4 is the data combination unit circuit diagram of the embodiment of the present invention;
Fig. 5 is time clock and the scanning impulse oscillogram of the embodiment of the present invention;
Fig. 6 is the circuit diagram of the keyboard state change pulse generation unit of the embodiment of the present invention;
Fig. 7 is the waveform correlation schematic diagram of the keyboard valid function of the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Fig. 1 is matrix keyboard scanner uni coding circuit theory diagram, is made up of matrix keyboard 400, first buffer register 101, second buffer register 102, status code register 200, scrambler 300, data combination unit 500.
Fig. 2 is the circuit diagram of the matrix keyboard 400 of the embodiment of the present invention, have 2 row, 2 row, totally 4 buttons, by button S1, button S2, button S3, button S4 and the pull-up resistor R1, pull-up resistor R2, pull-up resistor R3, the pull-up resistor R4 that are connected to power supply+VCC, and row three-state buffer 401, row three-state buffer 402, row status register 403, row status register 404 form.2 output terminals Y1, Y2 of row three-state buffer 401 are connected to 2 lines respectively, and 2 output terminals Y3, Y4 of row three-state buffer 402 are connected to 2 alignments respectively; All input end X1 ~ X4 of row three-state buffer 401 and row three-state buffer 402 are connected to low level.
2 input ends D41, D42 of row status register 403 are connected to 2 lines respectively, and 2 input ends D43, D44 of row status register 404 are connected to 2 alignments respectively; 2 output terminals Q41, Q42 of row status register 403 export row status signal I1, I2, and 2 output terminals Q43, Q44 of row status register 404 export row status signal I3, I4; 2 output terminals of row status register 403 and 2 output terminals of row status register 404 form 4 bit keyboard status signal output jointly, export keyboard state signal I1, I2, I3, I4.
In embodiment, the enable input EN1 Low level effective of row three-state buffer 401, the enable input EN2 high level of row three-state buffer 402 is effective; EN1 and EN2 is all connected to the CK sampling pulse output terminal of oscillator 500.Row status register 403 is all connected to the CK sampling pulse output terminal of oscillator 500 with received pulse input end CLK3, CLK4 of row status register 404, row status register 403 carries out latches data at the negative edge of CK sampling pulse, and row status register 404 carries out latches data at the rising edge of CK sampling pulse.
When row three-state buffer 401 and row three-state buffer 402 use the three-state buffer of same model, such as, when using three-state buffer 74HC241 simultaneously, it is effective that 74HC241 enable is input as high level, therefore, between CK sampling pulse output terminal and the enable input end EN1 of row three-state buffer 401, need increase not gate.Similarly, when row status register 403 and row status register 404 use the data register of same model, such as, when row status register 403 and row status register 404 all use double D trigger 74HC74 to form data register, it is effective that the triggering of 74HC74 is input as rising edge, therefore, between CK sampling pulse output terminal and the received pulse input end CLK3 of row status register 403, need increase not gate.
The first buffer register 101, second buffer register 102 in Fig. 1, status code register 200, scrambler 300, data combination unit 500 form Scan orientation circuit, and embodiment circuit diagram as shown in Figure 3.The status signal that embodiment matrix keyboard circuit exports has 4, therefore, first buffer register 101, second buffer register 102 all requires to deposit 4 bit binary data, 4 data input pin D10 ~ D13 of the first buffer register 101 are connected to I1, I2, I3, I4 successively, and 4 data input pin D14 ~ D17 of the second buffer register 102 are also connected to I1, I2, I3, I4 successively.
Data combination unit 500 is for realizing selected and sorted and the combination of two-way input data.In embodiment, 1 tunnel in two-way input data is 4 bit data J, and J comprises J3, J2, J1, J0; Other 1 tunnel is 4 bit data K, and K comprises K3, K2, K1, K0; The output data on 18, tunnel are L.The function of data combination unit 500 is, 8 export data L and have two kinds of combinations of sorting, a kind of sequence combination be 4 bit data J front, 4 bit data K, rear, namely export L7 ~ L0 and are followed successively by J3, J2, J1, J0, K3, K2, K1, K0; Another sequence combination be 4 bit data K front, 4 bit data J, rear, namely export L7 ~ L0 and are followed successively by K3, K2, K1, K0, J3, J2, J1, J0; Two kinds of sequence combinations are subject to the control of data select signal S.
Data combination unit 500 can adopt data selector, three-state buffer, or other modes realize.Fig. 4 is data combination unit 500 embodiment schematic diagram, and select 1 data selector 501,502 to form by 242, the data select signal S of 501,502 is all connected to CP2 scanning impulse.When CP2 is low level, 42 select 1 data selector 501,502 selector channel 0, and namely L7 ~ L0 equals K3, K2, K1, K0, J3, J2, J1, J0; When CP2 is high level, 42 select 1 data selector 501,502 selector channel 1, and namely L7 ~ L0 equals J3, J2, J1, J0, K3, K2, K1, K0.
Status code register 200 requires to deposit 8 bit binary data, and its 8 bit data input end D27 ~ D20 is connected to 8 bit data output terminal L7 ~ L0 of data combination unit 500; 8 input end A7 ~ A0 of scrambler 300 are connected to 8 data output end Q27 ~ Q20 of status code register 200.Scrambler 300 exports 4 the scale-of-two keys number determined through Scan orientation.
In Fig. 3 embodiment, first buffer register 101, second buffer register 102, status code register 200 form by edge triggered flip flop, preferably be made up of the d type flip flop of edging trigger, such as, be made up of double D trigger 74HC74,4D trigger 74HC175,8D trigger 74HC273.The trigger input of 4 edge triggered flip flops in the first buffer register 101 links together and forms received pulse input end, and be connected to CP2 scanning impulse, negative edge carries out latches data; The trigger input of 4 edge triggered flip flops in the second buffer register 102 links together and forms received pulse input end, and be connected to CP2 scanning impulse, rising edge carries out latches data; The trigger input of 8 edge triggered flip flops of status code register 200 links together and forms received pulse input end, and be connected to CP1 time clock, rising edge carries out latches data.
In Fig. 3 embodiment, the 8D trigger 74HC273 that first buffer register 101, second buffer register 102, status code register 200 trigger by rising edge, because the first buffer register 101 requires that negative edge carries out latches data, therefore, CP2 scanning impulse needs after a not gate is anti-phase, then is connected to the received pulse input end of the first buffer register 101; In addition, the Protection Counter Functions of described 74HC273 be made to be in disarmed state, ensure the first buffer register 101, second buffer register 102, status code register 200 only has Trigger Function.
In Fig. 3 embodiment, scrambler 300 is ROM (read-only memory).Address input end A7 ~ the A0 of ROM (read-only memory) is the input end of scrambler 300, and the data output end D3 ~ D0 of ROM (read-only memory) is the coding output terminal C3 ~ C0 of scrambler 300.
Embodiment does not draw the oscillator producing CP1 time clock, CP2 scanning impulse, CK sampling pulse, oscillator is multivibrator, export CP1 time clock, CP2 scanning impulse and CK sampling pulse, the cycle of CP1 time clock is 20 ~ 100ms, CP2 scanning impulse is the two divided-frequency signal of CP1 time clock, and the waveform of CP1, CP2 as shown in Figure 5.CP1 time clock, CP2 scanning impulse and CK sampling pulse also can be provided by the circuit outside matrix keyboard scanner uni coding circuit or device.
The principle of work of matrix keyboard scanner uni coding circuit is as follows:
In Fig. 2,4 buttons of matrix keyboard with 2 × 2 matrix form arrangement, all lines and alignment are all connected to power supply+VCC by pull-up resistor.Matrix keyboard is controlled by CK sampling pulse, adopts reversal process to obtain keyboard state signal I4, I3, I2, I1.Such as, the keyboard state signal not having key to press is the keyboard state signal that the keyboard state signal that 1111, S1 presses is 1010, S1, S2 presses simultaneously is 0010.4 binary codes of keyboard state signal are called key assignments.
The method that CK sampling pulse controls to carry out matrix keyboard sampling reading key assignments is: in the low level of CK sampling pulse, control all line output low levels by row three-state buffer 401, and row three-state buffer 402 exports the open alignment of high-impedance state; To be sampled by row status register 404 at the rising edge of CK sampling pulse and read high 2 as key assignments of alignment state; At the high level of CK sampling pulse, control all alignment output low levels by row three-state buffer 402, row three-state buffer 401 exports the open line of high-impedance state; To be sampled low 2 as key assignments of read line line states by row status register 403 at the negative edge of CK sampling pulse; Said process goes round and begins again, and 4 key assignments that row status register 404, row status register 403 export are always the last state of matrix keyboard.
Control to carry out sampling to matrix keyboard to read the method for key assignments from CK sampling pulse, row three-state buffer 401 the low level of CK sampling pulse enable effective time, require row status register 404 to carry out at the rising edge of CK sampling pulse latches data, row three-state buffer 402 are enable effectively at the high level of CK sampling pulse, row status register 403 carries out latches data at the negative edge of CK sampling pulse simultaneously.Conversely, if row three-state buffer 401 the high level of CK sampling pulse enable effective time, require row status register 404 to carry out at the negative edge of CK sampling pulse latches data, row three-state buffer 402 are enable effectively in the low level of CK sampling pulse, row status register 403 carries out latches data at the rising edge of CK sampling pulse simultaneously.
Controlling sampling at above-mentioned CK sampling pulse reads in the process of key assignments, the moment that row status register 403, row status register 404 carry out sampling is that row three-state buffer 402 carries out the moment of state reversion with row three-state buffer 401 just, and the row status register 403 under normal work or row status register 404 can correctly be sampled.If require the allowance in certain sequential, then can the CK sampling pulse being connected to row three-state buffer 402 and row three-state buffer 401 be postponed, method makes CK sampling pulse be connected to EN1, EN2 of row three-state buffer 401 and row three-state buffer 402 again through RC delay circuit, time delay is determined by RC delay circuit, determine that the principle of the time delay of RC delay circuit is, the CK sample pulse phase of delay is no more than 90 °; Or CK sampling pulse is connected to EN1, EN2 of row three-state buffer 401 and row three-state buffer 402 again after the buffering of several gate circuit, time delay is now overall delay time of described several gate circuit.
First buffer register 101, second buffer register 102, under CP2 scanning impulse controls, alternately carries out latches data to status signal I1, I2, I3, I4 that matrix keyboard exports; The output of the buffer register of up-to-date latch data is called existing state key assignments, the output of the buffer register of latch data is called front state key assignments slightly before, therefore, the first buffer register 101, second buffer register 102, under CP2 scanning impulse controls, alternately exports existing state key assignments and front state key assignments.
Fig. 3 and Fig. 5 in conjunction with the embodiments, after CP2 scanning impulse negative edge, at the low level state of CP2 scanning impulse, the existing state key assignments that first buffer register 101 exports is connected to the input end J3 of data combination unit 500, J2, J1, J0, the front state key assignments that second buffer register 102 exports is connected to the input end K3 of data combination unit 500, K2, K1, K0, and now data select signal S is connected to CP2 scanning impulse, for low level, output L7 ~ the L0 of data combination unit 500 equals K3, K2, K1, K0, J3, J2, J1, J0, namely before, state key assignments is front, existing state key assignments is rear, after CP2 scanning impulse rising edge, at the high level state of CP2 scanning impulse, the front state key assignments that first buffer register 101 exports is connected to input end J3, J2, J1, J0 of data combination unit 500, the existing state key assignments that second buffer register 102 exports is connected to input end K3, K2, K1, K0 of data combination unit 500, and now data select signal S is connected to CP2 scanning impulse, for high level, output L7 ~ the L0 of data combination unit 500 equals J3, J2, J1, J0, K3, K2, K1, K0, be equally front state key assignments front, existing state key assignments is rear.
CP2 scanning impulse is state key assignments, existing state key assignments before control first buffer register 101, second buffer register 102 alternately latch output, and data combination unit 500 carries out data selection sequence and the moment of combining, the of short duration nondeterministic statement that can be formed.The effect of status code register 200 is the impacts eliminating this nondeterministic statement.
Status code register 200 be input as the front state key assignments and existing state key assignments that data combination unit 500 exports, export and be similarly front state key assignments and existing state key assignments.Edge status code register 200 being carried out the CP1 time clock in the moment of latches data is called state latch edge, is the rising edge of CP1 in embodiment; CP2 scanning impulse is the two divided-frequency signal of CP1 time clock, and effective triggering edge of the CP1 time clock overturn by control CP2 scanning impulse is called status scan edge; In embodiment, status scan is along the negative edge being CP1 time clock, namely the first buffer register 101, second buffer register 102, data combination unit 500 latch and export before state key assignments, existing state key assignments time be engraved in the negative edge of CP1 time clock, therefore, at the rising edge of CP1 time clock, the front state key assignments that data combination unit 500 exports, existing state key assignments enter stable state, eliminate the impact of aforesaid nondeterministic statement.
If effective triggering edge that Clock pulse CP 1 gated sweep pulse CP2 overturns is negative edge, then the invalid triggering edge that Clock pulse CP 1 gated sweep pulse CP2 overturns is rising edge; If effective triggering edge that Clock pulse CP 1 gated sweep pulse CP2 overturns is rising edge, then the invalid triggering edge that Clock pulse CP 1 gated sweep pulse CP2 overturns is negative edge.The invalid triggering edge that Clock pulse CP 1 gated sweep pulse CP2 overturns is called state latch edge; In embodiment, status scan is along the negative edge being CP1 time clock, and state latch is along the rising edge being CP1 time clock.
4 existing state key assignments that status code register 200 data output end exports and 4 front state key assignments form 8 status codes jointly.
8 described status codes are used for current state and the mode of operation of recognition matrix formula keyboard.Such as, in the present embodiment, the status code pressed without key is 11111111; The status code of S1 key singly-bound push is 11111010; S1 key singly-bound presses and the status code maintained is 10101010; The status code of S1 key singly-bound releasing operation is 10101111; The status code of S2 key singly-bound push is 11110110; The status code of S4 key singly-bound push is 11110101; The S1 push of S2+S1 combination operation, represents that after first pressing S2, maintain at S2 the operation that the state pressed presses S1 again, the status code of this operation is 01100010.
Scrambler 300 is for being converted to key number by status code.In embodiment, be provided with 6 effective keyboard operations and state, comprise:
The singly-bound push of operation 0: button S1, key number is 0000;
The singly-bound push of operation 1: button S2, key number is 0001;
The singly-bound push of operation 2: button S3, key number is 0010;
Operation 3: button S3 singly-bound press after maintenance state, key number is 0011;
After operation 4: button S4 singly-bound is pressed, then the Macintosh operation of the S2 that pushes button, key number is 0100;
The singly-bound releasing operation of operation 5: button S1, key number is 0101.
The status code obtained according to afore mentioned rules and key number are shown in coding schedule 1:
Table 1 coding schedule
| Keyboard operation | Status code (address) | Key number (storage data) |
| S1 singly-bound is pressed | 11111010 | 0000 |
| S2 singly-bound is pressed | 11110110 | 0001 |
| S3 singly-bound is pressed | 11111001 | 0010 |
| Maintenance pressed by S3 singly-bound | 10011001 | 0011 |
| S4+S2 combination operation | 01010100 | 0100 |
| S1 singly-bound discharges | 10101111 | 0101 |
| Other operation or states | ******** | 1111 |
Scrambler 300 is combinational logic circuit, and design circuit meets the logical relation of table 1.
The scrambler 300 of embodiment is preferably made up of ROM (read-only memory) 301.ROM (read-only memory) 301 has 8 bit address, and totally 2
8individual 4 binary storage cells.6 effective keyboard operations and state have 6 effective status codes, corresponding 6 effective keys number; Using the address A7 ~ A0 of status code as ROM (read-only memory) 301, in the storage unit corresponding with 6 effective status codes, using corresponding key number as the write of storage data.The status code produced outside 6 effective keyboard operations and state is disarmed state code, and what other operations namely in table 1 or state produced is disarmed state code; In other storage unit, all write invalid keys number, invalid key number is a value outside 6 effective keys number, and in embodiment, invalid key number is 1111.
ROM (read-only memory) 301 is operated in data output state always.When ROM (read-only memory) 301 has sheet selected control system, data output cushioning control function, its sheet selected control system, data should be made to export cushioning control and to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can increase as required, or reduces, and now, only need select the ROM (read-only memory) 301 matched therewith.If the selection that the number of bits of key number is M, M value should meet 2
mbe more than or equal to the quantity sum of effective key number and invalid key number.When matrix keyboard has N bit keyboard status signal to export, ROM (read-only memory) 301 needs the input of 2 × N bit address, and M-bit data exports.
If need increase and decrease button operation function or adjustment button operation function, only need revise table 1 as required, amended content be re-write the storage content of ROM (read-only memory) 301.
In embodiment, when matrix keyboard S1 singly-bound is pressed, the state latch of the CP1 time clock of scrambler 300 after S1 singly-bound is pressed along starting, to the state latch edge of next CP1 time clock, output terminal C3 ~ C0 run-out key number 0000 of encoding; When matrix keyboard S2 singly-bound is pressed, the state latch of the CP1 time clock of scrambler 300 after S2 singly-bound is pressed along starting, to the state latch edge of next CP1 time clock, run-out key number 0001; After matrix keyboard first presses S4, then press S2, the state latch of the CP1 time clock of scrambler 300 after S2 Macintosh is pressed along starting, to the state latch edge of next CP1 time clock, run-out key number 0100; When matrix keyboard S1 singly-bound discharges, the state latch of the CP1 time clock of scrambler 300 after the release of S1 singly-bound along starting, to the state latch edge of next CP1 time clock, run-out key number 0101; Therefore can find out, when identify be effective button operation of matrix keyboard time, the state latch of the CP1 time clock of scrambler 300 after this effective button operation is along starting, to the state latch edge of next CP1 time clock, output duration is effective key number of CP1 width clock cycle.
In embodiment, when matrix keyboard S3 singly-bound is pressed, the state latch of the CP1 time clock of scrambler 300 after S3 singly-bound is pressed along starting, to the state latch edge of next CP1 time clock, run-out key number 0010; At the state latch of ensuing CP1 time clock along starting, to S3 singly-bound press maintenance state terminate after next CP1 time clock state latch edge, scrambler 300 run-out key number 0011; Therefore can find out, when identify be the maintenance state of matrix keyboard time, the duration of duration and this maintenance state that scrambler 300 exports effective key number adapts.
When the state of keyboard or when being operating as outside the effective keyboard operation of 6 described in table 1 and state, scrambler 300 exports invalid key numbers 1111.Be no matter export effective key number, or export invalid key number, the moment that scrambler 300 changes output content is the state latch edge of CP1 time clock; In embodiment, the moment that scrambler 300 changes output content is the rising edge of CP1 time clock.
The cycle of CP1 time clock is the scan period of matrix keyboard.The keyboard scan cycle, when more than 20ms, can avoid the impact of keyboard shake effectively; The keyboard scan cycle, when below 100ms, is unlikely to omit keyboard operation; Therefore, the cycle of CP1 time clock should control at 20 ~ 100ms.
The cycle request of CK sampling pulse is not more than the cycle of CP1 time clock, like this, alternately key assignments is obtained on each triggering edge of the two divided-frequency signal CP2 scanning impulse of CP1, when namely obtaining status code, can ensure that 4 key assignments that row status register 404, row status register 403 export are always the last state of matrix keyboard.The special case of CK sampling pulse directly uses CP1 time clock as CK sampling pulse.
Fig. 6 is the circuit diagram of the keyboard state change pulse generation unit of the embodiment of the present invention.When identify be effective button operation of matrix keyboard time, the state latch of the CP1 time clock of scrambler 300 after this effective button operation is along starting, to the state latch edge of next CP1 time clock, output duration is effective key number of CP1 width clock cycle.Receive the device that described matrix keyboard exports, need the moment to inquire about the output of matrix keyboard, obtain key number.The period distances of inquiry must be less than the cycle of CP1 time clock.
Whether the key number that circuit shown in Fig. 6 is used for the output of judgment matrix formula keyboard changes, when the key number that matrix keyboard exports changes, export keyboard state change pulse, for the key number that the receiving trap receiving matrix formula keyboard of auxiliary moment configuration keyboard exports, such as, using the interrupt request singal of keyboard state change pulse as receiving trap.
Circuit shown in Fig. 6 is made up of delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606.Delay buffer 601 is made up of 4 edge triggered flip flops only with Trigger Function, and the trigger input of 4 edge triggered flip flops is the received pulse input end of delay buffer 601, is all connected to the CP1 output terminal of clock pulse of oscillator 500; Delay buffer 601 carries out latches data on the state latch edge of CP1 time clock.
Delay buffer 601 carries out delay disposal respectively for the 4 bit data C3 ~ C0 of the coding output terminal to scrambler 300.4 data input pin D63 ~ D60 of delay buffer 601 are connected to the coding output terminal C3 ~ C0 of scrambler 300, and the data of 4 corresponding outputs of data output end Q63 ~ Q60 of delay buffer 601 are C31 ~ C01; C31 ~ C01 is after the first-level buffer of delay buffer 601, and its signal postpones a CP1 clock cycle than C3 ~ C0, Figure 7 shows that the waveform correlation schematic diagram of the keyboard valid function of the embodiment of the present invention.The T1 being located at CP1 time clock is interval, there is a valid function in matrix keyboard, the valid function of embodiment comprises: S1 singly-bound is pressed, S2 singly-bound is pressed, S3 singly-bound is pressed, the S1 of S4+S1 combination operation presses, the S2 of S4+S2 combination operation presses, the release of S1 singly-bound.On the next state latch edge of a valid function, the rising edge namely in Fig. 7 after CP1 time clock T1 interval, coding C3 ~ C0 that scrambler 300 exports changes; Interval at T2, scrambler 300 exports the efficient coding C3 ~ C0 of one-period; At T3, T4 and interval afterwards, coding C3 ~ C0 that scrambler 300 exports changes again and enters maintenance state, this maintenance state may be the maintenance state that such as S1 singly-bound presses below, export invalid key number, also may be the maintenance state that S3 singly-bound presses below, export effective key number, until valid function next time.
Coding C3 ~ C0 that D6 pulse in Fig. 7 schematically illustrates scrambler 300 output is in maintenance state, and change, does not still change, there is not described D6 pulse in side circuit.As shown in Figure 7, D6 pulse is low level, and the coding C3 ~ C0 schematically illustrating scrambler 300 output is in maintenance state, not change; D6 pulse is high level, schematically illustrates efficient coding C3 ~ C0 that scrambler 300 exports one-period.Q6 reflection in Fig. 7 be the situation of change of C31 ~ C01, obviously, Q6 postpones a CP1 clock cycle than D6.Equally, there is not described Q6 pulse in side circuit.
In Fig. 7, coding C3 ~ C0 that scrambler 300 exports is in maintenance state, not change, still change, the actual logical circuit be made up of 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606 completes.4 XOR gate, 1 of encoding in output terminal C3 ~ C0 with scrambler 300 is respectively corresponding, and input is respectively input, the output signal of 4 delay buffers 601.Such as, two input signals of XOR gate 602 are respectively C0 and C01, and C01 postpones a CP1 clock cycle than C0, and therefore, when C0 changes, XOR gate 602 exports the positive pulse of 1 CP1 width clock cycle; When C0 is a CP1 wide variety clock cycle signal, XOR gate 602 exports the positive pulse of 2 CP1 width clock cycle.XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1 ~ C3 changes respectively, and principle is with to judge whether C0 changes identical.The output terminal of XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 is connected to or the input end of door 606 respectively, or whether door 606 changes for comprehensive descision C0 ~ C3, as long as C0 ~ C3 changes, or namely door 606 exports keyboard state change pulse F, this pulse is positive pulse.
In embodiment, the 8D trigger 74HC273 that delay buffer 601 selects rising edge to trigger.
Delay buffer 601 can also adopt other schemes, such as, adopts RC circuit, utilizes 4 RC circuit to postpone C0 ~ C3 respectively; If be less than a CP1 clock cycle time delay of RC circuit, when then scrambler 300 exports the efficient coding C3 ~ C0 of one-period, start and export efficient coding C3 ~ C0 to terminate all to produce a keyboard state change pulse at output efficient coding C3 ~ C0, the width of keyboard state change pulse equals RC circuit delay time; If be more than or equal to a CP1 clock cycle time delay of RC circuit, when then scrambler 300 exports the efficient coding C3 ~ C0 of one-period, produce a keyboard state change pulse when exporting efficient coding C3 ~ C0 and starting, pulse width is more than or equal to 2 CP1 clock cycles.Require to be no more than the time delay of RC circuit 2 CP1 clock cycles, fail to report in order to avoid produce.
In embodiment, the first buffer register 101 carries out latches data at the negative edge of CP2 scanning impulse, and the second buffer register 102 carries out latches data at the rising edge of CP2 scanning impulse.Also the first buffer register 101 can be adopted to carry out latches data at the rising edge of CP2 scanning impulse, second buffer register 102 carries out the mode of latches data at the negative edge of CP2 scanning impulse, now, the output of data combination unit 500 forms status code with existing state key assignments in the posterior mode of front, front state key assignments.The status code that existing state key assignments forms in the posterior mode of front, front state key assignments is equally applicable to the present invention.
In embodiment, change the input connected mode of data combination unit 500, status code can be formed with existing state key assignments in the posterior mode of front, front state key assignments equally.
In described invention circuit, by the location to single key stroke, Macintosh operation, keyboard maintenance state of operation, the status code converting same binary length to is controlled by CP1 time clock, CP2 scanning impulse, adopt the mode of Unified coding to process, the operation of single key stroke, Macintosh, keyboard maintain state of operation and are only embodied in the not the same of status code; If need increase and decrease button operation function or adjustment button operation function, do not need amendment keyboard scanning circuit structure, only need upgrade scrambler 300, namely re-write the storage content upgrading ROM (read-only memory) according to the state code table after increase and decrease.Described invention circuit does not use the microcontroller such as single-chip microcomputer, ARM, without working procedure, and reliable operation.
Claims (10)
1. a matrix keyboard scanner uni coding circuit, is characterized in that, is made up of matrix keyboard, the first buffer register, the second buffer register, status code register, scrambler, data combination unit;
Described matrix keyboard scanner uni coding circuit carries out synchro control by scanning impulse and time clock;
Described matrix keyboard has that X is capable, Y row, is provided with N bit keyboard status signal output; Described N bit keyboard status signal is level signal; Described N=X+Y;
Described first buffer register and the second buffer register equal N position binary register; The N bit data input end of described first buffer register is connected to N bit keyboard status signal output successively; The N bit data input end of described second buffer register is connected to N bit keyboard status signal output successively;
The received pulse input end of described first buffer register and the second buffer register is connected to scanning impulse;
Described data combination unit is provided with first via N bit data input end, the second road N bit data input end and 2 × N bit data output terminal; Described first via N bit data input end is connected to the N bit data output terminal of the first buffer register successively, and the second road N bit data input end is connected to the N bit data output terminal of the second buffer register successively;
Described data combination unit is also provided with data select signal end; Described data select signal end is connected to scanning impulse; In 2 × N bit data output of data combination unit, when described scanning impulse is low level, first via N bit data is front, and the second road N bit data is rear; When described scanning impulse is high level, first via N bit data is rear, and the second road N bit data is front; Or in 2 × N bit data output of data combination unit, when described scanning impulse is low level, first via N bit data is rear, and the second road N bit data is front; When described scanning impulse is high level, first via N bit data is front, and the second road N bit data is rear;
Described status code register is 2 × N position binary register; 2 × N bit data input end of status code register is connected to 2 × N bit data output terminal of data combination unit;
The received pulse input end of described status code register is connected to time clock; Described matrix keyboard is controlled to obtain N bit keyboard status signal by sampling pulse;
Described scrambler has 2 × N position coding input end, and described 2 × N position coding input end is connected to 2 × N bit data output terminal of status code register.
2. matrix keyboard scanner uni coding circuit according to claim 1, is characterized in that: the cycle of described time clock is 20 ~ 100ms; Described scanning impulse is the two divided-frequency signal of time clock; The cycle of described sampling pulse is not more than the cycle of described time clock.
3. matrix keyboard scanner uni coding circuit according to claim 2, is characterized in that: the invalid triggering edge of described time clock gated sweep pulse upset is called state latch edge; Described status code register carries out latches data on the state latch edge of time clock; Described first buffer register is when the rising edge of scanning impulse carries out latches data, and the second buffer register carries out latches data at the negative edge of scanning impulse; Or described first buffer register is when the negative edge of scanning impulse carries out latches data, and the second buffer register carries out latches data at the rising edge of scanning impulse.
4. matrix keyboard scanner uni coding circuit according to claim 1, is characterized in that: 2 × N bit data output terminal of described status code register exports the status code of 2 × N position; Described status code is made up of effective status code and disarmed state code; The key number that described scrambler exports is made up of with invalid key number effective key number; Described effective status code is produced by effective keyboard operation or state, correspondingly when scrambler inputs each effective status code exports corresponding effectively key number; Described disarmed state code is produced by invalid keyboard operation or state, all correspondingly when scrambler inputs all disarmed state codes exports invalid key number.
5. matrix keyboard scanner uni coding circuit according to claim 4, it is characterized in that: described scrambler has M position key output terminal, the selection of M value should meet 2
mbe more than or equal to the quantity sum of effective key number and invalid key number.
6. matrix keyboard scanner uni coding circuit according to claim 5, it is characterized in that: also comprise keyboard state change pulse generation unit, whether the key number exported for judgment matrix formula keyboard changes, when the key number that matrix keyboard exports changes, export keyboard state change pulse.
7. matrix keyboard scanner uni coding circuit according to claim 6, is characterized in that: described keyboard state change pulse generation unit by M position delay buffer, a M XOR gate and or door form; The M position key number that M position delay buffer is used for matrix keyboard exports carries out signal delay respectively; The input of M XOR gate is respectively input, the output signal of M position delay buffer; The output of M XOR gate is connected to or the input end of door respectively; Or the output terminal of door exports keyboard state change pulse.
8. matrix keyboard scanner uni coding circuit according to claim 1, is characterized in that: also comprise oscillator; The pulse of described oscillator output clock, scanning impulse and sampling pulse.
9. matrix keyboard scanner uni coding circuit according to claim 1, is characterized in that: described matrix keyboard is made up of X capable-Y row key-press matrix, row three-state buffer, row three-state buffer, row status register, column-shaped state register; The line of all key-press matrixs is connected to the output terminal of row three-state buffer respectively, and the alignment of all key-press matrixs is connected to the output terminal of row three-state buffer respectively; All input ends of row three-state buffer and row three-state buffer are connected to low level; The line of all key-press matrixs is connected to the input end of row status register respectively, and the alignment of all key-press matrixs is connected to the input end of row status register respectively; The output terminal of described row status register and the output terminal of row status register form keyboard state signal output part jointly.
10. matrix keyboard scanner uni coding circuit according to claim 9, it is characterized in that: described row three-state buffer the low level of sampling pulse enable effective time, latches data, row three-state buffer are enable effectively at the high level of sampling pulse, row status register carries out latches data at the negative edge of sampling pulse to require row status register to carry out at the rising edge of sampling pulse; Or, row three-state buffer the high level of sampling pulse enable effective time, latches data, row three-state buffer are enable effectively in the low level of sampling pulse, row status register carries out latches data at the rising edge of sampling pulse to require row status register to carry out at the negative edge of sampling pulse.
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| CN201810338494.2A CN108536306B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard scanning and coding method |
| CN201610003604.0A CN105468164B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard scanner uni coding circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106549676A (en) * | 2016-10-28 | 2017-03-29 | 上海顺久电子科技有限公司 | Low-power consumption matrix keyboard and the power switch circuit using the matrix keyboard |
| CN110441150A (en) * | 2019-09-09 | 2019-11-12 | 浙江大学 | Double acting arm material tensile test method and its testing machine |
| CN113327412A (en) * | 2021-08-04 | 2021-08-31 | 深圳宇凡微电子有限公司 | Wireless signal decoding method, device, equipment and system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4414538A (en) * | 1981-12-07 | 1983-11-08 | Teletype Corporation | Keyboard sense gate |
| CN101510127A (en) * | 2009-03-30 | 2009-08-19 | 北京中星微电子有限公司 | Method, apparatus and chip for implementing keyboard module composite key function |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4291385A (en) * | 1973-12-17 | 1981-09-22 | Hewlett-Packard Company | Calculator having merged key codes |
| JPH0682314B2 (en) * | 1985-05-17 | 1994-10-19 | 富士通株式会社 | Keyboard simultaneous keystroke shift processing method |
| CN1159641C (en) * | 2001-07-11 | 2004-07-28 | 威盛电子股份有限公司 | Keyboard instruction fetch device for notebook computer |
| CN1192300C (en) * | 2002-11-20 | 2005-03-09 | 威盛电子股份有限公司 | Keyboard control circuit of universal serial bus interface |
| US20090128373A1 (en) * | 2007-11-15 | 2009-05-21 | Polycom, Inc. | Twin-contact keyboard arrangement |
| CN103226391B (en) * | 2013-05-22 | 2015-12-23 | 湖南工业大学 | A kind of Scan orientation method of independent keyboard |
| CN103279197B (en) * | 2013-06-08 | 2015-12-09 | 湖南工业大学 | A kind of Scan orientation method of keyboard |
-
2016
- 2016-01-05 CN CN201610003604.0A patent/CN105468164B/en active Active
- 2016-01-05 CN CN201810338494.2A patent/CN108536306B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4414538A (en) * | 1981-12-07 | 1983-11-08 | Teletype Corporation | Keyboard sense gate |
| CN101510127A (en) * | 2009-03-30 | 2009-08-19 | 北京中星微电子有限公司 | Method, apparatus and chip for implementing keyboard module composite key function |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
Non-Patent Citations (1)
| Title |
|---|
| 怯肇乾: "嵌入式人机界面中的键盘及其接口设计", 《单片机与嵌入式系统应用》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106549676A (en) * | 2016-10-28 | 2017-03-29 | 上海顺久电子科技有限公司 | Low-power consumption matrix keyboard and the power switch circuit using the matrix keyboard |
| CN106549676B (en) * | 2016-10-28 | 2019-09-17 | 青岛海信电器股份有限公司 | The power switch circuit of low-power consumption matrix keyboard and the application matrix keyboard |
| CN110441150A (en) * | 2019-09-09 | 2019-11-12 | 浙江大学 | Double acting arm material tensile test method and its testing machine |
| CN110441150B (en) * | 2019-09-09 | 2020-08-04 | 浙江大学 | Double-movable-arm material tensile test method and test machine thereof |
| CN113327412A (en) * | 2021-08-04 | 2021-08-31 | 深圳宇凡微电子有限公司 | Wireless signal decoding method, device, equipment and system |
Also Published As
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| CN108536306A (en) | 2018-09-14 |
| CN108536306B (en) | 2021-03-16 |
| CN105468164B (en) | 2018-06-15 |
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