CN105450199B - Cascade integral comb filter and its design method with quick settling time - Google Patents
Cascade integral comb filter and its design method with quick settling time Download PDFInfo
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- CN105450199B CN105450199B CN201510807427.7A CN201510807427A CN105450199B CN 105450199 B CN105450199 B CN 105450199B CN 201510807427 A CN201510807427 A CN 201510807427A CN 105450199 B CN105450199 B CN 105450199B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0201—Wave digital filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0202—Two or more dimensional filters; Filters for complex signals
- H03H2017/0204—Comb filters
Abstract
Cascade integral comb filter and its design method with quick settling time, are related to digital filter.The cascade integral comb filter with quick settling time is equipped with: digital control module, it is mainly used for monitoring system parameter, the system parameter includes but is not limited to electrification reset and power down enabled, output data rate, input channel, channel gain etc., as the control signal for enabling fast quick-recovery；High low speed cic filter is mainly used for for the low precision bit stream of high-speed that front end analogue sigma-delta modulator exports being converted into the output of low rate high-accuracy digital signal；The input of the high low speed cic filter terminates front end analogue sigma-delta modulator output end, the output end of high low speed cic filter exports low rate high-accuracy digital signal, and the control signal input of high low speed cic filter connects the enabled fast quick-recovery control signal output of digital control module.
Description
Technical field
The present invention relates to digital filters, more particularly, to a kind of cascaded integrator-comb with quick settling time
(CIC:Cascaded Integrator Comb) filter and its design method.
Background technique
Sigma-delta ADC is mainly made of simulation sigma-delta modulator and digital down filter, and digital down filter is usual
Using cic filter, the order of cic filter is higher, and settling time is longer.Such as document [1] " Low-Noise 24-bit
Delta Sigma ADC:ISL26132, ISL26134 " (Intersil Corporation, 2014.12) use third order sigma-delta
Modulator and quadravalence cic filter, settling time are four output data periods；Document [2] " 24-Bit Analog-to-
Digital Converter For Bridge Sensors:ADS1231 " (TEXAS INSTRUMENTS Corporation,
2010.12) third order sigma-delta modulator and quadravalence cic filter are used, settling time is four output data periods；Document [3]
" CS1232 user's manual " (core sea science and technology, 2011.08) uses third order sigma-delta modulator and quadravalence cic filter, settling time
For four output data periods；Document [4] " 24 A/D converter chips of preposition ultra-low noise amplifier: HX530 " (Hai Xin
Science and technology, 2012) second order sigma-delta modulator and quadravalence cic filter are used, settling time is four output data periods.With four
For rank cic filter, it is assumed that the output data period is 100mS (10Hz), then when chip powers on, chip enters from power-down mode
When operating mode, output data rate change, input channel switches or channel gain changes, ADC chip needs the foundation of 400mS
Time can just export first effective change data, and ADC chip can just export an effectively conversion number at interval of 100mS later
According to.
The disadvantage of high-order cic filter output data settling time length, largely affects the stand-by time of equipment,
Especially for battery powered equipment.By taking electronic scale as an example, in order to reduce stand-by power consumption, it will usually in standby mode season
ADC chip and sensor are intermittent into power-down mode, operating mode.For same standby mode weigh response speed,
The time that system is in power-down mode is longer, and the time for being in operating mode is shorter, i.e., system enters ADC chip after operating mode
The faster effective change data of output, then system standby power consumption is lower.By taking the 1s response time as an example, filtered using quadravalence CIC as above
Device, system enters after operating mode need 400ms after weight could be judged, so system is in the time of power-down mode
Up to 600ms.If the settling time of cic filter can be accelerated, 100ms is only such as needed to wait for, then same response speed, standby
Time reaches original 4 times.
High speed cic filter compares low speed cic filter, although precision is lost, settling time is shorter.Such as document
[1] the ratio of precision 10Hz of 80Hz is 1.4 low in, but settling time is 8 times of 10Hz；The ratio of precision 10Hz of 80Hz in document [2]
Low 1.5, but settling time is 8 times of 10Hz；The ratio of precision 10Hz of 80Hz is 1.1 low in document [3], but settling time is
8 times of 10Hz；The ratio of precision 5Hz of 10Hz is 0.4 low in document [4], but settling time is 2 times of 5Hz.So can be in system
When parameter change, using the feature that high speed cic filter settling time is short, the output data of cic filter is adjusted by dynamic
Rate realization quickly exports effective change data.
Summary of the invention
The purpose of the present invention is to provide a kind of cascaded integrator-comb (CIC:Cascaded with quick settling time
Integrator Comb) filter and its design method.
Cascade integral comb filter of the present invention with quick settling time is equipped with:
Digital control module, is mainly used for monitoring system parameter, the system parameter include but is not limited to electrification reset with
Power down enabled, output data rate, input channel, channel gain etc., as the control signal for enabling fast quick-recovery；
High low speed cic filter is mainly used for the low precision bit stream of the high-speed for exporting front end analogue sigma-delta modulator and turns
Change the output of low rate high-accuracy digital signal into；
The input of the high low speed cic filter terminates front end analogue sigma-delta modulator output end, high low speed CIC filtering
The output end of device exports low rate high-accuracy digital signal, and the control signal input of high low speed cic filter connects digital control
The enabled fast quick-recovery control signal output of module.
The design method of cascade integral comb filter with quick settling time, comprising the following steps:
(1) digital control module detects whether each system parameter changes, if changing, enters step (2)；If not
It changes, then enters step (8).
(2) SEL [1:0]=2 ' b00, the rising edge of first output data clock, cic filter export the down-sampled factor
For the filter value of the cic filter of R/4.
(3) the failing edge of first output data clock, SEL [1:0]=2 ' b01.
(4) SEL [1:0]=2 ' b01, the rising edge of second output data clock, cic filter export the down-sampled factor
For the filter value of the cic filter of R/2.
(5) the failing edge of second output data clock, SEL [1:0]=2 ' b10.
(6) SEL [1:0]=2 ' b10, the rising edge of third output data clock, cic filter export the down-sampled factor
For R/2 cic filter by the cumulative filter value being averaging of last time and current-period data.
(7) the failing edge of third output data clock, SEL [1:0]=2 ' b11.
(8) SEL [1:0]=2 ' b11, the 4th and the rising edge of output data clock later, cic filter output drop are adopted
Like factor is the filter value of the cic filter of R.
Cic filter of the invention is mainly used for handling the high-speed bitstream that sigma-delta modulator exports, and filters out Σ-
High-frequency quantization noise included in Delta modulator output signal, while carrying out signal down.
Present invention utilizes common device for ADC conversion accuracy in standby mode with respect to the low feature of working condition,
Propose a kind of method of system design cic filter.The design method spy short using high speed cic filter settling time
Point combines high speed cic filter and low speed cic filter, when system parameter changes, several data for exporting at first
It is exported by high speed cic filter, to effectively shorten cic filter settling time；And it is completely set up to low speed cic filter
Get up, data later all by its output, in turn ensure system in working condition to ADC requirement with high accuracy.Moreover, when low
After fast cic filter is set up, if being not turned off high speed cic filter, when output data rate needs to switch from low speed
When to high speed, high speed cic filter can export effective change data at once, not need any settling time.Due to low speed CIC
The gain of filter is the power relationship of the 2 of high speed cic filter, therefore only increasing need to can be realized by simple shifting function
Beneficial is consistent, does not need additional gain adjustment circuit.
Detailed description of the invention
Fig. 1 is the overall circuit configuration block diagram of the embodiment of the present invention.
Fig. 2 is the cic filter structural block diagram of the embodiment of the present invention.
Fig. 3 is the high low speed cic filter circuit structure of the embodiment of the present invention.
Specific embodiment
The present invention is made of digital control module 1, high low speed cic filter 2, and overall circuit block diagram is as shown in Figure 1.
The input signal of digital control module 1 be each system parameter, including electrification reset and exit power down, output data speed
Rate, channel gain, input channel etc..When any system parameter changes, selection signal SEL [1:0]=2 ' b00 is enabled, often
SEL [1:0] value adds 1 when one output data clock comes, until SEL [1:0]=2 ' b11.
Fig. 2 is cic filter structural block diagram, mainly by integrator (1/ (1-z-1))L, it is down-sampled switch and differentiator (1-
z-1)LIt constitutes, wherein X (z) is the output signal of sigma-delta modulator, and Y (z) is the output signal of cic filter, and L indicates CIC filter
The order of wave device, if R indicates that the working frequency of integrator is FS, then the working frequency of differentiator is FS/ R, i.e. cic filter
Output data rate is FS/R.X (z) is by integrator with frequency FSIt is integrated, then by differentiator with frequency FS/ R is carried out
Output data Y (z) after differential.
Fig. 3 is high low speed cic filter circuit structure, using quadravalence CIC structure, whereinUsing edge triggered flip flop reality
It is existing,It is realized using full adder,Indicate that the working frequency of each differentiator is followed successively by integrator working frequency
4/R, 2/R and 1/R, [W:0] [W+4:0] [W+8:0] indicate data bit width.
When system parameter changes, SEL [1:0] value is incremented to 2 ' b11 by 2 ' b00, and is maintained at 2 ' b11, i.e., and
One data is exported by the cic filter that the down-sampled factor is R/4, and second data is filtered by the CIC that the down-sampled factor is R/2
Device output, third data will be defeated after last time and the accumulated averaging of current data by the cic filter that the down-sampled factor is R/2
Out, the 4th and data later are exported by the cic filter that the down-sampled factor is R.It is equally 100mS with the output data period
For, the settling time of cic filter is increased to 100mS by 400mS.
The method of system design cic filter the following steps are included:
(1) digital control module detects whether each system parameter changes, if changing, enters step (2)；If not sending out
(8) changing enters step.
(2) SEL [1:0]=2 ' b00, the rising edge of first output data clock, it is R/ that filter, which exports the down-sampled factor,
The filter value of 4 cic filter.
(3) the failing edge of first output data clock, SEL [1:0]=2 ' b01.
(4) SEL [1:0]=2 ' b01, the rising edge of second output data clock, it is R/ that filter, which exports the down-sampled factor,
The filter value of 2 cic filter.
(5) the failing edge of second output data clock, SEL [1:0]=2 ' b10.
(6) SEL [1:0]=2 ' b10, the rising edge of third output data clock, it is R/ that filter, which exports the down-sampled factor,
2 cic filter is by the cumulative filter value being averaging of last time and current-period data.
(7) the failing edge of third output data clock, SEL [1:0]=2 ' b11.
(8) SEL [1:0]=2 ' b11, the 4th and the rising edge of output data clock later, filter output it is down-sampled because
Son is the filter value of the cic filter of R.
Claims (1)
1. the cic filter with quick settling time, it is characterised in that be equipped with:
Digital control module, for monitoring system parameter, output enables the control signal of fast quick-recovery；
High low speed cic filter, the low precision bit stream of high-speed for exporting front end analogue sigma-delta modulator are converted into low speed
The output of rate high-accuracy digital signal；
The input of the high low speed cic filter terminates front end analogue sigma-delta modulator output end, high low speed cic filter
Output end exports low rate high-accuracy digital signal, and the control signal input of high low speed cic filter connects digital control module
Enabled fast quick-recovery control signal output；
The system parameter includes that electrification reset and power down be enabled, output data rate, input channel, channel gain；
The design method of the cic filter with quick settling time is as follows:
(1) digital control module detects whether each system parameter changes, if changing, enters step (2)；If not occurring
(8) variation, then enter step；
(2) SEL [1:0]=2 ' b00, the rising edge of first output data clock, it is R/4 that cic filter, which exports the down-sampled factor,
Cic filter filter value；
(3) the failing edge of first output data clock, SEL [1:0]=2 ' b01；
(4) SEL [1:0]=2 ' b01, the rising edge of second output data clock, it is R/2 that cic filter, which exports the down-sampled factor,
Cic filter filter value；
(5) the failing edge of second output data clock, SEL [1:0]=2 ' b10；
(6) SEL [1:0]=2 ' b10, the rising edge of third output data clock, it is R/2 that cic filter, which exports the down-sampled factor,
Cic filter by the cumulative filter value being averaging of last time and current-period data；
(7) the failing edge of third output data clock, SEL [1:0]=2 ' b11；
(8) SEL [1:0]=2 ' b11, the 4th and the rising edge of output data clock later, cic filter output it is down-sampled because
Son is the filter value of the cic filter of R.
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