CN103795412A - Single-cycle oversampling digital-to-analog converter - Google Patents
Single-cycle oversampling digital-to-analog converter Download PDFInfo
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Abstract
The invention relates to a single-cycle oversampling digital-to-analog converter, specifically, an oversampling delta-sigma digital-to-analog converter which is suitable for single-cycle operation. According to a preferable embodiment of the invention, only one multiply-accumulate processor is in a digital filtering state so as to extract an output sequence R (I); and a system controller generates precise-timing modulator enable signals (EnM) and digital filter enable signals (EnF) to coordinate and activate certain circuit elements and manage the energy consumption of the system.
Description
Technical field
The present invention relates to analogue-to-digital converters.What especially, it was paid close attention to is the δ-σ over-sampling number mould converter that is applicable to fill order's periodic conversion.
Background technology
Although the signal of real world is analog signal, we need to use modulus (A/D) transducer to be transformed into numeric field conventionally.Circuit designer has on purpose carries out this conversion because it be a kind of at present for transmitting, the effective ways of Storage and Processing digital signal.For example, audio signal of a digitized representation, this just allows almost not have by a CD Player use disc storage of error.Complicated signal processing may also need A/D conversion, because only use digital computer or dedicated digital signal processor at numeric field, such signal processing is feasible.Signal is processed also particularly useful at numeric field, for example, in fields such as biomedical applications, the precision needing is provided to the task of magnetic resonance imaging (MRI) and so on.
Oversampler method has become popular A/D transducer recently, because than traditional analog digital conversion method, they have avoided the many difficulties that run into.This is because this transducer has certain attribute, is difficult to realize in integrated device electronics.Wherein the most important thing is to need to use the analog filter and the high-precision analog circuit that are easily subject to Noise and Interference.The advantage of traditional switch technology is to use a relatively low sample frequency, conventionally input signal (being the twice of signal bandwidth) under Nyquist rate.
Traditional A/D converter system requirement, in the time sampling at Nyquist rate, low pass anti-confusion filtering device is inputted at it, the signal of the outer composition of frequency band in attenuate high frequency noise amplitude and pseudo-frequency band.The frequency characteristic of this filter is to be determined by the analog element accuracy of manufacture.
On the other hand, over-sampling A/D transducer can use the analog element of simple and relative high tolerance, but needs fast and the suitable Digital Signal Processing level of complexity.They are a frequency far above under Nyquist rate, and modulation analog input becomes a simple digital code, the word of normally single position.These modulators exchange solution timely for by sacrificing the resolution of amplitude, so can use coarse analog circuit.Use high frequency modulated can eliminate the needs of simulation anti-confusion filtering device to the unexpected cut-out of input A/D transducer.Wave digital lowpass filter can make the output smoothing of digital modulator, and under Nyquist rate resampling, before they are blended in the frequency band of signal, the signal of attenuate acoustic noise, interference and radio-frequency component.Another digital filter is used in output extraction unit encoding and is converted to the signal that high word speed digital pulse coding is modulated.
Over-sampling A/D converter extensive use digital processing, has utilized such fact, and integrated circuit technique is compared for providing accurate analog circuit to be more suitable for for fast digital circuits is provided.Because their sample rate need to be much higher than Nyquist rate conventionally, traditional over-sampling A/D transducer is generally used for middling speed digital application, as digital audio, digital telephone and data communication.Such application need to be produced A/D transformation result continuously from a single input source.Therefore,, for traditional A/D transducer, a definition is unimportant good settling time.In addition, the electricity consumption of traditional over-sampling A/D transducer is relatively high often, because converter circuit must keep activating, produces continuous transformation result.
But due to its special resolution and precision, over-sampling A/D transducer also can be used in the tasks such as data acquisition, Industry Control and surveying instrument.In many such application, if desirable, come from a given input source, only there is the result of a conversion.For example, an analog input signal can be selected from many incoherent separate sources, and these derive from an input multiplexer may be maybe according to the sampling of required function in the incoherent time interval.In this application, before a new input signal is provided, A/D transducer can only be that a given input signal completes conversion.Therefore,, in single conversion or " single cycle conversion " application, the correlation between output data oversampling and powerful Time Continuous transformation result is unessential.
Traditional over-sampling A/D transducer is not suitable for fill order A/D conversion, because they are in order repeatedly to sample given analog input signal, to extend a period of time, produces multiple transformation results under the speed of the twice higher than input signal bandwidth.Such A/D transducer has complicated digital filtering level, lacks and also can make to input multiplexing difficulty the settling time defining.In addition, because traditional common continued operation of over-sampling A/D transducer carrys out time expand, they are not included in the power save circuit of closed portion transducer while use, and this situation is often to occur in monocycle work.
In view of above-mentioned, therefore need to provide one to be applicable to providing single A/D over-sampling A/D transducer of conversion.
Providing one to comprise that circuit optionally opens and closes part transducer in the time not needing to change, carry out over-sampling A/D transducer of minimization circuit power, is also desirable.
Over-sampling A/D transducer that comprises the digital filter circuit of reduced complexity is provided, and is also desirable.
Providing one to have definition good settling time, to facilitate the A/D converter of the multiplexed over-sampling of input, will be desired in addition.
Summary of the invention
Therefore object of the present invention provides over-sampling A/D transducer that is applicable to carrying out single cycle A/D conversion.
Another object of the present invention is to provide one and comprises minimization circuit power A/D transducer.
Another object of the present invention is to provide over-sampling A/D transducer that comprises the digital filter circuit of reduced complexity.
Further aim of the present invention is to provide one and has the settling time defining, to facilitate the multiplexed over-sampling A/D transducer of input.
Technical solution of the present invention:
According to these and other objects of the present invention, over-sampling δ-σ A/D transducer of applicable single cycle work is described.A/D transducer may comprise δ-σ modulator, decimation filter of digital and a system controller.When receiving a conversion initial signal, system controller can guide the sampling of δ-σ modulator and quantitative simulation input signal, produces a series of pulse density modulated output signal Y (k).Output signal Y (k) is filtered and extracts by digital filter, produce an output word R (
i), this is the numeral of the input signal that is sampled of an expression.In a preferred version of the present invention, only having a product accumulation processor is to be presented on digital filtering state, extracts output signal Y (k).System controller can produce modulators enable signal (EnM) and the digital filter enable signal (EnF) of accurate timing, the element in coordination activation and disconnection A/D change-over circuit and the energy power consumption of minimization system.
Contrast patent documentation: CN202111690U digital to analog converter 201120185263.6.
accompanying drawing explanation:
Under above and other object of the present invention detailed description below, very clear in conjunction with subsidiary drawing, what reference character was indicated is identical element or structure, carries throughout:
Fig. 1 a is the composition module of prior art over-sampling δ-σ A/D converter;
Fig. 1 b is the response diagram of δ-σ modulator under the excitation of an explanation input ramp signal;
Fig. 1 c is the response diagram of two δ-σ modulators under the excitation of an explanation input ramp signal;
Fig. 2 is the schematic diagram of the product accumulation processor of a prior art;
Fig. 3 is the schematic diagram of four product accumulation processors concurrent working of a prior art;
Fig. 4 is the schematic diagram of four product accumulation processors concurrent working of another prior art;
Fig. 5 be one consistent with principle of the present invention and structure over-sampling A/D converter block diagram;
Fig. 6 is and the schematic diagram of part three rank δ-σ modulators of structure consistent with principle of the present invention;
Fig. 7 is a schematic diagram that possible be used for single product accumulation processor device of decimation filter of digital of the present invention.
Embodiment:
What Fig. 1 a showed is the composition module of traditional over-sampling δ-σ A/D transducer 10, and A/D transducer 10 is made up of 3 basic modules: δ-σ modulator 20, finite impulse response (FIR) (FIR) digital filter 30 and system controller 40.In Fig. 1 a, the clock signal that δ-σ modulator 20 produces at system controller 40
guiding under, with a very high speed (manyfold of Nyquist rate) continuous sampling analog input signal V (t), that modulator 20 produces is a series of, depend on input signal V (t) size, and 1 the output sample Y (k) shaking between logic " height " level and " low " level.This causes analog input signal V (t) pulse density modulated, and at one time, the average level of the digital signal Y (k) that modulator 20 is exported approximates the average level of analog input signal V (t).Fig. 1 b has illustrated the response of the single order δ-σ modulator 20 under ramp input signal V (t) excitation.Along with the increase of V (t) quantity, the quantity of digital pulse signal Y (k) logic high has also increased, so the mean value of these pulses has mated current V (t) value.Otherwise along with V (t) quantity reduces, the quantity of the logic high of digital pulse signal Y (k) also reduces, and reflects the value of V (t).
Although a quantification is common, possible multilevel quantization is more suitable for some application.In this application, the resolution of digital signal Y (k) is variable with the quantity of the quantization level providing, and Fig. 1 c has illustrated the response of second order (two) δ-σ modulator 20 under ramp input signal V (t) excitation.Under main three levels in four available levels of second order δ-σ modulator 20 of output, shake, the local mean values of digital signal Y (k) equals the mean value of analog input V (t) like this.Although multidigit adjuster is more complicated than unit modulator, but they are desirable in some applications, because they have avoided in the time that the average amplitude V of input signal (t) is greater than Y (k) maximal density, the saturation problem of quantizer in the unit's of occurring in adjuster.If necessary, the ultimate resolution that such problem can also be mated modulator 20 by convergent-divergent input signal V (t) is avoided.
For after passing through digital filter 30, R (
i) over-sampling that retains to a certain degree of output word is very normal.If needed, further digital processing as low-pass filtering and downwards-sampling numeric word R (
i) may be performed to Nyquist rate, to generate final output signal (not showing).
A schematic diagram that is included in the product accumulation processor 41 in digital filter 30 is presented at Fig. 2.Product accumulation processor 41 comprises three basic modules, multiplier 42, adder 44 and register 46.As shown in Figure 2, length is the filter coefficient sequence S (j) and pulse digital signal Y (k) convolution of n (j=1,2...n).Convolution operation is by multiplier 42, completes the continuous sample of digital signal Y (k) and the continuous coefficients of coefficient sequence S (j) multiplies each other.Conventionally, each clock cycle, each coefficient of sequence S (j) is multiplied by element of Serial No. Y (k).The result of multiplication is to be all accumulated in register 46 by adder 44.Be multiplied by input sample Y (k) afterwards at the coefficient of all coefficient sequence S (j), a complete convolution results can obtain at register 46.Therefore, the coefficient sequence S (j) of product accumulation processor 41 treated length n, needs n clock cycle could produce a complete convolution results conventionally.
If the coefficient sequence S of length n (j) is well-chosen, so all coefficient sequence multiply each other the required time be less than or equal to digital filter 30 output rating B (
), under the speed that is more than or equal to B, a complete convolution results always can obtain at register 46.Such configuration can make A/D transducer 10 under a data rate faster than required output rating B, because an input signal V (t), and generation output word R (
i).But, this is not common way in reality because selected the length n of coefficient sequence, so n clock cycle be less than or equal to output rating B, these A/ D transducer 10 overall performances that often limited (increased speed, but reduced resolution).Therefore,, in great majority application, calculating a required time of complete convolution results is to exceed required output rating B.This means single product accumulation processor 41 can not produce fast enough output word R (
i) to meet required output rating B.
Traditional δ-σ A/D transducer is avoided this problem by multiple parallel product accumulation processor 41 work.For example, suppose that a specific digital filter has the coefficient sequence of a length n to process a complete convolution results with the required time of four times of output rating B.Can be configured with one
the digital filter of frequency response (K is constant), initial transient delay week after date provide an output word with an output rating B
.This will be presented in Fig. 3.Because the coefficient sequence n of length equals four times of B, and the result of calculation of a complete convolution, need the n cycle, four product accumulation processor 41 concurrent workings of minimum needs of every B clock cycle produce an output word
.
The work of this product accumulation processor scheme as shown in Figure 3, operate as follows: ten signal element Y (the 1)-Y (10) producing when first modulator provides the input of filter, product accumulation processor 41a multiplies each other the digital signal Y (k) of each corresponding S (j) coefficient and respective element, (be S (1) with Y (1) etc.) and each result is stored in register 46a.When following ten signal element Y (11)-Y (20) produces and be provided to the input of filter, product accumulation processor 41 multiplies each other ensuing ten S (j) coefficient (being S (11)-S (20)) and corresponding element, and each result is stored into again to 46a.Simultaneously, product accumulation processor 46 b multiply each other signal element Y (11)-Y (20) and first ten S (j) coefficient S (1)-S (10), and each result is stored in to register 46 b.The input, product accumulation processor 41 that produces and be provided to filter as signal element Y (21)-Y (30) next ten S (j) coefficient S (21)-S (30) multiplied each other with these elements, and stores each result at register 46a.Meanwhile, product accumulation processor 46 b are by signal element Y (21)-Y (30) and ensuing ten S (j) coefficient (being S (11)-S (20)) and each result is stored in to register 46 b.Meanwhile, tired processor 46 c of product multiply each other signal element Y (21)-Y (30) and S (j) coefficient S (1)-S (10), and by each result store at register 46 c.When signal element Y (31)-Y (40) produces and be provided to the input of filter, product accumulation processor 41a next ten S (j) coefficient S (31)-S (40) multiplies each other with these elements, and each result is stored in to register 46a.
Like this, a complete convolution results just appears in register 46a.Because the S of all 40 coefficient sequence elements (j) (being S (1)-S (40)) has been multiplied by the digital input signals Y (k) (being Y (1)-Y (40)) of 40 elements.Therefore, the numeric word R of a representative simulation input signal V (t) (
) be present in register 46a.In addition, product accumulation processor 41b, 41c and 41d are multiplied by digital input signals element Y (31)-Y (40) and their corresponding filter coefficients, and each result is stored in register 46b-46d separately.
Can see from description above, every B clock cycle, output word R that the element Y (k) between input signal and last filter coefficient S (n) generate (
) completing cumulative multiplication calculating, a register in four registers 46 completes convolutional calculation.In the ensuing cycle, product accumulation processor (41a) restarts to calculate output word
.Corresponding register (46a) is initialized to zero, and the n product accumulation operation of another sequence starts, and this will cause output sequence sample
.Coefficient sequence pointer restarts from j=1 in ring-like mode.
A famous alternative realization of describing in Fig. 3
filter as shown in Figure 4.In Fig. 4, four digital list entries of input
as the copy of input signal Y (k), compared with previous, all postpone B cycle.Delay is produced by Postponement module 53.These four sequences are to be multiplied by coefficient sequence S[j in independent multiplication accumulation processor 50].Therefore generate output word
.Each processor comprises 52, one adders 54 of a multiplier and an accumulator register 56.
Shown in Fig. 3 and 4, the configuration of observation filter device, clearly, when the input that a new input signal V (t) is provided to transducer, is used traditional over-sampling A/D transducer of these filters to experience an of short duration time of delay.For example, at Fig. 1, according to the structure of modulator 20, through the delay (modulator transient delay) in m cycle, digital signal Y (k) starts the input signal V (t) that reflection newly provides.As the function of a state of digital filter 30, at this in a flash accurately, a minimum n cycle, at most after the variable delay in n+b-1 cycle, can obtain a correct analog digital transformation result R (
i).In the reality changing, may be due to internal pipeline level, extra delay p cycle.Therefore, A/D transducer 10 of total transient response time may be different to maximum m+n+B+p-1 cycle from minimum m+n+p cycle.
Also very clear in Fig. 3 and Fig. 4, only having a product accumulation processor 41 or 50 is to use in any given time, produces required output word
.The output of other product accumulation processors abandons because transient delay is coarse, if or output over-sampling feature be not the digital processing for subsequently, be exactly redundancy.Therefore,, when traditional A/D transducer 10 is the application for making discrete monocycle conversion, most variable frequency filter circuit is not just used.
The improved over-sampling A/D converter system that is applicable to doing single cycle A/D conversion has been provided.In a preferred version of the present invention, only having a product accumulation processor is to be presented on digital filtering state, extracts output sequence
.A system controller produces modulators enable signal (EnM) and the digital filter enable signal (EnF) of accurate timing, coordinates to activate the energy power consumption of some circuit element and management system.
Fig. 5 has shown the over-sampling A/D converter system 100 that absorbs principle of the present invention.Over-sampling A/D converter system 100 comprises three basic modules, δ-σ modulator 101, finite impulse response (FIR) (FIR) digital filter 102 and system controller 103.As shown in Figure 5, modulator 101 and digital filter 102 have circuit to enable input.System controller 103 can pass through " effectively " and " non-effective " enable signal " EnM " and " EnF " separately, optionally enables and forbid these circuit." therefore, A/D converter system 100 can be enabled, forbidding, and then reactivate, produce a series of discrete analog(ue)-digital translation at the time point of specifying.
" effectively " used herein and " non-effective " are only used for explanation, do not refer in particular to fixing logic level, and for example, these terms can exchange and not affect work of the present invention.
As shown in Figure 5, the work of A/D transducer 100, may start switching signal " CS " guidance system controller 103 by one and start transfer process.Depend on required working method, this signal may be produced by many different modes.For example, when a digital-to-analogue conversion is desirable (monocycle work), CS signal may be produced by external source.After converting after an automatically circulation before and then (continued operation), CS signal also may produce in inside (in A/D transducer 100 inside), or at the expiration one and then before the adjustable delay period (single cycle operation of repetition) of change-over period after completing, it may be also inner or outside generation.Controller 103 also can use an inside or external timing signal generator clocking
, digital filter clock signal
.
For electrical energy saving, modulator 101 may be the low-power consumption mode (not enabling) that is set at first acquiescence.When CS signal is while being effective, 103 can make system controller enable (activating), and modulator 101 uses modulators enable signal (EnM).This allows modulator 101 to produce pulse density modulated numeral sample Y (k), and it is the input signal of an expression
and reference signal
between the numeral of ratio.At every turn when CS signal is while being effective, system controller 103 is preferably only enabled the time of modulator 101 necessity, the effective sample Y (k) that produces digital filter 102 desired minimum numbers, generates a digital conversion results (i.e. a numeric word).The sample of this quantity is typically expressed as n continuous effective sample Y (k).The time that modulator 101 is enabled can be expressed as the value of m+n, and wherein n is the input sample of requirement, and m is the transient delay of modulator 101, and depends on the customized configuration of modulator 101.After past m+n time period, the analog input sample finally needing should be processed by modulated device 101.Now, once it has completed treatment of simulated input signal, system controller 103 modulators enable signals (EnM) become non-effective, forbid modulator 101.This allows modulator 101 just not enable after the processed correct time of last analog input signal, thereby has saved power consumption.
For some specific modulator structures, modulator 101 time of enabling time expand is good, as simplified the sequential requirement of whole system.In addition, extending activationary time may provide extra output sample Y (k), and this may be useful for some function, as built in self testing.
As shown in Figure 5, numeral sample Y (k) is further processed by digital filter 102.Because numeral sample Y (k) but by one about analog input signal
factor m time delay, when modulator 101 is while enabling at first, the Y (k) of effective sample there will not be at input digital filter 102.Therefore, there is no need to make digital filter 102 to synchronize with modulator 101.System controller 103 preferably waits until that first effective sample sequence Y (k) enables it before appearing at input digital filter 102.Only have in the time that it produces the numeral sample Y (k) needing and just enable digital filter 102, this has reduced the overall power of A/D transducer 100 in transfer process.
System controller 103 can be determined reasonable time, from enabling the moment at first of modulator 101, by the known transient delay of countdown time m, enables digital filter 102.Once the time expires, first effective sample sequence Y (k) should appear at the input of digital filter 102.System controller 103 may make the filtering of digital filter 102 allow signal (EnF) to enable, thereby the moment that makes digital filter 102 appear at its input at first effective numeral sample Y (k) is activated.
Be similar to the work of modulator 101, digital filter 102 is activated in order to only have the minimum time to produce the digital conversion results of needs.This time can be expressed as n+p, and n is the quantity of the input sample Y (k) that effectively processed by digital filter 102, and p is the channel delay of digital filter 102, and this depends on the concrete configuration of filter.After n+p time warp, system controller 103 preferably filter permission signal (EnF) is non-effective, therefore processes input sample Y (k) when it completes, and forbids filter 102.When conversion is not performed, by forbidden digit filter 102, reduce the power consumption of A/D transducer 100.
System controller 103 can be determined reasonable time, by forbidding moment countdown p time of delay from modulator 101.Once the time expires, last effective sample sequence Y (k) should be produced by digital filter 102.This makes digital filter 102 disabled after the correct time that effectively numeral sample Y (k) has been filtered.
For some specific modulator structures, modulator 102 time of enabling time expand is good, as simplified the sequential requirement of whole system.In addition, extending filter 102 activationary times may provide extra output sample Y (k), and this may be useful for some function, as built in self testing.
A/D converter system 100 work that are presented at Fig. 5 are as follows.At first, A/D transducer 100 is being changed initial signal CS into " energy-conservation " pattern that is operated in an acquiescence under non-effective.Under this pattern, it is non-effective that system controller 103 may allow signal (EnF) and modulators enable signal (EnM) by two filters, and two modulators 101 and digital filter 102 are placed in to low power consumpting state (not enabling).When CS signal is while being effective, system controller 103 may be enabled modulator 101, produces an analog input signal
pulse density modulated sequence Y (k).Modulator 101 can be enabled a time that is more than or equal to m+n, obtains n effective sample Y (k), then can forbid immediately by controller 103.Digital filter 102 had better keep not enabling, until first effective sample Y (k) appears at its input.Become a digital output character in order to weaken zoop and to extract numeral sample Y (k)
, system controller 103 may make digital filter 103 enable the time that is more than or equal to n+p.Afterwards, system controller 103 forbidden digit filter 102 immediately.In this, A/D transducer 100 has returned to the protecting energy pattern of acquiescence, and may remain there, until conversion initial signal CS is effective again.
By such work, A/D converter system 100 has reduced it in two translative mode (when CS signal is effectively and in A/D transfer process) with at the total power consumption of idle pulley (, when CS signal is non-effective, not having A/D to change in the time carrying out).For example, in translative mode, system controller 103, with the time of minimum needs, enables modulator 101 and digital filter 102, and carries out task separately, and they all forbid other times.This make A/D transducer 100 use necessary, minimum power consumption produces the result of a conversion.Equally, under idle pulley, system controller 103 can forbid modulator 101 and digital filter 102 minimizes the power consumption of A/D converter system 100 in inactive period.
In Fig. 5, if conversion initial signal CS is effectively, be synchronized with new input signal
Application (for example,, if conversion initial signal CS is while being effective state, the transient response time that input multiplexer has changed A/D transducer 100 can be defined as m+n+p clock cycle.This is that wherein digital filter 102 has the possible minimum transient delay of A/D transducer 100 of the length n of a coefficient sequence.If conversion initial signal CS is effectively, a synchronous new input signal application
(for example, if a period of time after the state variation of input multiplexer: conversion initial signal CS is effective, but before A/D transducer completes a change-over period), A/D transducer 100 transient response times can be defined as 2* n+m+p-1 clock cycle.This is that great changes have occurred input signal during this time because conversion initial signal CS may still remain valid at the end of change-over period, and A/D converter 100 can be carried out follow-up conversion and generate the result of the new input signal of correct reflection like this.2 * n+m+p-1 value representatives have the maximum instantaneous of the digital filter 102 of the length n of a coefficient sequence to postpone to A/D transducer 100.Therefore, A/D transducer 100 provides convenience to input multiplexed definition good settling time.
One uses suitable δ-σ modulator of the present invention as shown in Figure 6.In Fig. 6, show the 3rd δ-σ modulator 200, it has three utmost points stable in starting point and feedforward.Modulator 200 comprises summing junction 201, integrator 202-204, adder 205, comparator 206, clock generator 207 and initialization controller 208.In the time of work, modulator 200 impulse densities regulate analog input signal
produce numeral sample Y (k).For example, when modulation is desirable (, when conversion initial signal CS is effectively changed with the state of an input multiplexer), modulators enable signal (
) be effective and an analog input signal
summing junction 201 in input is provided.Effective modulators enable signal (
) under response, clock generator 207 can use modulator clock signal (
) carry out clocking
with suitable relative phase relation, so that some some work of modulator 200 (summing up node 201, integrator 202-204, output adder 205, and comparator 206) is suitably to coordinate.
Once the digital output sample Y (k) of requirement produces, modulator 200 will be by non-effective modulators enable signal (EnM) forbidding.Disabled when modulator 200, conventionally use 206 to one groups of predefined initial condition of initialization controller 208 " initialization " or " replacement " integrator 202-204 and comparator, to guarantee the stable of modulator 200, this is desirable.Such initialization connects each of three integrators 202-204 in whole integrating condenser (not showing) and completes for Y=0 state by adjusting comparator 206 by opening or closing some switch (not show).
Although the integrator 202-204 of initial condition and comparator 206 only have very little effect to the precision of the transformation result producing at A/ D converter system 100 (Fig. 5), due to the unpredictability of initial condition, it is difficult to guarantee stable modulator conventionally.The method of common practicality is to carry out measuring stability by the emulation initial condition widely in all possible situation.Generally, this has represented an intersection all possible input signal values of product and all possible modulator initial condition.By the initial condition of modulator 200 (being integrator 202-204 and comparator 206) explication, must be simulated greatly reduce with the quantity of the many possible situation that guarantees overall modulator stable, thereby reduce to greatest extent the time of designing modulator 200 necessity.
A/D the converter system 100 that is presented at Fig. 5 may allow modulator 101 before the beginning of a new change-over period, uses modulators enable signal (EnM) initialization.For example, modulators enable signal (EnM) 101 is normally become non-effective by system controller 103 controls, when having after n the effective sample Y of generation (k), and forbidding modulator 101.In portion of time, modulator 101 is forbidden, and digital filter 102 may remain processes numeral sample Y (k), completes the change-over period.Non-effective modulators enable signal (EnM) may cause the part or all of integrating condenser (not showing) at modulator 101 to be initialised, start (when modulators enable signal (EnM) is again effective) when the ensuing change-over period, modulator 101 is just initialised.
As an extra power-saving measures, when modulator 101 is forbidden, the some or all of circuit that are included in modulator 101 may be closed, when these circuit reopen (ought enable modulation signal (EnM) again effective), the very important stabilization time that modulator 101 is required, can calculate by modulator transient delay factor m.This method provides a kind of electric power management mechanism of point-device minimal power consumption.
A product accumulation processor that is applicable to digital frequency conversion filter of the present invention is presented at Fig. 7.
A/D the converter system that is different from prior art adopts the digital filter of multiple product accumulation processors, and A/D converter system of the present invention preferably only comprises a product accumulation processor in its digital filtering stage.This point by with Fig. 3 or Fig. 4 in the contrast of prior art scheme product accumulation processor visible, single product accumulation processor is presented at Fig. 7.
The background parts of this application just as discussed, traditional over-sampling A/D converter system produces multiple transformation results from a given input signal configuration.Analog input signal is applied to these A/D transducers of input in the sufficiently long time, so that they overcome the transient delay cycle by accumulating enough convolution results by product accumulation processor, than conventionally only having the tired processor of a product faster under data transfer rate, start production figures output signal.Such A/D transducer depends on hypothesis: 1) this is desirable, from a specific input signal to obtain multiple order transformation results; 2) they will be connected the input signal of sufficiently long a period of time to one, accumulate with one faster data rate start the input sample of production figures transformation result.
But these hypothesis are always incorrect.In fact, in many data acquisitions application, such as test and measurement and Industry Control need to obtain a series of monocycle transformation result from many incoherent sources conventionally.For example, the input of A/D transducer is arranged on a computer can be connected to a multiplexer, and scanning is positioned at the operating voltage of the multiple actuators on production line.
Computer may be monitored execution work voltage and A/D transducer, to guarantee that they are operated in the voltage range of an appointment.Still be connected to a specific input channel at this and the similar multiplexer of applying, only have the sufficiently long time to allow A/D transducer produce a transformation result.After the result of conversion obtains, A/D transducer multiplexer that can reset, changes passage, so that next input signal can be converted.
For monocycle transformation applications, as mentioned above, A/D converter only needs a multiplication accumulation processor in its digital filtering level.This is because only have a complete convolution results to need to produce for each input signal.After result produces, a new input signal is applied to A/ D transducer, needs the accent of convolution process to start.When A/D transducer resets, any previous change-over period is stored in the convolution results of other product accumulation processors because inaccuracy or loss.Therefore, when traditional A/D transducer comprise multiple for the product accumulation processors in single cycle application, except a single cycle product accumulation processor, other just cut little ice.
Compared with traditional A/D transducer, the invention provides a kind of A/D transducer and digital filter, use the arrangement of a product accumulation processor to be applicable to effective single cycle A/D conversion.Such configuration has greatly been simplified the realization of digital filter and has been reduced power consumption.Suitable (Fig. 5) of the present invention digital filter 102 uses the example of multiplication accumulation processor shown in Figure 7.
In Fig. 7, multiplication accumulation processor 300 comprises input multiplier 310, adder 311, register 312 and coefficient maker 313.At work, multiplication accumulation processor 300 zoop of decaying, and extract numeral sample Y (k) be supplied to by modulator 101 (Fig. 1) with produce digital output character R (
i).When filtering is to expect filter, enable signal (
) effectively, described output signal indication coefficient generator 313 is to provide the coefficient sequence s (j) of described the first coefficient s (1) to an input of multiplier 310, be provided to the accurate moment of another multiplier 310 input ends at first effective modulator output sample y (1), described filter enable signal (
) sufficiently long time of remaining valid for all n filter coefficient s (j), j=1,2...n be multiplied by the corresponding modulator output sample Y (k) being produced by coefficient generator 313, k=1,2, ... the result of n and described multiplication is accumulated in register 312 by adder 311, take produce complete convolution results (as digital output character R (
i)).
Once by register 312 export digital output character R (
i), multiplication accumulation processor 300 will make described non-effective filter enable signal (
) forbidding.When disabled, some or all circuit of digital filter 102 (Fig. 5) are being placed in the energy-saving mode of the additional electricity-saving mechanism of conduct, with minimise power consumption, when filter enable signal (
) be non-effective, system controller 103 (Fig. 5) can interrupt clock signal
.In addition, when filter enable signal (
) becoming effective status from non-effective state, register 312 (Fig. 7) can be deleted the convolution results that any previous conversion may exist, and carrys out initialization.
Although preferred embodiment of the present invention discloses, various circuit are connected to other circuit, it will be apparent to one skilled in the art that and can not need with such connection, adjunct circuit can be the connecting circuit of interconnection, does not depart from spirit of the present invention.Those skilled in the art also will appreciate that, the present invention can be different from above-mentioned example, and described example only for illustrative purposes, rather than restrictive, and the present invention is only defined by the claims scope.
Claims (4)
1. a single circulation over sampling digital to analog converter, it is characterized in that: an over-sampling number mould converter circuit comprises: δ-σ modulator circuit, it receives analog input signal and analog input signal is converted to the numeral sample of modulating, δ-σ modulator circuit has an input and an output, a filter circuit is coupled to the output of described modulator circuit, receive the numeral sample of modulating from described modulator circuit, and the numeral sample that conversion was modulated becomes a digital output character; A system controller circuit, it is coupled to modulator circuit and filter circuit, optionally enables and forbid modulator circuit and filter circuit.
2. a kind of single circulation over sampling digital to analog converter according to claim 1, it is characterized in that: system controller circuit is configured to receive conversion initial signal, like this, when conversion initial signal is while being effective, system controller circuit instruction simulation-quantizer circuit converts analog input signal to digital output character; When digital output character produces, system controller circuit is configured to forbid described analogue-to-digital converters circuit; Modulator circuit is configured to receive a modulators enable signal from system controller circuit; When modulators enable signal is while being effective, enable modulator circuit; When modulators enable signal is while being non-effective, forbidding modulator circuit; When modulators enable signal is while being effective, modulator circuit is enabled; It is effectively one necessary period that system controller circuit keeps modulators enable signal, by desired digital filter circuit generating digital output word, allows modulator circuit produce the numeral sample of some; Filter circuit is configured to receiving filter enable signal from described system controller circuit; When filter circuit enable signal is while being effective, enable filter circuit; When filter circuit enable signal is while being non-effective, forbidding filter circuit; When filter circuit enable signal is while being effective, filter circuit is enabled; It is effectively one necessary period that system controller circuit keeps filter circuit enable signal, by desired digital filter circuit generating digital output word, allows filter circuit filter digital output sample; Wherein modulator circuit is three rank δ-σ modulators; Wherein modulator circuit further comprises clock generator circuit; Wherein modulator circuit further comprises an initialization controller; Wherein modulator circuit further comprises integrating circuit, the predefined initial condition of integrating circuit group of can optionally resetting of initialization controller wherein; Wherein modulator further comprises comparator circuit, the predefined initial condition of integrating circuit group of can optionally resetting of initialization controller wherein; Filter circuit is a finite impulse response filter; Digital filter circuit further comprises a coefficient generator; Coefficient generator configuration is used for from system controller circuit receiving filter enable signal; When analog input signal synchronous applications is to analogue-to-digital converters circuit, there is the settling time of a m+n+p; Synchronous when analog input signal, apply an analogue-to-digital converters circuit, there is the settling time of 2 * n+m+p-1; Digital filter circuit further comprises a product accumulation processor.
3. a kind of single circulation over sampling digital to analog converter according to claim 1, is characterized in that: a method that is transformed into digital signal from analog signal comprises: modulated analog signal creates modulation digital sample; Filter modulation digital sample by digital filter, create a digital output character; And control signal is provided, optionally enable and forbid the work of the circuit of being responsible for modulation and filtering; Wherein provide this step further to comprise: to make modulator open a period of time, by desired digital filter circuit generating digital output word, allow modulator circuit produce the numeral sample of some; After the digital phantom of some produces, forbid immediately modulator; After the first numeral sample is provided, enable digital filter; Produce after digital output character forbidden digit filter immediately; The feature of described modulation is to use δ-σ modulator; The feature of described filtration is to use a finite impulse response filter; Described analog-to-digital feature is to be synchronously converted into digital output character when analog signal, has the settling time of a m+n+p; Described analog-to-digital feature is in the time that analog signal is synchronously converted into digital output character, has the settling time of 2 * n+m+p-1.
4. a kind of single circulation over sampling digital to analog converter according to claim 1, is characterized in that: a method of reaching single cycle analog-digital conversion comprises: indication modulator circuit regulates analog input signal, produces modulation digital sample; Control signal is provided, optionally enables and forbid modulator circuit, optionally initialization modulator circuit; Method further comprises: designation number filter circuit filters modulation digital sample, produces a digital output character; Control signal is provided, optionally enables and forbid indication filter circuit and initialization filter circuit optionally; Wherein provide this step further to comprise: to enable the modulator one necessary period of indication of modulator circuit, by desired digital filter circuit generating digital output word, allow modulator circuit produce the numeral sample of some; After the digital phantom of some produces, the indication of forbidding modulation immediately step; After the digital phantom of some produces, controller circuitry described in initialization; After the numeral sample of the first modulation is provided, enable digital filter indication; After digital output character produces, forbid immediately described filter indication; After digital output character produces, digital filter circuit described in initialization; Wherein initialization step further comprises: integrating circuit is set to one group of predefined initial condition; After digital output character produces, digital filter circuit described in initialization; Wherein the feature of modulator indication step is to use δ-σ modulator; The feature of its median filter indication step is to use a finite impulse response filter.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450199A (en) * | 2015-11-19 | 2016-03-30 | 厦门大学 | Cascading integration comb filter with quick building time, and design method for cascading integration comb filter |
| CN111083941A (en) * | 2018-08-21 | 2020-04-28 | 康姆索利德有限责任公司 | Analog-to-digital converter |
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| CN1115922A (en) * | 1993-10-25 | 1996-01-31 | 摩托罗拉公司 | Bandpass sigma-delta analog-to-digital converter (ADC), method therefor, and receiver using same |
| US6208279B1 (en) * | 1998-08-17 | 2001-03-27 | Linear Technology Dorporation | Single-cycle oversampling analog-to-digital converter |
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- 2013-11-26 CN CN201310606857.3A patent/CN103795412A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1115922A (en) * | 1993-10-25 | 1996-01-31 | 摩托罗拉公司 | Bandpass sigma-delta analog-to-digital converter (ADC), method therefor, and receiver using same |
| US6208279B1 (en) * | 1998-08-17 | 2001-03-27 | Linear Technology Dorporation | Single-cycle oversampling analog-to-digital converter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450199A (en) * | 2015-11-19 | 2016-03-30 | 厦门大学 | Cascading integration comb filter with quick building time, and design method for cascading integration comb filter |
| CN111083941A (en) * | 2018-08-21 | 2020-04-28 | 康姆索利德有限责任公司 | Analog-to-digital converter |
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