CN105449996B - Minimum degaussing duration control method and device - Google Patents
Minimum degaussing duration control method and device Download PDFInfo
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- CN105449996B CN105449996B CN201511027974.XA CN201511027974A CN105449996B CN 105449996 B CN105449996 B CN 105449996B CN 201511027974 A CN201511027974 A CN 201511027974A CN 105449996 B CN105449996 B CN 105449996B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The present invention relates to a kind of minimum degaussing duration control method, the minimum degaussing duration control method comprises the following steps：Judge output voltage sampling finish time inductive current whether zero passage or contrast inductance degaussing time and output voltage sampling time；It is not more than the output voltage sampling time when each output voltage sampling finish time inductive current zero passage or inductance degaussing time, output voltage sampling is invalid, increases minimum ON time and is sampled for next cycle output voltage；When each output voltage sampling finish time inductive current, zero passage or inductance degaussing time are not more than the output voltage sampling time, output voltage sampling is effective, compare the minimum ON time limiting value of minimum ON time and internal system setting, if minimum ON time is more than the minimum ON time limiting value that internal system is set, reduces minimum ON time and sampled for next cycle output voltage.
Description
Technical field
The invention belongs to power technique fields, and in particular to a kind of minimum degaussing duration control method and device.
Background technology
At present, because the needs of energy-conserving and environment-protective, many application scenarios require more and more stricter to the stand-by power consumption of system.
Such as be widely used in various household electrical appliance and be commonly used for standby primary side feedback formula AC-DC power supplys, in another example
A kind of floating non-isolated DC-DC power source of ground structure shown in Fig. 1.Both power supplys are all in power tube shut-off instance sample output electricity
Pressure.Fig. 2 is the timing waveform of the output voltage sampling of the non-isolated DC-DC power sources of Fig. 1.
It is the output voltage sample waveform figure under intermediate load condition shown in left figure in Fig. 2, inductance degaussing time Tdemag
More than output voltage sampling time length Tsam, output voltage can be with efficiently sampling；It is light load or unloaded shown in right figure in Fig. 2
Under the conditions of output voltage sample waveform figure, because power tube ON time is very short under underloading, inductance peak point current very little, cause electricity
The sense degaussing time is too small, and inductance degaussing time Tdemag is less than output voltage sampling time length Tsam, exports in the case
Voltage sample mistake (i.e. the voltage of sampling period and be not equal to output voltage).Now, a kind of simple solution is in electricity
Source output terminal connects fictitious load, to increase the peak point current of inductance or transformer during power tube turns on so as to increase in the TOFF phases
Between the degaussing time come ensure output voltage sampling stability.When change range of input voltage is wider, this method may
Significant power attenuation can be brought, causes the standby requirement that can not meet low-power consumption.
The content of the invention
, can be big in input voltage or output voltage it is an object of the invention to provide a kind of minimum degaussing duration control method
During range, using the power tube ON time of minimum, i.e., realize have to output voltage under system power dissipation minimal condition
Effect sampling.
What the present invention was realized in：A kind of minimum degaussing duration control method, the minimum degaussing duration control method
Comprise the following steps：
Power tube is disconnected, and output voltage is sampled；
Judge output voltage sampling finish time inductive current whether zero passage or contrast inductance degaussing time and output voltage
Sampling time；
Adopted when each output voltage sampling finish time inductive current zero passage or inductance degaussing time no more than output voltage
The sample time, output voltage sampling is invalid, increases minimum ON time and is sampled for next cycle output voltage；
When each output voltage sampling finish time inductive current, zero passage or inductance degaussing time do not adopt more than output voltage
The sample time, output voltage sampling is effective, the minimum ON time limiting value of more minimum ON time and internal system setting, such as
Fruit minimum ON time is more than the minimum ON time limiting value that internal system is set, and reduces minimum ON time and for next
Cycle output voltage samples, if minimum ON time is less than or equal to the minimum ON time limiting value that internal system is set,
Then minimum ON time is changed to minimum ON time limiting value.
A kind of minimum degaussing time-controlling arrangement, the minimum degaussing time-controlling arrangement include：Inductive current zero passage is examined
Slowdown monitoring circuit, trigger and minimum ON time adjustment circuit, the inductive current zero cross detection circuit are used to judge inductive current
Whether nought state was in.
Further,
The minimum degaussing time-controlling arrangement working method is that the inductive current zero cross detection circuit output first is high
Level or low level signal input the trigger, and output voltage sampled signal inputs the trigger and is used as the trigger
Clock signal, the trigger gathers first high level or low level signal in output voltage sampled signal finish time
And high level or low level FLAG signals are exported to represent the validity of output voltage sampling, the minimum ON time adjustment
Circuit adjusts minimum ON time, the minimum ON time input PWM generative circuits according to the FLAG signals.
Preferably, the inductive current zero cross detection circuit can by comparator detect inductive current whether zero passage.
Preferably, the inductive current zero cross detection circuit is by measuring voltage or detection on output voltage sampling resistor
Inductive current detection resistance RCS voltage with judge inductive current whether zero passage.
Preferably, the trigger is d type flip flop or JK flip-flop.
Preferably, the minimum ON time adjustment circuit is TON_MIN control circuits or IPK_MIN control circuits.
Preferably, the minimum degaussing time adjusting circuit course of work is：
When FLAG is high level, then switch S2 turns on one section by the Oneshot pulse controlled times, by pulling down constant-current source
I2 discharges electric capacity C1, and VC voltages reduce；When DRV signal is changed into 1 from 0, constant-current source I3 charges to electric capacity C2, when the electricity on C2
Comparator COMP2 outputs high level when pressure exceeds VC voltages, if now voltage also exceeds VREF simultaneously on C2, power tube is most
Small ON time TON_MIN exports high level, and TON_MIN output high level represents that DRV minimum ON times terminate；
When FLAG is low level, then switch S1 turns on one section by the Oneshot pulse controlled times, by pulling up constant-current source
I1 charges to electric capacity C1, the rise of VC voltages.
Compared with prior art, beneficial effects of the present invention：
(1) a kind of minimum degaussing duration control method of the present invention, can be in input voltage or output voltage wide variation
When, using the power tube ON time of minimum, that is, realize under system power dissipation minimal condition to the efficiently sampling of output voltage；
(2) a kind of minimum degaussing duration control method of the present invention, passes through the control of minimum degaussing time so that be when unloaded
The minimum ON time length of system optimizes the stand-by power consumption of system near output voltage sampled signal time span point,
With high efficiency；
(3) a kind of minimum degaussing time-controlling arrangement of the present invention, is a kind of adaptive controller, greatly simplify periphery
The complexity used is designed, application is very convenient.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, it will use below required in embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the present invention, for this area
For those of ordinary skill, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the non-isolated DC-DC power source circuit diagram of floating ground structure of background technology；
Fig. 2 is the output voltage sample waveform figure of Fig. 1 in background technology；
Fig. 3 is the minimum degaussing duration control method flow chart of the present invention；
Fig. 4 is the minimum degaussing time-controlling arrangement flow chart of the present invention；
Fig. 5 is the minimum degaussing time-controlling arrangement flow chart of the embodiment of the present invention one；
Fig. 6 is the minimum degaussing time-controlling arrangement flow chart of the embodiment of the present invention two；
Fig. 7 is the minimum ON time adjustment circuit figure of the embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein only to explain the present invention, not
For limiting the present invention.
It should be noted that when element is referred to as " being fixed on " or " being arranged at " another element, it can be directly another
On one element or it may be simultaneously present centering elements.When an element is known as " being connected to " another element, it can
To be directly to another element or may be simultaneously present centering elements.
Only it is relative concept each other it should also be noted that, the orientation term such as left and right, upper and lower in the embodiment of the present invention
Or using the normal operating condition of product as reference, and should not be regarded as restrictive.
As shown in figure 3, a kind of minimum degaussing duration control method provided in an embodiment of the present invention, the minimum degaussing time
Control method includes：
Step 101, power tube is disconnected, and output voltage is sampled；
Step 102, judge output voltage sampling finish time inductive current whether zero passage or contrast the inductance degaussing time with
The output voltage sampling time；
Step 103, when each output voltage samples finish time inductive current zero passage or inductance degaussing time no more than defeated
Go out the voltage sample time, output voltage sampling is invalid, step 104, increases minimum ON time and for output of next cycle electricity
Pressure sampling；
Step 105, when each output voltage sampling finish time inductive current not zero passage or inductance degaussing time be more than it is defeated
Going out the voltage sample time, output voltage sampling is effective, step 106, the minimum of more minimum ON time and internal system setting
ON time limiting value, step 107, if minimum ON time is more than the minimum ON time limiting value that internal system is set,
Reduce minimum ON time and sampled for next cycle output voltage, step 108, if minimum ON time is less than or equal to
Internal system set minimum ON time limiting value, then minimum ON time be changed to minimum ON time limiting value.
A kind of minimum degaussing duration control method of the present invention, can in input voltage or output voltage wide variation,
Using the ON time of minimum, i.e., under system power dissipation minimal condition, realize the efficiently sampling to output voltage.
Such as Fig. 4, a kind of minimum degaussing time-controlling arrangement, the minimum degaussing time-controlling arrangement includes：Inductive current
Zero cross detection circuit 201, trigger 204 and minimum ON time adjustment circuit 206, the inductive current zero cross detection circuit
201 are used to judge whether inductive current was in nought state.
As shown in figure 4, the minimum degaussing time-controlling arrangement working method is the inductive current zero cross detection circuit
201 the first high level of output or low level signal 202 input the trigger 204, and output voltage sampled signal 203 inputs described
Trigger 204 simultaneously terminates as the clock signal of the trigger 204, the trigger 204 in output voltage sampled signal 203
Moment gathers first high level or low level signal 202 and exports high level or low level FLAG signals 205 to represent
The validity of output voltage sampling, the minimum ON time adjustment circuit 206 adjust minimum according to the FLAG signals 205 and led
Logical time 207, the minimum ON time 207 input PWM generative circuits 208.
First high level or low level signal 202 are representing whether inductive current had been in nought state.
Minimum ON time adjustment circuit 206 according to FLAG signals 205 come the minimum ON time of control system, if such as
FLAG=1 then reduces the minimum ON time of system, increases the minimum ON time of system if FLAG=0.
As shown in Figures 4 to 6, the inductive current zero cross detection circuit 201 can detect inductive current by comparator
Whether zero passage.
As shown in Figures 4 to 6, the inductive current zero cross detection circuit 201 is by measuring on output voltage sampling resistor
Voltage or detection inductive current detection resistance RCS voltage with judge inductive current whether zero passage.
As shown in Figures 4 to 6, the trigger 204 is d type flip flop or JK flip-flop.
As shown in Figures 4 to 6, the minimum ON time adjustment circuit 206 is TON_MIN (during the minimum conducting of system
Between) control circuit 209 or IPK_MIN (the minimum peak electric current of system) control circuit 210.
Embodiment one, the minimum ON time adjustment circuit 206 are TON_MIN control circuits 209, and TON_MIN is controlled
The output signal of circuit 209 is the minimum ON time of system to PWM generative circuits 208.Under a normal load, the conducting of system
Time determines that ON time is typically greater than TON_MIN by the EA outputs inside PWM generative circuits 208, and now TON_MIN believes
Number do not influence the work of system；And when system enters unloaded or pole light-load mode, the conducting required by PWM generative circuits 208
Time possible very little, now by the TON_MIN control circuits 209 set by minimum degaussing time-controlling arrangement come decision systems
ON time.The minimum ON time adjustment circuit 206 of minimum degaussing time-controlling arrangement, is led by the minimum of control system
The logical time carrys out the minimum degaussing time of indirect control system, by the inductance electricity for monitoring output voltage sampled signal finish time
Stream whether zero passage come judge the degaussing time of system whether be more than output voltage sampled signal time span.Unloaded or extremely light
Under loading condition, minimum degaussing time-controlling arrangement works, the result is that under limit during the degaussing of inductance or transformer
Between be approximately equal to the time span of output voltage sampled signal.
Embodiment two, the minimum ON time adjustment circuit 206 are IPK_MIN control circuits 210.Such as BUCK types
DC-DC, TON_MIN and the relation of degaussing time are as follows：
Inductance peak point current is corresponding to TON_MINIn inductive current discharge regime, degaussing
Time and IPK relation isTwo equatioies of joint obtainSo
By controlling TON_MIN to control the degaussing time.
As shown in fig. 7, the minimum ON time adjustment circuit course of work is：
When FLAG is high level, then switch S2 turns on one section by the Oneshot pulse controlled times, by pulling down constant-current source
I2 discharges electric capacity C1, and VC voltages reduce；When DRV signal is changed into 1 from 0, constant-current source I3 charges to electric capacity C2, when the electricity on C2
Comparator COMP2 outputs high level when pressure exceeds VC voltages, if now voltage also exceeds VREF simultaneously on C2, power tube is most
Small ON time TON_MIN exports high level, and TON_MIN output high level represents that DRV minimum ON times terminate；
When FLAG is low level, then switch S1 turns on one section by the Oneshot pulse controlled times, by pulling up constant-current source
I1 charges to electric capacity C1, the rise of VC voltages.
Obviously, VC voltages reduce, then TON_MIN reduces；VC voltages raise, then TON_MIN increases.It is realized in FLAG
=1, TON_MIN reduce, in FLAG=0, the function of TON_MIN increases.
Wherein comparator COMP1 and reference voltage VREF1 effect is for setting TON_MIN_LMT, limiting system
The TON_MIN least limit time.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
Any modification, equivalent substitution or improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (6)
1. a kind of minimum degaussing duration control method, it is characterised in that the minimum degaussing duration control method includes following step
Suddenly:
Power tube is disconnected, and output voltage is sampled；
Judge whether zero passage or contrast inductance degaussing time and output voltage sample output voltage sampling finish time inductive current
Time；
When each output voltage, which samples finish time inductive current zero passage or inductance degaussing time, to be sampled no more than output voltage
Between, output voltage sampling is invalid, increases minimum ON time and is sampled for next cycle output voltage；
When zero passage or inductance degaussing time are not more than output voltage sampling to each output voltage sampling finish time inductive current
Between, output voltage sampling is effective, the minimum ON time limiting value of more minimum ON time and internal system setting, if most
Small ON time is more than the minimum ON time limiting value that internal system is set, and reduces minimum ON time and is used for next cycle
Output voltage samples, if minimum ON time is less than or equal to the minimum ON time limiting value that internal system is set, most
Small ON time is changed to minimum ON time limiting value.
2. a kind of minimum degaussing time-controlling arrangement, it is characterised in that the minimum degaussing time-controlling arrangement includes：Inductance electricity
Zero cross detection circuit, trigger and minimum ON time adjustment circuit are flowed, the inductive current zero cross detection circuit is used to judge
Whether inductive current was in nought state；The minimum degaussing time-controlling arrangement working method is the inductive current zero passage
Detect the high level of circuit output first or low level signal inputs the trigger, output voltage sampled signal inputs the triggering
Device simultaneously gathers described first as the clock signal of the trigger, the trigger in output voltage sampled signal finish time
High level or low level signal simultaneously export high level or low level FLAG signals to represent the validity of output voltage sampling, institute
State minimum ON time adjustment circuit and minimum ON time, the minimum ON time input are adjusted according to the FLAG signals
PWM generative circuits.
3. minimum degaussing time-controlling arrangement according to claim 2, it is characterised in that the inductive current zero passage detection
Circuit can by comparator detect inductive current whether zero passage.
4. minimum degaussing time-controlling arrangement according to claim 3, it is characterised in that the inductive current zero passage detection
Circuit judges inductance by measuring the voltage of voltage on output voltage sampling resistor or detection inductive current detection resistance RCS
Electric current whether zero passage.
5. minimum degaussing time-controlling arrangement according to claim 2, it is characterised in that the trigger is d type flip flop
Or JK flip-flop.
6. minimum degaussing time-controlling arrangement according to claim 2, it is characterised in that the minimum ON time adjustment
Circuit is the minimum peak current control circuit of minimum the ON time control circuit or system of system.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511027974.XA CN105449996B (en) | 2015-12-31 | 2015-12-31 | Minimum degaussing duration control method and device |
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| CN201511027974.XA CN105449996B (en) | 2015-12-31 | 2015-12-31 | Minimum degaussing duration control method and device |
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| CN105449996B true CN105449996B (en) | 2018-04-06 |
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| CN113507213B (en) * | 2021-08-23 | 2023-07-07 | 苏州中科华矽半导体科技有限公司 | Current mode control method of boost power supply chip for wide input application |
| CN113992019B (en) * | 2021-10-11 | 2023-09-08 | 茂睿芯（深圳）科技有限公司 | Control method and device of flyback converter and electronic equipment |
| CN114825892B (en) * | 2022-05-27 | 2023-08-11 | 杭州晶丰明源半导体有限公司 | Minimum on-time circuit, controller, circuitry and current detection method |
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