CN105449996A - Minimum demagnetization time control method and device - Google Patents
Minimum demagnetization time control method and device Download PDFInfo
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- CN105449996A CN105449996A CN201511027974.XA CN201511027974A CN105449996A CN 105449996 A CN105449996 A CN 105449996A CN 201511027974 A CN201511027974 A CN 201511027974A CN 105449996 A CN105449996 A CN 105449996A
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- degaussing
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000005347 demagnetization Effects 0.000 title abstract 6
- 238000005070 sampling Methods 0.000 claims abstract description 44
- 230000001939 inductive effect Effects 0.000 claims description 39
- 238000001514 detection method Methods 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 description 3
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006757 chemical reactions by type Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The invention relates to a minimum demagnetization time control method and device. The minimum demagnetization time control method comprises the following steps of judging whether inductor current passes through zero at an output voltage sampling finish moment or not or comparing the demagnetization time of an inductor with output voltage sampling time; allowing output voltage sampling to be invalid and increasing minimum conduction time for output voltage sampling at a next period when the inductor current at each output voltage sampling finish moment passes through zero or the demagnetization time of the inductor is not more than the output voltage sampling time; allowing the output voltage to be valid when the inductor current at each output voltage sampling finish moment does not pass through zero or the demagnetization time of the inductor is greater than the output voltage sampling time; and comparing the minimum conduction time with the minimum conduction time limitation value set in the system, and reducing the minimum conduction time for output voltage sampling at the next period if the minimum conduction time is greater than the minimum conduction time limitation value set in the system.
Description
Technical field
The invention belongs to power technique fields, be specifically related to a kind of minimum degaussing duration control method and device.
Background technology
At present, due to the needs of energy-conserving and environment-protective, a lot of application scenario requires more and more stricter to the stand-by power consumption of system.
Such as to be widely used in various household electrical appliance and to be commonly used for standby former limit reaction type AC-DC power supply, again a kind of floating ground structure non-isolated DC-DC power source shown in such as Fig. 1.These two kinds of power supplys are all turn off instance sample output voltage at power tube.Fig. 2 is the timing waveform of the output voltage sampling of Fig. 1 non-isolated DC-DC power source.
Be output voltage sample waveform figure under intermediate load condition shown in left figure in Fig. 2, inductance degaussing time Tdemag is greater than output voltage sampling time length Tsam, and output voltage can efficiently sampling; Output voltage sample waveform figure under underload or idle condition shown in right figure in Fig. 2, because under underloading, power tube ON time is very short, inductance peak current is very little, cause the inductance degaussing time too small, inductance degaussing time Tdemag is less than output voltage sampling time length Tsam, in the case output voltage sample error (namely sampling period voltage and be not equal to output voltage).Now, a kind of simple solution connects dummy load at power output end, with increase inductance or transformer at the peak current of power tube conduction period thus the degaussing time increased during TOFF ensure the stability that output voltage is sampled.When change range of input voltage is wider, this method may bring significant power loss, causes the standby requirement that can not meet low-power consumption.
Summary of the invention
The object of this invention is to provide a kind of minimum degaussing duration control method, when input voltage or output voltage wide variation, minimum power tube ON time can be utilized, under system power dissipation minimal condition, namely realize the efficiently sampling to output voltage.
The present invention is achieved in that a kind of minimum degaussing duration control method, and described minimum degaussing duration control method comprises the following steps:
Power tube disconnects, and samples to output voltage;
Judge output voltage sampling finish time inductive current whether zero passage or contrast inductance degaussing time and the output voltage sampling time;
Be not more than the output voltage sampling time when each output voltage sampling finish time inductive current zero passage or inductance degaussing time, output voltage sampling is invalid, increases minimum ON time and samples for next cycle output voltage;
When each output voltage sampling finish time inductive current, zero passage or inductance degaussing time are not greater than the output voltage sampling time, output voltage sampling effectively, the minimum ON time limiting value that more minimum ON time and internal system are arranged, if minimum ON time is greater than the minimum ON time limiting value that internal system is arranged, reduce minimum ON time and sample for next cycle output voltage, if minimum ON time is less than or equal to the minimum ON time limiting value that internal system is arranged, then minimum ON time changes minimum ON time limiting value into.
A kind of minimum degaussing time-controlling arrangement, described minimum degaussing time-controlling arrangement comprises: inductive current zero cross detection circuit, trigger and minimum ON time Circuit tuning, and described inductive current zero cross detection circuit is for judging whether inductive current was in nought state.
Further,
Described minimum degaussing time-controlling arrangement working method is, described inductive current zero cross detection circuit exports the first high level or low level signal inputs described trigger, output voltage sampled signal inputs described trigger and as the clock signal of described trigger, described trigger gathers described first high level or low level signal in output voltage sampled signal finish time and exports high level or low level FLAG signal to represent the validity that output voltage is sampled, described minimum ON time Circuit tuning adjusts minimum ON time according to described FLAG signal, described minimum ON time input PWM generative circuit.
Preferably, described inductive current zero cross detection circuit can detect inductive current whether zero passage by comparator.
Preferably, described inductive current zero cross detection circuit is by the voltage measured on output voltage sampling resistor or detect voltage that inductive current detects resistance RCS to judge inductive current whether zero passage.
Preferably, described trigger is d type flip flop or JK flip-flop.
Preferably, described minimum ON time Circuit tuning is TON_MIN control circuit or IPK_MIN control circuit.
Preferably, the described minimum degaussing time adjusting circuit course of work is:
When FLAG is high level, then switch S 2 conducting one section is by the Oneshot pulse controlled time, is discharged to electric capacity C1 by drop-down constant-current source I2, and VC voltage reduces; When DRV signal becomes 1 from 0, constant-current source I3 charges to electric capacity C2, when the voltage on C2 exceeds VC voltage, comparator COMP2 exports high level, if now on C2, voltage also exceeds VREF simultaneously, then the minimum ON time TON_MIN of power tube exports high level, and TON_MIN exports high level and represents that the minimum ON time of DRV terminates;
When FLAG is low level, then switch S 1 conducting one section is by the Oneshot pulse controlled time, is charged to electric capacity C1 by pull-up constant-current source I1, and VC voltage raises.
Compared with prior art, beneficial effect of the present invention:
(1) a kind of minimum degaussing duration control method of the present invention, when input voltage or output voltage wide variation, can utilize minimum power tube ON time, namely realize the efficiently sampling to output voltage under system power dissipation minimal condition;
(2) a kind of minimum degaussing duration control method of the present invention, by the control of minimum degaussing time, make the minimum ON time length of system during zero load near output voltage sampled signal time span point, optimize the stand-by power consumption of system, there is high efficiency;
(3) a kind of minimum degaussing time-controlling arrangement of the present invention, is a kind of adaptive controller, greatly simplify the complexity that periphery design uses, apply very convenient.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the floating ground structure non-isolation DC-DC power circuit diagram of background technology;
Fig. 2 is the output voltage sample waveform figure of Fig. 1 in background technology;
Fig. 3 is the present invention's minimum degaussing duration control method flow chart;
Fig. 4 is the present invention's minimum degaussing time-controlling arrangement flow chart;
Fig. 5 is the embodiment of the present invention one minimum degaussing time-controlling arrangement flow chart;
Fig. 6 is the embodiment of the present invention two minimum degaussing time-controlling arrangement flow chart;
Fig. 7 is the minimum ON time Circuit tuning figure of the embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
It should be noted that, when element is called as " being fixed on " or " being arranged at " another element, it can directly on another element or may there is centering elements simultaneously.When an element is known as " being connected to " another element, it can be directly connected to another element or may there is centering elements simultaneously.
Also it should be noted that, the orientation term such as left and right, upper and lower in the embodiment of the present invention, is only relative concept or be reference with the normal operating condition of product each other, and should not be regarded as have restrictive.
As shown in Figure 3, the minimum degaussing duration control method of the one that the embodiment of the present invention provides, described minimum degaussing duration control method comprises:
Step 101, power tube disconnects, and samples to output voltage;
Step 102, judges output voltage sampling finish time inductive current whether zero passage or contrast inductance degaussing time and the output voltage sampling time;
Step 103, be not more than the output voltage sampling time when each output voltage sampling finish time inductive current zero passage or inductance degaussing time, output voltage sampling is invalid, step 104, increases minimum ON time and samples for next cycle output voltage;
Step 105, when each output voltage sampling finish time inductive current, zero passage or inductance degaussing time are not greater than the output voltage sampling time, output voltage sampling effectively, step 106, the minimum ON time limiting value that more minimum ON time and internal system are arranged, step 107, if minimum ON time is greater than the minimum ON time limiting value that internal system is arranged, reduce minimum ON time and sample for next cycle output voltage, step 108, if minimum ON time is less than or equal to the minimum ON time limiting value that internal system is arranged, then minimum ON time changes minimum ON time limiting value into.
A kind of minimum degaussing duration control method of the present invention, when input voltage or output voltage wide variation, can utilize minimum ON time, namely under system power dissipation minimal condition, realize the efficiently sampling to output voltage.
As Fig. 4, a kind of minimum degaussing time-controlling arrangement, described minimum degaussing time-controlling arrangement comprises: inductive current zero cross detection circuit 201, trigger 204 and minimum ON time Circuit tuning 206, and described inductive current zero cross detection circuit 201 is for judging whether inductive current was in nought state.
As shown in Figure 4, described minimum degaussing time-controlling arrangement working method is, described inductive current zero cross detection circuit 201 exports the first high level or low level signal 202 inputs described trigger 204, output voltage sampled signal 203 inputs described trigger 204 and as the clock signal of described trigger 204, described trigger 204 gathers described first high level or low level signal 202 in output voltage sampled signal 203 finish time and exports high level or low level FLAG signal 205 to represent the validity that output voltage is sampled, described minimum ON time Circuit tuning 206 adjusts minimum ON time 207 according to described FLAG signal 205, described minimum ON time 207 inputs PWM generative circuit 208.
Described first high level or low level signal 202 are in order to represent whether inductive current was in nought state.
Minimum ON time Circuit tuning 206 carrys out the minimum ON time of control system according to FLAG signal 205, if such as FLAG=1, reduces the minimum ON time of system, if FLAG=0, increases the minimum ON time of system.
As shown in Figures 4 to 6, described inductive current zero cross detection circuit 201 can detect inductive current whether zero passage by comparator.
As shown in Figures 4 to 6, described inductive current zero cross detection circuit 201 is by the voltage measured on output voltage sampling resistor or detect voltage that inductive current detects resistance RCS to judge inductive current whether zero passage.
As shown in Figures 4 to 6, described trigger 204 is d type flip flop or JK flip-flop.
As shown in Figures 4 to 6, described minimum ON time Circuit tuning 206 is TON_MIN (the minimum ON time of system) control circuit 209 or IPK_MIN (the minimum peak electric current of system) control circuit 210.
Embodiment one, described minimum ON time Circuit tuning 206 is that the minimum ON time of the output signal of TON_MIN control circuit 209, TON_MIN control circuit 209 and system is to PWM generative circuit 208.Under a normal load, the ON time of system is exported by the EA of PWM generative circuit 208 inside and determines, ON time is generally all greater than TON_MIN, now the work of TON_MIN signal not influential system; And when system enters zero load or pole light-load mode, the ON time required by PWM generative circuit 208 may be very little, the TON_MIN control circuit 209 now set by minimum degaussing time-controlling arrangement decides the ON time of system.The minimum ON time Circuit tuning 206 of minimum degaussing time-controlling arrangement, be the minimum degaussing time of being carried out indirectly control system by the minimum ON time of control system, by monitoring the inductive current of output voltage sampled signal finish time, whether zero passage judges whether the degaussing time of system is greater than the time span of output voltage sampled signal.Under zero load or pole light-load conditions, minimum degaussing time-controlling arrangement works, and consequently under limit, the degaussing time of inductance or transformer approximates the time span of output voltage sampled signal.
Embodiment two, described minimum ON time Circuit tuning 206 is IPK_MIN control circuit 210.Such as the relation of BUCK type DC-DC, TON_MIN and degaussing time is as follows:
The inductance peak current that TON_MIN is corresponding is
at inductive current discharge regime, the pass of degaussing time and IPK is
combine two equatioies to obtain
so the degaussing time can be controlled by control TON_MIN.
As shown in Figure 7, the described minimum ON time Circuit tuning course of work is:
When FLAG is high level, then switch S 2 conducting one section is by the Oneshot pulse controlled time, is discharged to electric capacity C1 by drop-down constant-current source I2, and VC voltage reduces; When DRV signal becomes 1 from 0, constant-current source I3 charges to electric capacity C2, when the voltage on C2 exceeds VC voltage, comparator COMP2 exports high level, if now on C2, voltage also exceeds VREF simultaneously, then the minimum ON time TON_MIN of power tube exports high level, and TON_MIN exports high level and represents that the minimum ON time of DRV terminates;
When FLAG is low level, then switch S 1 conducting one section is by the Oneshot pulse controlled time, is charged to electric capacity C1 by pull-up constant-current source I1, and VC voltage raises.
Obviously, VC voltage reduces, then TON_MIN reduces; VC voltage raises, then TON_MIN increases.It achieves and reduces at FLAG=1, TON_MIN, in the function that FLAG=0, TON_MIN increase.
Wherein the effect of comparator COMP1 and reference voltage VREF1 is used to set TON_MIN_LMT, limits the least limit time of the TON_MIN of system.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement or improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a minimum degaussing duration control method, is characterized in that, described minimum degaussing duration control method comprises the following steps:
Power tube disconnects, and samples to output voltage;
Judge output voltage sampling finish time inductive current whether zero passage or contrast inductance degaussing time and the output voltage sampling time;
Be not more than the output voltage sampling time when each output voltage sampling finish time inductive current zero passage or inductance degaussing time, output voltage sampling is invalid, increases minimum ON time and samples for next cycle output voltage;
When each output voltage sampling finish time inductive current, zero passage or inductance degaussing time are not greater than the output voltage sampling time, output voltage sampling effectively, the minimum ON time limiting value that more minimum ON time and internal system are arranged, if minimum ON time is greater than the minimum ON time limiting value that internal system is arranged, reduce minimum ON time and sample for next cycle output voltage, if minimum ON time is less than or equal to the minimum ON time limiting value that internal system is arranged, then minimum ON time changes minimum ON time limiting value into.
2. a minimum degaussing time-controlling arrangement, it is characterized in that, described minimum degaussing time-controlling arrangement comprises: inductive current zero cross detection circuit, trigger and minimum ON time Circuit tuning, and described inductive current zero cross detection circuit is for judging whether inductive current was in nought state.
3. minimum degaussing time-controlling arrangement according to claim 2, it is characterized in that, described minimum degaussing time-controlling arrangement working method is, described inductive current zero cross detection circuit exports the first high level or low level signal inputs described trigger, output voltage sampled signal inputs described trigger and as the clock signal of described trigger, described trigger gathers described first high level or low level signal in output voltage sampled signal finish time and exports high level or low level FLAG signal to represent the validity that output voltage is sampled, described minimum ON time Circuit tuning adjusts minimum ON time according to described FLAG signal, described minimum ON time input PWM generative circuit.
4. the minimum degaussing time-controlling arrangement according to Claims 2 or 3, is characterized in that, described inductive current zero cross detection circuit can detect inductive current whether zero passage by comparator.
5. minimum degaussing time-controlling arrangement according to claim 4, it is characterized in that, described inductive current zero cross detection circuit is by the voltage measured on output voltage sampling resistor or detect voltage that inductive current detects resistance RCS to judge inductive current whether zero passage.
6. the minimum degaussing time-controlling arrangement according to Claims 2 or 3, is characterized in that, described trigger is d type flip flop or JK flip-flop.
7. the minimum degaussing time-controlling arrangement according to Claims 2 or 3, is characterized in that, described minimum ON time Circuit tuning is TON_MIN control circuit or IPK_MIN control circuit.
8. the minimum degaussing time-controlling arrangement according to Claims 2 or 3, is characterized in that, the described minimum degaussing time adjusting circuit course of work is:
When FLAG is high level, then switch S 2 conducting one section is by the Oneshot pulse controlled time, is discharged to electric capacity C1 by drop-down constant-current source I2, and VC voltage reduces; When DRV signal becomes 1 from 0, constant-current source I3 charges to electric capacity C2, when the voltage on C2 exceeds VC voltage, comparator COMP2 exports high level, if now on C2, voltage also exceeds VREF simultaneously, then the minimum ON time TON_MIN of power tube exports high level, and TON_MIN exports high level and represents that the minimum ON time of DRV terminates;
When FLAG is low level, then switch S 1 conducting one section is by the Oneshot pulse controlled time, is charged to electric capacity C1 by pull-up constant-current source I1, and VC voltage raises.
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| CN201511027974.XA CN105449996B (en) | 2015-12-31 | 2015-12-31 | Minimum degaussing duration control method and device |
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| CN201511027974.XA CN105449996B (en) | 2015-12-31 | 2015-12-31 | Minimum degaussing duration control method and device |
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| CN105449996B CN105449996B (en) | 2018-04-06 |
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Cited By (3)
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| CN113507213A (en) * | 2021-08-23 | 2021-10-15 | 苏州中科华矽半导体科技有限公司 | Current mode control method of boost power supply chip for wide input application |
| CN113992019A (en) * | 2021-10-11 | 2022-01-28 | 茂睿芯（深圳）科技有限公司 | Control method and device of flyback converter and electronic equipment |
| CN114825892A (en) * | 2022-05-27 | 2022-07-29 | 杭州晶丰明源半导体有限公司 | Minimum on-time circuit, controller, circuit system and current detection method |
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