CN105448946A - Image sensing chip packaging structure and realization process - Google Patents
Image sensing chip packaging structure and realization process Download PDFInfo
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- CN105448946A CN105448946A CN201610002545.5A CN201610002545A CN105448946A CN 105448946 A CN105448946 A CN 105448946A CN 201610002545 A CN201610002545 A CN 201610002545A CN 105448946 A CN105448946 A CN 105448946A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims description 83
- 230000008569 process Effects 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 63
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 57
- 229910052802 copper Inorganic materials 0.000 claims abstract description 56
- 239000010949 copper Substances 0.000 claims abstract description 56
- 239000000463 material Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000011521 glass Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- 229920002120 photoresistant polymer Polymers 0.000 claims description 47
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 238000002161 passivation Methods 0.000 claims description 24
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 21
- 239000010936 titanium Substances 0.000 claims description 21
- 229910052719 titanium Inorganic materials 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 238000005476 soldering Methods 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 238000000608 laser ablation Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000000843 powder Substances 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 239000000919 ceramic Substances 0.000 claims 1
- 238000010992 reflux Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000008054 signal transmission Effects 0.000 abstract description 3
- 230000008646 thermal stress Effects 0.000 abstract description 3
- 230000006872 improvement Effects 0.000 description 21
- 238000005530 etching Methods 0.000 description 6
- 210000003127 knee Anatomy 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 4
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 208000037656 Respiratory Sounds Diseases 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses an image sensing chip packaging structure and a manufacturing method therefor, and belongs to the field of semiconductor packaging. The packaging structure comprises an image sensing chip and a transparent substrate, wherein the image sensing chip is connected with the transparent substrate through a chip micro-convex point. According to the packaging structure and the manufacturing method, a copper micro-convex point with relatively high rigidity and relatively high strength is adopted for replacing a macromolecular material to connect the image sensing chip with a glass cover plate, so that the shortcoming of poor thickness uniformity of macromolecular support walls is overcome, the thermal stress caused by difference of thermal expansion coefficients is reduced, and the problems of layering, cracks and the like in the structure are improved; the height of the copper micro-convex point can be adjusted according to actual needs, so that the requirement of the image sensing chip on a distance between the glass cover plate and a light sensing region of the chip is met; and a signal of the light sensing region of the image sensing chip is transmitted directly through the copper micro-convex point on one side of the light sensing region, and a signal transmission distance is relatively short, so that the problem of signal delay is improved.
Description
Technical field
The present invention relates to a kind of semiconductor chip package and preparation method thereof, particularly relate to a kind of image sensing chip-packaging structure and preparation method thereof, belong to field of semiconductor package.
Background technology
Image sensing chip is a kind of semiconductor module, is a kind of equipment optical image being converted into electronic signal, and electronic signal can be used for storing after process or digitlization further, or shows etc. for image is passed to display unit.It is widely used in digital camera and other electro-optical devices.Image sensing chip is mainly divided into charge coupled device (CCD) and CMOS (CIS) two class.Although CCD image sensor is better than CMOS in the quality of image and noise etc., cmos sensor can with traditional semiconductor fabrication techniques manufacture, and production cost is lower.Simultaneously because parts number used is relatively less and signal transmission distance is short, CMOS possesses the advantages such as low in energy consumption, electric capacity, inductance and stray delay reduction.
Along with the appearance of various Advanced Packaging, the packing forms of image sensing chip also towards gentlier, thinner, more portable future development, also require higher performance, faster speed and lower cost simultaneously.
The surrounding of chip and glass cover-plate bonds together by current sensing chip structure general knee wall (macromolecular material) that affects, need to leave certain distance between chip photosensitive area and glass cover-plate, this just requires that knee wall must have certain thickness simultaneously.But due to the knee wall strength and stiffness adopted at present less, and caliper uniformity is poor, be not enough to ensure there are enough distances between chip photosensitive area and glass cover-plate, generally only there are 30 ~ 50 μm, and chip and the problem such as glass cover-plate joint poor flatness and glass surface out-of-flatness can be caused.In addition, because the thermal expansion coefficient difference of knee wall material and other materials is comparatively large, makes the problem such as crackle, layering that the interface of knee wall and other materials easily occurs to be caused by thermal stress, thus cause product failure.In addition, the signal of chip photosensitive area is generally passed to chip back via the silicon through hole of chip surrounding or silicon groove by metallic circuit by existing image sensing chip structure, and signaling path is longer, and signal delay is comparatively serious.
Therefore, in the urgent need to a kind of high reliability, high performance image sensing chip-packaging structure.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of image sensing chip-packaging structure and preparation method thereof is provided, by encapsulating structure of the invention process, can ensure there are enough spacing between chip and glass cover-plate, the lamination problem of chip and glass cover-plate can be improved, can signaling path be shortened, improve chip speed.
Technical scheme of the present invention is achieved in that
A kind of image sensing chip-packaging structure, is characterized in that, comprising:
Image sensing chip 104, described image sensing chip has photosensitive area 100a, chip passivation layer 100b, chip bonding pad 100c and chip bump lower metal layer 100d, and described chip bump lower metal layer is manufactured with chip micro convex point 119;
Transparency carrier 105, described transparency carrier side deposits layer of titanium metal 106, metal copper layer 107 and substrate passivation layer 109 successively, is manufactured with substrate micro convex point 121 outside described transparency carrier, and transparent area 116 is left in described transparency carrier centre position.
As a further improvement on the present invention, described image sensing chip-packaging structure, it is characterized in that, described image sensing chip 104 realizes interconnecting by chip micro convex point 119 and transparency carrier 105, chip photosensitive area 100a towards transparency carrier and with transparent area 116 centering.
As a further improvement on the present invention, described image sensing chip-packaging structure, is characterized in that, described chip passivation layer 100b can be the materials such as silica, silicon nitride, polyimides PI.
As a further improvement on the present invention, described image sensing chip-packaging structure, is characterized in that, described chip micro convex point 119 can be copper micro convex point or golden micro convex point.
As a further improvement on the present invention, described image sensing chip-packaging structure, is characterized in that, described transparency carrier 105 can be the materials such as glass, quartz, pottery.
As a further improvement on the present invention, described image sensing chip-packaging structure, is characterized in that, described substrate passivation layer 109 can be the materials such as silica, silicon nitride, polyimides PI.
As a further improvement on the present invention, described image sensing chip-packaging structure, is characterized in that, described substrate micro convex point 121 can be copper micro convex point or golden micro convex point.
Image sensing chip-packaging structure realize a technique, it is characterized in that, comprise the following steps:
Step 1, provides a wafer 100, and described wafer functional surfaces is front, and the one side contrary with it is reverse side.Front has photosensitive area 100a, chip passivation layer 100b, some chip bonding pad 100c, described chip bonding pad is formed with chip bump lower metal layer 100d;
Step 2, in described wafer 100 front surface coated first photoresist layer 101, and is forming the first photoresist layer first opening 110 with the chip bump lower metal layer 100d of exposed bottom by exposure, developing manufacture process with chip bump lower metal layer corresponding position;
Step 3, depositing chip copper bump 102 in described first photoresist layer first opening 110, bump height is 50 ~ 100 μm;
Step 4, depositing chip solder layer 103 on described chip copper bump 102, solder layer is 10 ~ 20 μm;
Step 5, removes the first photoresist layer 101, and the described chip soldering bed of material 103 is carried out backflow formation chip micro convex point 119;
Step 6, cuts described wafer 100, by discrete for wafer be single chips 104;
Step 7, provides a transparency carrier 105, and in described transparency carrier side plated metal titanium layer 106, titanium layer thickness is 2 ~ 3 μm;
Step 8, plated metal layers of copper 107 in described layer of titanium metal 106, copper layer thickness is for being 2 ~ 3 μm;
Step 9, applies the second photoresist layer 108 in described metal copper layer 107, and is forming the second photoresist layer second opening 120 with the metal copper layer 107 of exposed bottom by exposure, developing manufacture process with metallic circuit and corresponding position, transparent area;
Step 10, with the second photoresist layer 108 for mask carries out isotropism wet etching, the metal copper layer 107 that removal exposes and layer of titanium metal 106 are to expose transparent area 116;
Step 11, removes the second photoresist layer 108;
Step 12, deposits a laminar substrate passivation layer 109 in described metal copper layer 107, and exposes transparent area 116, substrate ubm layer 117 and substrate pads 118;
Step 13, applies the 3rd photoresist layer 111 on described substrate passivation layer 109, and is forming the 3rd opening 130 with exposed bottom substrate ubm layer 117 by exposure, developing manufacture process with substrate ubm layer corresponding position;
Step 14, deposition substrate copper bump 112 in described 3rd photoresist layer the 3rd opening 130, bump height is 200 ~ 300 μm;
Step 15, deposition substrate solder layer 113 on described substrate copper bump 112, solder layer is 20 ~ 30 μm;
Step 16, removes the 3rd photoresist layer 111;
Step 17, applies scaling powder 114, and chip micro convex point is aimed at the substrate pads 118 on transparency carrier 105 in the chip micro convex point 119 of described chip 104;
Step 18, is placed into the chip micro convex point 119 of described chip 104 in the substrate pads 118 of transparency carrier 105, and carries out backflow formation interconnection solder joint 115 and substrate micro convex point 121;
Step 19, carries out cutting to described transparency carrier 105 and obtains single image sensing chip package.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, step 1 synchronously can be carried out to step 16 with step 7 to step 6, or first does step 7 to step 16 and then perform step 1 to step 6.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the formation method of described chip copper bump 102 is galvanoplastic.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the described chip soldering bed of material 103 is tin-silver solder or tin-silver-copper solder.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the deposition process of the described chip soldering bed of material 103 is galvanoplastic or silk screen print method.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the removing method of described first photoresist layer 101 is for peeling off or etching.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the segmentation method of described wafer 100 is machine cuts or laser ablation.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the formation method of described layer of titanium metal 106 and metal copper layer 107 is PVD.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, remove the layer of titanium metal 106 that exposes and the method for metal copper layer 107 is wet etching.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the removing method of described second photoresist layer 108 is for peeling off or etching.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the formation method of described substrate passivation layer 109 is PECVD or CVD.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the formation method of described substrate copper bump 112 is galvanoplastic.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, described substrate solder layer 113 is tin-silver solder or tin-silver-copper solder.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the deposition process of described substrate solder layer 113 is galvanoplastic or silk screen print method.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the removing method of described 3rd photoresist layer 111 is for peeling off or etching.
As a further improvement on the present invention, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the cutting method of described transparency carrier 105 is machine cuts or laser ablation.
Compared with prior art, the invention has the beneficial effects as follows:
The invention provides a kind of image sensing chip-packaging structure and preparation method thereof.
1. by adopting the copper or golden micro convex point replacement macromolecular material connection image sensing chip and glass cover-plate that rigidity is comparatively large, intensity is relatively high, overcome the shortcoming of macromolecule knee wall caliper uniformity difference, reduce the thermal stress that thermal expansion coefficient difference causes, improve the problems such as the layering in structure, crackle.
2. the height of copper or golden micro convex point can adjust according to actual needs, is generally 50 ~ 100 μm, can ensure there are enough distances between glass cover-plate and chip photosensitive area.
3. realize perpendicular interconnection by copper or au bump between image sensing chip photosensitive area and glass cover-plate circuit, compared to prior art, signal transmission distance can shorten 30% ~ 50%, thus can improve signal delay problem.
Accompanying drawing explanation
Fig. 1 is the image sensing chip-packaging structure schematic diagram drawn according to the embodiment of the present invention.
Fig. 2 ~ Figure 20 is the schematic diagram of the image sensing chip-packaging structure manufacture method according to embodiment of the present invention drafting.
Fig. 2 is the encapsulating structure generalized section after step 1.
Fig. 3 is the encapsulating structure generalized section after step 2.
Fig. 4 is the encapsulating structure generalized section after step 3.
Fig. 5 is the encapsulating structure generalized section after step 4.
Fig. 6 is the encapsulating structure generalized section after step 5.
Fig. 7 is the encapsulating structure generalized section after step 6.
Fig. 8 is the encapsulating structure generalized section after step 7.
Fig. 9 is the encapsulating structure generalized section after step 8.
Figure 10 is the encapsulating structure generalized section after step 9.
Figure 11 is the encapsulating structure generalized section after step 10.
Figure 12 is the encapsulating structure generalized section after step 11.
Figure 13 is the encapsulating structure generalized section after step 12.
Figure 14 is the encapsulating structure generalized section after step 13.
Figure 15 is the encapsulating structure generalized section after step 14.
Figure 16 is the encapsulating structure generalized section after step 15.
Figure 17 is the encapsulating structure generalized section after step 16.
Figure 18 is the encapsulating structure generalized section after step 17.
Figure 19 is the encapsulating structure generalized section after step 18.
Figure 20 is the encapsulating structure generalized section after step 19.
By reference to the accompanying drawings, make the following instructions:
100-wafer 100a-chip photosensitive area
100b-chip passivation layer 100c-chip bonding pad
100d-chip bump lower metal layer 101-first photoresist layer
The 102-chip copper bump 103-chip soldering bed of material
104-mono-chips 105-transparency carrier
106-layer of titanium metal 107-metal copper layer
108-second photoresist layer 109-substrate passivation layer
110-first photoresist layer first opening 111-the 3rd photoresist layer
112-substrate copper bump 113-substrate solder layer
114-scaling powder 115-interconnects solder joint
116-transparent area 117-substrate ubm layer
118-substrate pads 119-chip micro convex point
120-second photoresist layer second opening 121-substrate micro convex point
130-the 3rd photoresist layer the 3rd opening
Embodiment
In order to more clearly understand technology contents of the present invention, describe in detail especially exemplified by following examples, and coordinate accompanying drawing to elaborate to above-mentioned feature and advantage of the present invention.Its object is only better understand content of the present invention but not limit the scope of the invention.The semiconductor package of the embodiment of the present invention may be used for the preparation of micro convex point, but its application is not limited to this.
With reference to Fig. 1, this schematic diagram is the image sensing chip-packaging structure of embodiment of the present invention, comprising:
Image sensing chip 104, described image sensing chip has photosensitive area 100a, chip passivation layer 100b, chip bonding pad 100c and chip bump lower metal layer 100d, and described chip bump lower metal layer is manufactured with chip micro convex point 119;
Transparency carrier 105, described transparency carrier side deposits layer of titanium metal 106, metal copper layer 107 and substrate passivation layer 109 successively, is manufactured with substrate micro convex point 121 outside described transparency carrier, and transparent area 116 is left in described transparency carrier centre position.
Alternatively, described image sensing chip 104 realizes interconnecting by chip micro convex point 119 and transparency carrier 105, chip photosensitive area 100a towards transparency carrier and with transparent area 116 centering.
Alternatively, described chip passivation layer 100b can be the materials such as silica, silicon nitride, polyimides PI.
Alternatively, described chip micro convex point 119 can be copper micro convex point or golden micro convex point.
Alternatively, described transparency carrier 105 can be the materials such as glass, quartz, pottery.
Alternatively, described substrate passivation layer 109 can be the materials such as silica, silicon nitride, polyimides PI.
Alternatively, described substrate micro convex point 121 can be copper micro convex point or golden micro convex point.
See Fig. 2 to Figure 20, the manufacture method of image sensing chip-packaging structure of the present invention is as follows:
Step 1, provides a wafer 100, and described wafer functional surfaces is front, and the one side contrary with it is reverse side.Front has photosensitive area 100a, chip passivation layer 100b, some chip bonding pad 100c, described chip bonding pad is formed with chip bump lower metal layer 100d;
Step 2, in described wafer 100 front surface coated first photoresist layer 101, and is forming the first photoresist layer first opening 110 with the chip bump lower metal layer 100d of exposed bottom by exposure, developing manufacture process with chip bump lower metal layer corresponding position;
Step 3, depositing chip copper bump 102 in described first photoresist layer first opening 110, bump height is 50 ~ 100 μm;
Step 4, depositing chip solder layer 103 on described chip copper bump 102, solder layer is 10 ~ 20 μm;
Step 5, removes the first photoresist layer 101, and the described chip soldering bed of material 103 is carried out backflow formation micro convex point 119;
Step 6, cuts described wafer 100, by discrete for wafer be single chips 104;
Step 7, provides a transparency carrier 105, and in described transparency carrier side plated metal titanium layer 106, titanium layer thickness is 2 ~ 3 μm;
Step 8, plated metal layers of copper 107 in described layer of titanium metal 106, copper layer thickness is 2 ~ 3 μm;
Step 9, applies the second photoresist layer 108 in described metal copper layer 107, and is forming the second photoresist layer second opening 120 with the metal copper layer 107 of exposed bottom by exposure, developing manufacture process with metallic circuit and corresponding position, transparent area;
Step 10, with the second photoresist layer 108 for mask carries out isotropism wet etching, the metal copper layer 107 that removal exposes and layer of titanium metal 106 are to expose transparent area 116;
Step 11, removes the second photoresist layer 108;
Step 12, deposits a laminar substrate passivation layer 109 in described metal copper layer 107, and exposes transparent area 116, substrate ubm layer 117 and substrate pads 118;
Step 13, applies the 3rd photoresist layer 111 on described substrate passivation layer 109, and is forming the 3rd photoresist layer the 3rd opening 130 with exposed bottom substrate ubm layer 117 by exposure, developing manufacture process with substrate ubm layer corresponding position;
Step 14, deposition substrate copper bump 112 in described 3rd photoresist layer the 3rd opening 130, bump height is 200 ~ 300 μm;
Step 15, deposition substrate solder layer 113 on described substrate copper bump 112, solder layer is 20 ~ 30 μm;
Step 16, removes the 3rd photoresist layer 111;
Step 17, applies scaling powder 114, and chip micro convex point is aimed at the substrate pads 118 on transparency carrier 105 in the chip micro convex point 119 of described chip 104;
Step 18, is placed into the chip micro convex point 119 of described chip 104 in the substrate pads 118 of transparency carrier 105, and carries out backflow formation interconnection solder joint 115 and substrate micro convex point 121;
Step 19, carries out cutting to described transparency carrier 105 and obtains single image sensing chip package.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, step 1 synchronously can be carried out to step 16 with step 7 to step 6, or first does step 7 to step 16 and then perform step 1 to step 6.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the formation method of described chip copper bump 102 is galvanoplastic.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the described chip soldering bed of material 103 is tin-silver solder or tin-silver-copper solder.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the deposition process of the described chip soldering bed of material 103 is galvanoplastic or silk screen print method.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the removing method of described first photoresist layer 101 is for peeling off or etching.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the segmentation method of described wafer 100 is machine cuts or laser ablation.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the formation method of described layer of titanium metal 106 and metal copper layer 107 is PVD.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, remove the layer of titanium metal 106 that exposes and the method for metal copper layer 107 is wet etching.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the removing method of described second photoresist layer 108 is for peeling off or etching.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the formation method of described substrate passivation layer 109 is PECVD or CVD.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the formation method of described substrate copper bump 112 is galvanoplastic.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, described substrate solder layer 113 is tin-silver solder or tin-silver-copper solder.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the deposition process of described substrate solder layer 113 is galvanoplastic or silk screen print method.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the removing method of described 3rd photoresist layer 111 is for peeling off or etching.
Alternatively, described a kind of image sensing chip-packaging structure realize technique, it is characterized in that, the cutting method of described transparency carrier 105 is machine cuts or laser ablation.
Although the embodiment of the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. an image sensing chip-packaging structure, is characterized in that, comprising:
Image sensing chip (104), comprise photosensitive area (100a), chip passivation layer (100b), chip bonding pad (100c) and chip bump lower metal layer (100d), described chip bump lower metal layer is manufactured with chip micro convex point (119);
Transparency carrier (105), described transparency carrier side deposits layer of titanium metal (106), metal copper layer (107) and substrate passivation layer (109) successively, described transparency carrier one end is manufactured with substrate micro convex point (121), and transparent area (116) is left in described transparency carrier centre position;
Described image sensing chip (104) realizes interconnecting by chip micro convex point (119) and transparency carrier (105), chip photosensitive area (100a) towards transparency carrier and with transparent area (116) centering.
2. image sensing chip-packaging structure according to claim 1, is characterized in that, described chip micro convex point (119) is copper micro convex point or golden micro convex point.
3. image sensing chip-packaging structure according to claim 1, is characterized in that, described transparency carrier (105) is glass, quartz or ceramic.
4. image sensing chip-packaging structure realize a technique, it is characterized in that, comprise the following steps:
Step 1, provides a wafer (100), and described wafer functional surfaces is front, and the one side contrary with it is reverse side; Front has photosensitive area (100a), chip passivation layer (100b), some chip bonding pads (100c), described chip bonding pad is formed with chip bump lower metal layer (100d);
Step 2, in described wafer (100) front surface coated first photoresist layer (101), and forming the first photoresist layer first opening (110) with the chip bump lower metal layer (100d) of exposed bottom by exposure, developing manufacture process with chip bump lower metal layer corresponding position;
Step 3, depositing chip copper bump (102) in described first photoresist layer first opening (110);
Step 4, in the upper depositing chip solder layer (103) of described chip copper bump (102);
Step 5, removes the first photoresist layer (101), and the described chip soldering bed of material (103) is carried out high temperature reflux formation chip micro convex point (119);
Step 6, cuts described wafer (100), by discrete for wafer be single chips (104);
Step 7, provides a transparency carrier (105), in described transparency carrier side plated metal titanium layer (106);
Step 8, in the upper plated metal layers of copper (107) of described layer of titanium metal (106);
Step 9, in upper coating second photoresist layer (108) of described metal copper layer (107), and forming the second photoresist layer second opening (120) with the metal copper layer of exposed bottom (107) by exposure, developing manufacture process with metallic circuit and corresponding position, transparent area;
Step 10, with the second photoresist layer (108) for mask carries out isotropism wet etching, the metal copper layer (107) that removal exposes and layer of titanium metal (106) are to expose transparent area (116);
Step 11, removes the second photoresist layer (108);
Step 12, in upper deposition one laminar substrate passivation layer (109) of described metal copper layer (107), and exposes transparent area (116), substrate ubm layer (117) and substrate pads (118);
Step 13, in the upper coating the 3rd photoresist layer (111) of described substrate passivation layer (109), and forming the 3rd photoresist layer the 3rd opening (130) with exposed bottom substrate ubm layer (117) by exposure, developing manufacture process with substrate ubm layer corresponding position;
Step 14, deposition substrate copper bump (112) in described 3rd photoresist layer the 3rd opening (130);
Step 15, in the upper deposition substrate solder layer (113) of described substrate copper bump (112);
Step 16, removes the 3rd photoresist layer (111);
Step 17, applies scaling powder (114), and chip micro convex point is aimed at the substrate pads (118) on transparency carrier (105) in the chip micro convex point (119) of described chip (104);
Step 18, the chip micro convex point (119) of described chip (104) is placed in the substrate pads (118) of transparency carrier (105), and carries out backflow formation interconnection solder joint (115) and substrate micro convex point (121);
Step 19, carries out cutting to described transparency carrier (105) and obtains single image sensing chip package.
5. a kind of image sensing chip-packaging structure according to claim 8 realize technique, it is characterized in that, step 1 is synchronously carried out to step 6 and step 7 to step 16, or first does step 7 to step 16 and then perform step 1 to step 6.
6. a kind of image sensing chip-packaging structure according to claim 8 realize technique, it is characterized in that, the cutting method of described wafer (100) is machine cuts or laser ablation.
7. a kind of image sensing chip-packaging structure according to claim 8 realize technique, it is characterized in that, the formation method of described layer of titanium metal (106) or metal copper layer (107) is PVD.
8. a kind of image sensing chip-packaging structure according to claim 8 realize technique, it is characterized in that, remove the layer of titanium metal (106) that exposes and the method for metal copper layer (107) is wet etching.
9. a kind of image sensing chip-packaging structure according to claim 8 realize technique, it is characterized in that, the formation method of described substrate passivation layer (109) is PECVD or CVD.
10. a kind of image sensing chip-packaging structure according to claim 8 realize technique, it is characterized in that, the cutting method of described transparency carrier (105) is machine cuts or laser ablation.
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