CN105448895A - High-voltage MiP capacitor and manufacturing method thereof - Google Patents
High-voltage MiP capacitor and manufacturing method thereof Download PDFInfo
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- CN105448895A CN105448895A CN201410360152.2A CN201410360152A CN105448895A CN 105448895 A CN105448895 A CN 105448895A CN 201410360152 A CN201410360152 A CN 201410360152A CN 105448895 A CN105448895 A CN 105448895A
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Abstract
The invention provides a high-voltage MiP capacitor which comprises a polycrystalline silicon pole plate, which is arranged to the bottom portion of the high-voltage MiP capacitor and serves as a first lower pole plate of the high-voltage MiP capacitor; a first metal pole plate, which is arranged at the top portion of the high-voltage MiP capacitor and serves as a second lower pole plate thereof; a second metal pole plate, which is arranged between the polycrystalline silicon pole plate and the first metal pole plate and serves as an upper pole plate of the high-voltage MiP capacitor; and a dielectric layer, which is filled between the polycrystalline silicon pole plate and the second metal pole plate and between the first metal pole plate and the second metal pole plate. Besides, the invention also provides a manufacturing method of the high-voltage MiP capacitor.
Description
Technical field
The present invention relates to semiconductor device and manufacture field, particularly relate to a kind of high voltage MiP capacitor and manufacture method thereof of novel structure.
Background technology
PiP (poly-insulator-poly, polycrystalline silicon-on-insulator-polysilicon) capacitor is that one is widely used in and prevents analog circuit from launching noise and warbled device.Because PiP capacitor has the top crown and bottom crown formed by polysilicon (identical with the material of the gate electrode of logical circuit), therefore the electrode of PiP capacitor can be formed together with gate electrode, and without the need to independent formation process.
Such as, Fig. 1 shows the basic structure of a kind of PiP capacitor of prior art, as shown in Figure 1, this PiP capacitor 100 mainly comprises: the polysilicon layer 2101 being used as PiP top crown arranged from top to bottom successively, insulator layer 102 and the polysilicon layer 1103 as PiP bottom crown.
MiM (Metal-Insulator-Metal, metal-insulator-metal type) electric capacity is produced on interconnection layer by capacitance technology, i.e. postchannel process (BEOL, BackEndOfLine) in, both mutually compatible with integrated circuit technology, again by zooming out the distance between passive device and conductive substrates, overcoming that parasitic capacitance is large, device performance increases with frequency and obvious lower degradation problem, making this technology become the main flow making passive capacitor part in RF integrated circuit gradually.In addition, MiM electric capacity can also reduce the degree of difficulty and complexity technology integrated with CMOS front-end process.Therefore, MiM capacitance technology is developed just fast.
But traditional MiM and PiP capacitor only can meet low-voltage (<10V) digit chip needs.For the application of high voltage (HV, HighVoltage) >10V, traditional MiM and PiP capacitor just shows larger inferior position in balance puncture voltage and capacitance density.
Therefore, the relation between the puncture voltage/capacitance/process complexity how weighing capacitor is a hot issue of this area.
Summary of the invention
The present inventor proposes a kind of MiP capacitor arrangement of novelty, to solve an above-mentioned balance difficult problem for MiM or the PiP capacitor of prior art.
According to an aspect of the present invention, provide a kind of high voltage MiP capacitor, comprising:
Polysilicon pole plate, is placed in the bottom of described high voltage MiP capacitor as its first bottom crown;
First metal polar plate, is placed in the top of described high voltage MiP capacitor as its second bottom crown;
Second metal polar plate, is arranged between described polysilicon pole plate and described first metal polar plate, as the top crown of described high voltage MiP capacitor; And
Dielectric layer, is filled between described polysilicon pole plate and described second metal polar plate and between described first metal polar plate and described second metal polar plate.
Preferably, in above-mentioned high voltage MiP capacitor, described polysilicon pole plate and described first metal polar plate are electrically connected via first passage.
Preferably, in above-mentioned high voltage MiP capacitor, also comprise: be electrically connected head, be arranged at the top of described high voltage MiP capacitor, described electric connection head is electrically connected described second metal polar plate via second channel.
Preferably, in above-mentioned high voltage MiP capacitor, described electric connection head is coated on the same plane of described high voltage MiP capacitor with identical technique and material with described first metal polar plate.
Preferably, in above-mentioned high voltage MiP capacitor, described dielectric layer is made up of inter-level dielectric isolated material.
Preferably, in above-mentioned high voltage MiP capacitor, the thickness of described inter-level dielectric isolated material is between 2000 dust to 30000 dusts.
Preferably, in above-mentioned high voltage MiP capacitor, the thickness of described dielectric layer is selected according to the requirement of puncture voltage or capacitance.
Preferably, in above-mentioned high voltage MiP capacitor, the thickness of described second metal polar plate is between 200 dust to 3000 dusts.
Preferably, in above-mentioned high voltage MiP capacitor, the operating voltage of described high voltage MiP capacitor is between 0 volt to 1200 volts.
Preferably, in above-mentioned high voltage MiP capacitor, the operating voltage of described high pressure MiP capacitor is greater than 10 volts, and the puncture voltage of described high voltage MiP capacitor is greater than 80 volts.
Preferably, in above-mentioned high voltage MiP capacitor, the thickness of the dielectric layer between described first metal polar plate and described 3rd metal polar plate is different from the dielectric layer thickness between described second metal polar plate and described 3rd metal polar plate.
According to a further aspect in the invention, additionally provide a kind of manufacture method of high voltage MiP capacitor as above, comprising:
A. deposit spathic silicon pole plate on substrate, as the first bottom crown of described high voltage MiP capacitor;
B. on described polysilicon pole plate, the first dielectric layer is deposited;
C. on described first dielectric layer, the second metal polar plate is formed, as the top crown of described high voltage MiP capacitor;
D. the second dielectric layer is deposited; And
E. on described second dielectric layer, the first metal polar plate is formed, as the second bottom crown of described high voltage MiP capacitor.
Preferably, in above-mentioned manufacture method, in described step e, comprise further: formed further on described second dielectric layer and be electrically connected head.
Preferably, in above-mentioned manufacture method, between described steps d and step e, comprise further: chemico-mechanical polishing is carried out to the upper surface of the second dielectric layer deposited; Perforate on described second dielectric layer; Deposits conductive material in described perforate, to form the first passage being electrically connected described polysilicon pole plate and described first metal polar plate and the second channel being electrically connected described second metal polar plate and described electric connection head respectively; And the unwanted metallic member removed on the upper surface of described second dielectric layer.
In sum, the invention provides a kind of capacitor of mixed type MiP structure of novelty, this MiP capacitor can obtain higher capacitance density while supporting high voltage applications.
Should be appreciated that more than the present invention generality describe and the following detailed description be all exemplary and explanat, and be intended to for as claimed in claim the invention provides further explanation.
Accompanying drawing explanation
Comprising accompanying drawing is further understand the present invention for providing, and they are included and form a application's part, and accompanying drawing shows embodiments of the invention, and plays the effect explaining the principle of the invention together with this specification.In accompanying drawing:
Fig. 1 shows the basic structure of the PiP capacitor of prior art.
Fig. 2 shows a preferred embodiment of the structure according to MiP capacitor of the present invention.
Fig. 3 shows the flow chart of the basic step of the manufacture method according to MiP capacitor of the present invention.
Fig. 4 a-Fig. 4 c shows the MiP capacitor fabrication process shown in Fig. 2.
Embodiment
With detailed reference to accompanying drawing, embodiments of the invention are described now.Now with detailed reference to the preferred embodiments of the present invention, its example is shown in the drawings.In the case of any possible, in all of the figs the identical mark of use is represented same or analogous part.In addition, although the term used in the present invention selects from public term, but some terms mentioned in specification of the present invention may be that applicant selects by his or her judgement, its detailed meanings illustrates in the relevant portion of description herein.In addition, require not only to pass through used actual terms, but the meaning that also will be contained by each term understands the present invention.
First embodiment described in reference diagram 2 describes design of the present invention in detail, wherein figure 2 show a preferred embodiment of the structure according to MiP capacitor of the present invention.
As shown in the figure, high voltage MiP capacitor 200 of the present invention mainly comprises: polysilicon pole plate 201, first metal polar plate 202, second metal polar plate 203 and dielectric layer 204.Polysilicon pole plate 201 is placed in the bottom of high voltage MiP capacitor 200 as its first bottom crown.First metal polar plate 202 is placed in the top of high voltage MiP capacitor 200 as its second bottom crown.Such as, in a preferred embodiment of figure 2, this first metal polar plate 202 is arranged on the top surface of MiP capacitor 200, like this by following the first passage 205 discussed in more detail is electrically connected this polysilicon pole plate 201 and the first metal polar plate 202 after, this first metal polar plate 202 can be used as the electric connection head of bottom crown.
Particularly, one second metal polar plate 203 is arranged between above-mentioned polysilicon pole plate 201 and the first metal polar plate 202 by the present invention, as the top crown of high voltage MiP capacitor 200.According to a preferred embodiment, the thickness of this second metal polar plate 203 can between 200 dust to 3000 dusts.
In addition, dielectric layer 204 is filled between polysilicon pole plate 201 and the second metal polar plate 203 and between the first metal polar plate 202 and the second metal polar plate 203.Preferably, dielectric layer 204 is made up of inter-level dielectric isolated material (ILD, InterlayerDielectric).
Like this, just be equivalent to define two capacitance structures in MiP capacitor 202 of the present invention, the second capacitance structure that the first capacitance structure namely formed in polysilicon pole plate 201 (bottom crown) and the second metal polar plate 203 (top crown) and the first metal polar plate 202 (bottom crown) and the second metal polar plate 203 (top crown) are formed.
In addition, according to the present invention, polysilicon pole plate 201 and the first metal polar plate 202 can be electrically connected via first passage 205.
As shown in Figure 2, above-mentioned high voltage MiP capacitor 200 can also comprise an electric connection 206, is arranged at the top of high voltage MiP capacitor 200.This electric connection 206 is electrically connected the second metal polar plate 203 via second channel 207.
Particularly, in the preferred embodiment shown in figure 2, this electric connection 206 can be coated on the same plane of high voltage MiP capacitor 200 with identical technique and material with the first metal polar plate 202, such as on the top.Can once be formed this electric connection 206 and the first metal polar plate 202 with simpler technique like this, thus be realized lower manufacturing cost.But the present invention is not limited to this.Such as, this electric connection 206 material that same first metal polar plate 202 also can be selected different, and utilize different technique to be formed.And such as, the lower surface of this electric connection 206 also can be in different planes with the first metal polar plate 202.
In the present invention, the thickness of dielectric layer 204 can be selected according to the requirement of puncture voltage or capacitance.Such as, with reference to figure 2, assuming that the thickness of dielectric layer 204 between polysilicon pole plate 201 (bottom crown) and the second metal polar plate 203 (top crown) is D1, suppose that the thickness of the dielectric layer 204 between the first metal polar plate 202 (bottom crown) and the second metal polar plate 203 (top crown) is D2 simultaneously.
Under the prerequisite that the gross thickness as D1+D2 sum is constant, if when thickness D1 is not identical with thickness D2, then to compare the identical situation of the thickness of D1 with D2 larger for the total capacitance of this MiM capacitor 200, but puncture voltage is compared lower.In addition, when the gross thickness of D1+D2 increases, puncture voltage relatively becomes large and total capacitance diminishes relatively.Like this, just can need design or regulate above-mentioned thickness D1 and D2 according to the parameter of reality.
The thickness of this dielectric layer 204, the i.e. thickness of inter-level dielectric isolated material, preferably between 2000 dust to 30000 dusts.Such as, as an example, if the thickness (D1+D2) of the dielectric layer 204 between the basal surface of polysilicon pole plate 201 and the first metal polar plate 202 be 8000 dusts and the thickness of this polysilicon pole plate 201 is 2000 dust time, the capacitance density of this MiP capacitor 200 is about 0.13*2=0.26fF/ μm 2.
Practice shows, adopts the operating voltage of the MiP capacitor of structure of the present invention between about 0 volt to about 1200 volts, more preferably between about 10 volts to about 80 volts, (can namely obtain the puncture voltage being greater than 80 volts).Only meet compared to prior art the MiP capacitor that low-voltage (<10V) applies, MiP capacitor of the present invention is suitable for applying widely.In addition, structure of the present invention can also balance MiP puncture voltage, relation between capacitance and process complexity well, realizes the solution of cost and combination property optimum.
The manufacture method according to MiP capacitor of the present invention is discussed in detail below with reference to Fig. 3 and Fig. 4 a-4c.
First, as shown in Figure 3, this manufacture method 300 mainly can comprise following step:
Step 301: deposit spathic silicon pole plate on substrate, as the first bottom crown of described high voltage MiP capacitor;
Step 302: deposit the first dielectric layer on polysilicon pole plate;
Step 303: form the second metal polar plate on the first dielectric layer, as the top crown of described high voltage MiP capacitor;
Step 304: deposit the second dielectric layer; And
Step 305: form the first metal polar plate on the second dielectric layer, as the second bottom crown of described high voltage MiP capacitor.
Forward Fig. 4 a to, first deposition of polysilicon layer 201 (step 301) on substrate.As already discussed above, this polysilicon layer 201 will as the first bottom crown in high voltage MiP capacitor.
Then, in fig. 4b, on this polysilicon layer 201, further deposit thickness is the first dielectric layer 204-1 and the metal level 203 of D2 successively, and this metal level 203 will be used as top crown in high voltage MiP capacitor.
Then, as illustrated in fig. 4 c, the second dielectric layer 204-2 is deposited on metal level 203 and part first dielectric layer 204-1.
Finally, by forming the first metal polar plate 202 on the second dielectric layer 204-2, as the second bottom crown of high voltage MiP capacitor, MiP capacitor as shown in Figure 2 can just be formed.
According to a preferred embodiment, above-mentioned described step 305 can also comprise: formed further on the second dielectric layer 204-2 and be electrically connected 206 (see Fig. 2).
In addition, in the preferred embodiment, following step can also be performed between step 304 and step 305: chemico-mechanical polishing (CMP) is carried out to the upper surface of the second dielectric layer 204-2 deposited; Perforate on the second dielectric layer 204-2 (any known photoetching or etch process such as can be utilized to carry out perforate); In perforate, deposits conductive material (such as, this electric conducting material can be tungsten), with form the first passage 205 that is electrically connected polysilicon pole plate 201 and the first metal polar plate 202 respectively and be electrically connected the second metal polar plate 203 and be electrically connected 206 second channel 207; The last unwanted metallic member (such as can utilize any known chemico-mechanical polishing, photoetching or etch process to perform this removal step) removed again on the upper surface of the second dielectric layer 204-2.
Those skilled in the art can be obvious, can carry out various modifications and variations and without departing from the spirit and scope of the present invention to above-mentioned exemplary embodiment of the present invention.Therefore, be intended to that the present invention is covered and drop within the scope of appended claims and equivalent arrangements thereof to amendment of the present invention and modification.
Claims (14)
1. a high voltage MiP capacitor, is characterized in that, comprising:
Polysilicon pole plate, is placed in the bottom of described high voltage MiP capacitor as its first bottom crown;
First metal polar plate, is placed in the top of described high voltage MiP capacitor as its second bottom crown;
Second metal polar plate, is arranged between described polysilicon pole plate and described first metal polar plate, as the top crown of described high voltage MiP capacitor; And
Dielectric layer, is filled between described polysilicon pole plate and described second metal polar plate and between described first metal polar plate and described second metal polar plate.
2. high voltage MiP capacitor as claimed in claim 1, it is characterized in that, described polysilicon pole plate and described first metal polar plate are electrically connected via first passage.
3. high voltage MiP capacitor as claimed in claim 2, is characterized in that, also comprise:
Be electrically connected head, be arranged at the top of described high voltage MiP capacitor, described electric connection head is electrically connected described second metal polar plate via second channel.
4. high voltage MiP capacitor as claimed in claim 3, it is characterized in that, described electric connection head is coated on the same plane of described high voltage MiP capacitor with identical technique and material with described first metal polar plate.
5. high voltage MiP capacitor as claimed in claim 1, it is characterized in that, described dielectric layer is made up of inter-level dielectric isolated material.
6. high voltage MiP capacitor as claimed in claim 5, it is characterized in that, the thickness of described inter-level dielectric isolated material is between 2000 dust to 30000 dusts.
7. high voltage MiP capacitor as claimed in claim 1, is characterized in that, the thickness of described dielectric layer is selected according to the requirement of puncture voltage or capacitance.
8. high voltage MiP capacitor as claimed in claim 1, it is characterized in that, the thickness of described second metal polar plate is between 200 dust to 3000 dusts.
9. high voltage MiP capacitor as claimed in claim 1, it is characterized in that, the operating voltage of described high voltage MiP capacitor is between 0 volt to 1200 volts.
10. high pressure MiP capacitor as claimed in claim 9, it is characterized in that, the operating voltage of described high pressure MiP capacitor is greater than 10 volts, and the puncture voltage of described high voltage MiP capacitor is greater than 80 volts.
11. high voltage MiP capacitors as claimed in claim 1, it is characterized in that, the thickness of the dielectric layer between described first metal polar plate and described 3rd metal polar plate is different from the dielectric layer thickness between described second metal polar plate and described 3rd metal polar plate.
The manufacture method of 12. 1 kinds of high voltage MiP capacitors as claimed in claim 1, is characterized in that, comprising:
A. deposit spathic silicon pole plate on substrate, as the first bottom crown of described high voltage MiP capacitor;
B. on described polysilicon pole plate, the first dielectric layer is deposited;
C. on described first dielectric layer, the second metal polar plate is formed, as the top crown of described high voltage MiP capacitor;
D. the second dielectric layer is deposited; And
E. on described second dielectric layer, the first metal polar plate is formed, as the second bottom crown of described high voltage MiP capacitor.
13. manufacture methods as claimed in claim 12, is characterized in that, in described step e, comprise further: formed further on described second dielectric layer and be electrically connected head.
14. manufacture methods as claimed in claim 13, is characterized in that, between described steps d and step e, comprise further:
Chemico-mechanical polishing is carried out to the upper surface of the second dielectric layer deposited;
Perforate on described second dielectric layer;
Deposits conductive material in described perforate, to form the first passage being electrically connected described polysilicon pole plate and described first metal polar plate and the second channel being electrically connected described second metal polar plate and described electric connection head respectively; And
Remove the unwanted metallic member on the upper surface of described second dielectric layer.
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| CN201410360152.2A CN105448895A (en) | 2014-07-25 | 2014-07-25 | High-voltage MiP capacitor and manufacturing method thereof |
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| CN201410360152.2A CN105448895A (en) | 2014-07-25 | 2014-07-25 | High-voltage MiP capacitor and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448887A (en) * | 2014-08-28 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | High-voltage MiM capacitor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146939A (en) * | 1998-09-18 | 2000-11-14 | Tritech Microelectronics, Ltd. | Metal-polycrystalline silicon-N-well multiple layered capacitor |
| US7312118B2 (en) * | 2002-11-27 | 2007-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US7317221B2 (en) * | 2003-12-04 | 2008-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | High density MIM capacitor structure and fabrication process |
| US20090004809A1 (en) * | 2005-09-12 | 2009-01-01 | International Business Machines Corporation | Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material |
-
2014
- 2014-07-25 CN CN201410360152.2A patent/CN105448895A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146939A (en) * | 1998-09-18 | 2000-11-14 | Tritech Microelectronics, Ltd. | Metal-polycrystalline silicon-N-well multiple layered capacitor |
| US7312118B2 (en) * | 2002-11-27 | 2007-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US7317221B2 (en) * | 2003-12-04 | 2008-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | High density MIM capacitor structure and fabrication process |
| US20090004809A1 (en) * | 2005-09-12 | 2009-01-01 | International Business Machines Corporation | Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448887A (en) * | 2014-08-28 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | High-voltage MiM capacitor |
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