CN105448806A - Semiconductor device and manufacturing method for reducing surface topology and character line stringer residual - Google Patents
Semiconductor device and manufacturing method for reducing surface topology and character line stringer residual Download PDFInfo
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- CN105448806A CN105448806A CN201410430700.4A CN201410430700A CN105448806A CN 105448806 A CN105448806 A CN 105448806A CN 201410430700 A CN201410430700 A CN 201410430700A CN 105448806 A CN105448806 A CN 105448806A
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Abstract
The invention relates to a semiconductor device and a manufacturing method for reducing surface topology and character line stringer residual. According to the method, a substantially flat substrate for subsequent character line formation is prepared by forming a first dielectric filler material in an embedded oxide region and removing the dielectric filler material. The method takes into consideration the production of a semiconductor memory device of which the size is reduced as the character line stringer residual material is reduced.
Description
Technical field
The present invention relates to a kind of structure of semiconductor device and form the method for this semiconductor device, particularly relate to a kind of memory device of improvement and manufacture the method for this kind of memory device.
Background technology
Flash memory device comprises an array arranging the memory cell (memorycell) arranged with hurdle haply.Each memory cell comprises the transistor arrangement of passage having grid, drain electrode, source electrode and be defined between drain electrode and source electrode.The corresponding character line of grid, the bit line of drain electrode or the corresponding memory array of source electrode.The grid of traditional flash memory cell is double-grid structure haply, double-grid structure comprises the grid of a control gate and a suspension joint, wherein the grid of suspension joint is folded between two dielectric layers, to catch carrier (such as electronics), with memory cell of programming.
Semi-conductor industry is more and more towards less and have more the electronic device evolution of performance, as calculation element, communicator and memory device.In order to maintain while the size reducing this kind of device or improve their respective performances, the size of the element in device must be reduced.But problem occurs along with this kind of reduction.
Applicant found to for the manufacture of the traditional handicraft of memory device and the relevant defect of the memory device made thus and problem.For example, about flash memory device, when the size of memory cell is reduced, occur to stop reduction size further also to maintain the performance of memory cell and the problem of respective function simultaneously.The memory cell caused with traditional technique has large surface undulation (topology).This change has in part because the existence in Nei Mai diffusible oxydation district (diffusionoxideregion).When formation and when etching character line to the structure wanted because large surface undulation, so undesired residual materials (residualmaterial) still can be stayed in microgap (crevices) or along edge.This residual materials is called as " longeron " (stringer).When space between the size and/or those character lines of character line reduces, these " longerons " become more serious problem.
Summary of the invention
The object of the invention is to, a kind of manufacture method for manufacturing the useful semiconductor device of memory device is provided, particularly subtract for those manufacture method that undersized semiconductor device can reduce surface undulation and character line longeron remnants, and the semiconductor device be made up of this method is provided.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of manufacture method reducing surface undulation and character line longeron remnants that the present invention proposes, it comprises the following steps: to provide a substrate, a resilient coating and a hard cover curtain layer; Formed in one in a substrate and bury diffusion region; Along substrate deposition one first dielectric fill material; Remove the first dielectric fill material excessive on hard cover curtain layer; Carry out autoregistration patterning (self-alignedpatterning) to form at least one groove in the self-aligned contacts district of semiconductor; Along substrate deposition one second dielectric fill material; Remove the second dielectric fill material excessive on hard cover curtain layer; Remove hard cover curtain layer; And remove the first dielectric fill material.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, is also included in before carrying out autoregistration patterning, be coated with a photoresist layer to semiconductor at least partially.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, is also included in after carrying out autoregistration patterning, removes the step of photoresist layer.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, also can be included in after removing the first dielectric fill material, the step of deposition one first dielectric layer.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, also can comprise the step along the first dielectric layer deposition one first conductive layer.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, also can comprise the step forming one second conductive layer along the first conductive layer.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, also can comprise the step etching at least one character line in the semiconductors.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, wherein can by cloth in substrate plant ion formed in bury diffusion region.In specific embodiment of the present invention, diffusion region can be buried by Doped n-type alloy in a substrate in being formed.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, wherein the step of depositing first dielectric packing material can comprise deposition monoxide as silica.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, wherein in the process removing the first excessive dielectric fill material, the cmp (chemical-mechanicalpolishing) of the planarization causing the first dielectric fill material can be comprised.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, wherein can comprise etching in the process removing the first dielectric fill material.In certain embodiments, can comprise use in the process removing the first dielectric fill material has the etchant of high selectivity to carry out etching semiconductor for silicon.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, wherein the deposition of the first dielectric layer can comprise deposition one oxygen nitrogen oxygen (oxide-nitride-oxide) layer.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, wherein can comprise deposit spathic silicon in the process of the first dielectric layer deposition first conductive layer.
The manufacture method of aforesaid reduction surface undulation and character line longeron remnants, wherein the formation of the second conductive layer can comprise formation one tungsten silicide (tungstensilicide) layer.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of semiconductor device that the present invention proposes, comprising: a substrate; Be arranged in substrate one and bury diffusion region, wherein substrate and in bury the surface undulation (topology) that diffusion region has reduction; And along substrate and in bury diffusion region configuration a character line.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor device, wherein character line comprises the first conductive layer and the second conductive layer.
Aforesaid semiconductor device, burying diffusion region wherein can comprise arsenic ion.
Aforesaid semiconductor device, also comprises one first dielectric layer, and the first dielectric layer can comprise an oxygen nitrogen oxygen layer.
Aforesaid semiconductor device, wherein the first conductive layer can comprise polysilicon.
Aforesaid semiconductor device, wherein the second conductive layer can comprise tungsten silicide.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, semiconductor device of the present invention and the manufacture method reducing surface undulation and character line longeron remnants at least have following advantages and beneficial effect: provided by the inventionly a kind ofly reduced the manufacture method that therefore surface undulation also reduces the semiconductor device of character line longeron problem, and the semiconductor device to be made up of this method, there is the ability of the size reducing flash memory device.It is by after removing the first dielectric fill material, and substrate is in fact flat, and the surface undulation that can reduce allows when not having undesired residual materials or " longeron " is formed, and deposits subsequently and forms character line.
In sum, the invention relates to the manufacture method of a kind of semiconductor device and reduction surface undulation and character line longeron remnants.The method can comprise in combination buries the formation of the first dielectric fill material in zoneofoxidation and removing of this dielectric fill material, with the substrate flat in fact for the preparation of the formation of character line subsequently.The method can consider the production of the semiconductor memory device of the size of the reduction along with the character line longeron surplus material reduced.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 illustrates according to one embodiment of the invention, the profile of the semiconductor after ion cloth is planted.
Fig. 2 illustrates according to one embodiment of the invention, the profile of the semiconductor after depositing first dielectric packing material.
Fig. 3 illustrates according to one embodiment of the invention, removing the profile of the semiconductor after the first excessive dielectric fill material.
Fig. 4 A illustrates according to one embodiment of the invention, the vertical view of the semiconductor after coating photoresist layer.
Fig. 4 B-Fig. 4 C illustrates according to one embodiment of the invention, coating photoresist layer to semiconductor at least partially and carry out autoregistration patterning to form two profiles of the semiconductor after at least one groove in self-aligned contacts district.
Fig. 4 D illustrates according to one embodiment of the invention, the vertical view of the semiconductor after carrying out autoregistration patterning and remove photoresist layer.
Fig. 5 A-Fig. 5 B illustrates according to one embodiment of the invention, two profiles of the semiconductor after deposition second dielectric fill material.
Fig. 6 A-Fig. 6 C illustrates according to one embodiment of the invention, removing regional and the schematic diagram of the semiconductor after the second excessive dielectric fill material.
Fig. 7 A-Fig. 7 C illustrates according to one embodiment of the invention, removing regional and the schematic diagram of the semiconductor after hard cover curtain layer.
Fig. 8 A-Fig. 8 C illustrates according to one embodiment of the invention, removing regional and the schematic diagram of the semiconductor after the first dielectric fill material.
Fig. 9 A-Fig. 9 B illustrates according to one embodiment of the invention, two profiles of the semiconductor after depositing first dielectric layer, the first conductive layer and the second conductive layer.
Figure 10 A-Figure 10 D illustrates according to one embodiment of the invention, the regional of the semiconductor after etching many character lines and schematic diagram.
Figure 11 illustrates according to one embodiment of the invention, the stereogram of a part of semiconductor after etching at least two character lines.
Figure 12 illustrates according to one embodiment of the invention, a kind of process chart of formation method of semiconductor memory device.
Figure 13 illustrates according to one embodiment of the invention, the process chart of the formation method of a kind of semiconductor memory device that the Figure 12 that continues illustrates.
100: semiconductor
110: substrate
120: resilient coating
130: hard cover curtain layer
140: etching region
150: inside bury diffusion region
160: the first dielectric fill material
170: groove
180: self-aligned contacts district
190: photoresist layer
200: the second dielectric fill material
210: the first dielectric layers
220: the first conductive layers
230: the second conductive layers
240: character line
300: semiconductor memory device
310,320,330,340,350,360,370,380,390,400,410,420,430,440,450,500,510,520,530,540,550,560: step
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, the semiconductor device propose foundation the present invention and its embodiment of manufacture method reducing surface undulation and character line longeron remnants, structure, method, step, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can clearly present in the detailed description of following cooperation with reference to graphic preferred embodiment.For convenience of description, below in an example, identical element represents with identical numbering.
Still can the semiconductor device of storage data even if non-volatility memory refers to that Self-memory body removes electrical providing.Non-volatility memory includes but not limited to mask read-only memory (MaskRead-OnlyMemory), read-only memory able to programme (ProgrammableRead-OnlyMemory), erasable programmable read-only memory (ErasableProgrammableRead-OnlyMemory), electronic type erasable programmable read-only memory (ElectricallyErasableProgrammableRead-OnlyMemory) and fast flash memory bank.
As used in this " substrate " can comprise any below or thereon can the material of forming apparatus, circuit, epitaxial layer or semiconductor.Haply, substrate can be positioned at the layer of the basalis below semiconductor device or even forming semiconductor device in order to definition.When not for limited, substrate can comprise one of them or any combination of silicon, doped silicon, germanium, SiGe, semiconducting compound or other semi-conducting materials.
Fig. 1 illustrates according to one embodiment of the invention, the profile of the semiconductor after ion cloth is planted.The semiconductor 100 illustrated comprises substrate 110, resilient coating 120 and a hard cover curtain layer 130.Resilient coating can comprise silica (SiO
2), silicon oxynitride (SiO
xn
y) or its any combination.For example, hard cover curtain layer can be nitride layer, as silicon nitride (Si
3n
4).
Resilient coating can be formed, as chemical vapour deposition technique (ChemicalVaporDeposition, CVD) or spin dielectric medium technique (spin-ondielectricprocessing) by any suitable depositing operation.Hard cover curtain layer can be formed, as CVD or spin dielectric medium technique by any suitable technique.For example, the formation of resilient coating and/or hard cover curtain layer can by technique (enhancedHighAspectRatioProcess, the eHARP) chamber of the reinforcement high-aspect-ratio for chemical vapour deposition (CVD); High density plasma deposition is as high density plasma CVD method (highdensityplasmachemicalvapordeposition); Plasma assisted oxidation (PlasmaEnhancedOxide, PEOX) technique; Use the undoped silicon glass (undopedsiliconglass) as chemical vapour deposition (CVD); Tetraethyl siloxanes (tetraethoxysilane, TEOS) deposits; Or high-temperature oxydation (HotTemperatureOxide, HTO) thin film deposition.
In the embodiment in figure 1, hard cover curtain layer 130 is etched with resilient coating 120 to form etching region 140 in semiconductor 100.In certain embodiments, also can etching substrates 110.In certain embodiments, can etch by wet type or dry-etching.The example of the non-wet etch process for limiting comprises chemical gaseous phase etching (chemicalvaporetching), metal assisted etch (metalassistedetching) and electroless plating etching (electrolessetching).For example, acid etching solution can be used as comprised nitric acid (HNO
3) and/or the mixture of hydrofluoric acid (HF) carry out chemical gaseous phase etching.In certain embodiments, wet etch process can be buffer stage oxide etch (bufferedoxideetch) technique or buffer stage hydrofluoric acid (bufferedhydrofluoricacid) technique.The example of the non-dry etch process for limiting comprises plasma etching, sputter-etch, ionization etching (ionizationetching) and reactive ion etching (reactiveionetching).
Then can plant ion and in being formed, bury diffusion region 150 in etching region 140 by cloth.In the embodiment in figure 1, the step that ion planted by cloth (inside buries diffusion (burieddiffusion, " BD ") cloth plants (implantation, " IMP ")) produce in substrate 110 and bury diffusion region 150 (inside burying diffusion (burieddiffusion, " BD ")).In the specific embodiment of the present invention, diffusion region can be buried by Doped n-type alloy in a substrate in being formed.For example, in certain embodiments, diffusion region can be buried by arsenic doped ion in being formed in a substrate.In certain embodiments, can Doping Phosphorus ion in a substrate.In one embodiment, can adulterate the composition of alloy in a substrate.Hard cover curtain layer 130 can stop the ion diffuse in the region covered by hard cover curtain layer 130.
Bury diffusion region 150 in formation after, the first dielectric fill material can be formed along semiconductor.Fig. 2 illustrates according to one embodiment of the invention, the profile of the semiconductor after depositing first dielectric packing material.In fig. 2, substrate 110 is coated with the first dielectric fill material 160 (in bury diffusion oxide (burieddiffusionoxide, " BDOX ").First dielectric fill material 160 can be silica (SiO
2) and silicon oxynitride (SiO
xn
y) in any one or its any combination.In certain embodiments, the first dielectric fill material can one deck comprising dielectric material or more layer.In the embodiment of fig. 2, the first dielectric fill material fills in fact etching region 140, and buries diffusion region 150 in covering.
The first dielectric fill material can be formed, as CVD or spin dielectric medium technique by any suitable depositing operation.For example, the formation of the first dielectric fill material can by technique (enhancedHighAspectRatioProcess, the eHARP) chamber of the reinforcement high-aspect-ratio for chemical vapour deposition (CVD); High density plasma deposition is as high density plasma CVD method (highdensityplasmachemicalvapordeposition); Plasma assisted oxidation (PlasmaEnhancedOxide, PEOX) technique; Use the undoped silicon glass (undopedsiliconglass) as chemical vapour deposition (CVD); Tetraethyl siloxanes (tetraethoxysilane, TEOS) deposits; Or high-temperature oxydation (HotTemperatureOxide, HTO) thin film deposition.
In some embodiments of the invention, removable the first excessive dielectric fill material.For example, the first dielectric fill material 160 of removable covering hard cover curtain layer 130.In specific embodiment of the present invention, the first dielectric fill material 160 of removable covering hard cover curtain layer 130 is with the surface of planarizing semiconductor.Fig. 3 illustrates according to one embodiment of the invention, removing the profile of the semiconductor after the first excessive dielectric fill material.In certain embodiments, the first dielectric fill material 160 can be removed by cmp.As shown in Figure 3, hard cover curtain layer 130 can be used as a stop etch layers to stop further grinding.In one embodiment, can by grinding and etching step combination or remove the first excessive dielectric fill material 160 by etching step separately.Etch process can be the wet type or dry-etching that previous definition crosses.In certain embodiments, the first excessive dielectric fill material at least partially can be removed by optionally etch process, wherein preferably remove the first dielectric fill material.
In certain embodiments, may want to form groove in the region of semiconductor.In certain embodiments, multiple groove can be formed.In one embodiment of this invention, photoetching process (photolithography) and autoregistration patterning can be used to form one or more groove.Photoetching process or photolithography (opticallithography) comprise expose and develop photosensitive polymer or photoresistance to form three-dimensional pattern on substrate.General sequence for photoetching process can comprise the baking after preparing substrate, coating photoresistance, prebake, exposure, exposure, development and rear baking (post-baking).Haply, the uniform thickness set up through the photoresistance of substrate may be important.Alternatively, the layer of bottom anti-reflective plated film (BottomAnti-reflectiveCoating, BARC) can be coated with to substrate before coating photoresist layer.Before coating photoresistance, adhesion promoter (adhesionpromoter) can be coated with to substrate.
According to the specific embodiment of the present invention, autoregistration patterning can be used to form self-aligned contacts district in the semiconductors.Fig. 4 A-Fig. 4 D illustrates according to one embodiment of the invention, coating photoresist layer to semiconductor at least partially and carry out autoregistration patterning to form regional and the schematic diagram of the semiconductor in the process of at least one groove in self-aligned contacts district.Particularly, Fig. 4 A illustrates according to one embodiment of the invention, the vertical view of the semiconductor after coating photoresist layer.Fig. 4 B-Fig. 4 C illustrates according to one embodiment of the invention, coating photoresist layer to semiconductor at least partially and carry out autoregistration patterning to form two profiles of the semiconductor after at least one groove in self-aligned contacts district.Fig. 4 D illustrates according to one embodiment of the invention, the vertical view of the semiconductor after carrying out autoregistration patterning and remove photoresist layer.
In the embodiment of Fig. 4 A, coating photoresist layer 190 to semiconductor 100.This photoresistance can experience the baking after prebake, exposure, exposure, development and rear step of drying.After process, only have the specific part wanted of semiconductor still cover by photoresist layer.In certain embodiments, only the semiconductor of some is covered by photoresist layer, but in other examples, multiple regions of semiconductor are covered by photoresist layer.Still will be avoided etching subsequently by the part substrate that photoresist layer covers, ion cloth plants, and/or other technology.
In the specific embodiment of the present invention, can the not capped part of etching semiconductor to form groove 170 in substrate 110.After the etching, removable photoresistance, leaves the self-aligned contacts district in semiconductor.Fig. 4 D is the self-aligned contacts district 180 illustrated in semiconductor 100.Self-aligned contacts district 180 comprises the groove 170 burying diffusion region 150 and the first dielectric fill material 160 in vicinity.
Fig. 4 B is the profile illustrating in autoregistration patterning process the part semiconductor still covered by photoresist layer.As shown in Figure 4 B, not etching substrates 110 to form groove.Fig. 4 C illustrates region that etching is not capped to form groove 170.In the embodiment of Fig. 4 C, form groove 170 at the interior either side burying diffusion region 150.Can etch by any suitable etch process, as the wet type that previously described or dry-etching.
In certain embodiments, the second dielectric fill material 200 to semiconductor can be then coated with.Fig. 5 A-Fig. 5 B illustrates according to one embodiment of the invention, two profiles of the semiconductor after deposition second dielectric fill material.
Fig. 5 A is the profile illustrating in autoregistration patterning process the region still covered by photoresist layer 190.Fig. 5 B is the profile in the self-aligned contacts district illustrating semiconductor.
In certain embodiments, the second dielectric fill material 200 covered substrate is coated with at least partially.In the embodiment shown in Fig. 5 B, the second dielectric fill material 200 fills the groove 170 in substrate 110.Second dielectric fill material 200 can be silica (SiO2) and any one in silicon oxynitride (SiOxNy) or its any combination.
The second dielectric fill material can be coated with by any suitable depositing operation.For example, can by chemical vapor deposition method as eHARP (strengthening the technique of high-aspect-ratio) or high density plasma CVD method be coated with the second dielectric fill material.In certain embodiments, the second dielectric fill material can be coated with by spin dielectric medium technique.For example, can by technique (eHARP) chamber of the reinforcement high-aspect-ratio for chemical vapour deposition (CVD); High density plasma deposition is as high density plasma CVD method; Plasma assisted oxidation (PEOX) technique; Use the undoped silicon glass as chemical vapour deposition (CVD); Tetraethyl siloxanes (TEOS) deposits; Or high-temperature oxydation (HTO) thin film deposition forms the second dielectric fill material.
In certain embodiments, removable the second excessive dielectric fill material.For example, the second dielectric fill material 200 of removable covering hard cover curtain layer 130.In specific embodiment of the present invention, the second dielectric fill material 200 of removable covering hard cover curtain layer 130 is with the surface of planarizing semiconductor.In certain embodiments, the second dielectric fill material 200 can be removed by cmp, etching or its any combination.Fig. 6 A-Fig. 6 C illustrates according to one embodiment of the invention, removing regional and the schematic diagram of the semiconductor after the second excessive dielectric fill material.
More specifically, Fig. 6 A illustrates in autoregistration patterning process, the profile in the region still covered by photoresist layer of semiconductor 100.As shown in Figure 6A, consider the surface of planarization, hard cover curtain layer 130 stops the first dielectric fill material to be removed further.
Fig. 6 B is the profile in the self-aligned contacts district 180 illustrating semiconductor 100.Fig. 6 C illustrates according to one embodiment of the invention, removing the vertical view of the semiconductor 100 after the second excessive dielectric fill material 200.Fig. 6 C shows the second dielectric fill material 200 and the first dielectric fill material 160 in the self-aligned contacts district 180 of semiconductor 100.
According to specific embodiment, then removable hard cover curtain layer 130.Fig. 7 A-Fig. 7 C illustrates according to one embodiment of the invention, removing regional and the schematic diagram of the semiconductor after hard cover curtain layer.
Fig. 7 A illustrates in autoregistration patterning process, the profile in the region still covered by photoresist layer.Fig. 7 B is the profile in the self-aligned contacts district 180 illustrating semiconductor 100.Fig. 7 C illustrates the vertical view at the semiconductor 100 removed after hard cover curtain layer 130.
As previously mentioned, hard cover curtain layer can be any suitable material as silicon nitride, and this material stops the ion diffuse in overlay area.Consider the surface of planarization, hard cover curtain layer also can stop the first dielectric fill material further to be ground.Can by any suitable removing method as cmp, etching or its any combination remove hard cover curtain layer.
In specific embodiment of the present invention, then removable first dielectric fill material.In certain embodiments, the surface undulation that the first dielectric fill material provides planarization is in fact removed.In one embodiment, resilient coating can be removed together along with the first dielectric fill material.Fig. 8 A-Fig. 8 C illustrates according to one embodiment of the invention, removing regional and the schematic diagram of the semiconductor after the first dielectric fill material and resilient coating.
Especially, Fig. 8 A illustrates in autoregistration patterning process, the profile in the region still covered by photoresist layer.Fig. 8 B is the profile in the self-aligned contacts district 180 illustrating semiconductor 100.Fig. 8 C illustrates according to embodiments of the invention, removing the vertical view of the semiconductor 100 after the first dielectric fill material 160 and resilient coating 120.
The first dielectric fill material can be removed by any suitable method.For example, by etching as Wet-type etching or dry-etching, or the first dielectric fill material can be removed by cmp.In certain embodiments, the first dielectric fill material can be removed by etching and cmp.In certain embodiments, the first dielectric fill material can be removed by optionally etch process.For example, comprise in the embodiment of silica in the first dielectric fill material, etch process can have the high selectivity to silicon.
In certain embodiments, resilient coating 120 can be removed together along with the first dielectric fill material 160.In other examples, partly can remove resilient coating together along with the first dielectric fill material, and fully remove resilient coating by technique subsequently.Can by any suitable removing method as cmp, etching or its any combination remove resilient coating.
In the embodiment of Fig. 8 A, remove the first dielectric fill material and resilient coating causes surface undulation flat in fact.In flash memory device, when the size of the memory cell of flash memory device reduces, occur stop further reduction size and maintain the performance of memory cell and the problem of respective function simultaneously.Traditional technique causes surface undulation large on memory cell.This change has in part because the existence in Nei Mai diffusible oxydation district.When being formed and etching character line to the structure wanted, because large surface undulation, so undesired residual materials still can be stayed in microgap (crevices) or along edge.This residual materials is called as " longeron " (stringer).
The invention provides one and reduce surface undulation, and therefore reduce the manufacture method of the semiconductor device of character line longeron problem, and the semiconductor memory device be made up of these class methods.The invention provides the ability of the size reducing flash memory device.For example, in the embodiment of Fig. 8 A, after removing the first dielectric fill material, substrate is in fact flat.When not for being limited to theory, the surface undulation of reduction allows when not having undesired residual materials or " longeron " is formed, and deposits subsequently and forms character line.
In specific embodiment of the present invention, removable first dielectric layer.In certain embodiments, then removable first conductive layer and the second conductive layer.Fig. 9 A-Fig. 9 B illustrates according to one embodiment of the invention, two profiles of the semiconductor after depositing first dielectric layer, the first conductive layer and the second conductive layer.These layers can be formed, as CVD or rotary coating by any suitable depositing operation.For example, can by technique (eHARP) chamber of the reinforcement high-aspect-ratio for chemical vapour deposition (CVD); High density plasma deposition is as high density plasma CVD method; Plasma assisted oxidation (PEOX) technique; Use the undoped silicon glass as chemical vapour deposition (CVD); Tetraethyl siloxanes (TEOS) deposits; Or high-temperature oxydation (HTO) thin film deposition forms the first dielectric layer 210.
First dielectric layer 210 can be any suitable dielectric medium, as silica (SiO
2), silicon nitride (Si
3n
4), silicon oxynitride (SiO
xn
y) or its any combination.In the embodiment that Fig. 9 A illustrates, the first dielectric layer comprises oxygen nitrogen oxygen (ONO) layer.First conductive layer 220 can comprise any suitable electric conducting material as polysilicon.In the embodiment that Fig. 9 A illustrates, the first conductive layer 220 comprises polysilicon.Second conductive layer 230 can comprise any suitable electric conducting material as metal silicide (metalsilicide).For example, the second conductive layer can comprise tantalum silicide, titanium silicide, cobalt silicide, nickel silicide, Platinum Silicide, tungsten silicide or its any combination.In the embodiment that Fig. 9 A illustrates, the second conductive layer 230 comprises tungsten silicide.
In specific embodiment of the present invention, one or more character line can be etched in the semiconductors.Figure 10 A-Figure 10 D illustrates according to one embodiment of the invention, the regional of the semiconductor after etching many character lines and schematic diagram.
Especially, Figure 10 A illustrates still to be covered by photoresist layer in autoregistration patterning process and to comprise the profile in the region of character line.Figure 10 B illustrates still to be covered by photoresist layer in autoregistration patterning process and not comprise the profile in the region of character line after the etching.Figure 10 C is the profile in the self-aligned contacts district of the semiconductor illustrated after etching character line.
Figure 10 D illustrates according to one embodiment of the invention, the vertical view of the semiconductor after etching character line.Character line 240 can be etched, as wet type or dry-etching by any suitable technique.In the embodiment of Figure 10 D, etching character line 240 buries diffusion region 150 perpendicular to interior.
Figure 11 illustrates according to one embodiment of the invention, the stereogram of a part of semiconductor after etching at least two character lines.In the embodiment in figure 11, etch the character line 240 comprising the first conductive layer 220 and the second conductive layer 230 and bury diffusion region 150 perpendicular to interior.
Figure 12 illustrates according to one embodiment of the invention, a kind of process chart of formation method of semiconductor memory device.In an exemplary embodiment of the invention, a kind of method forming semiconductor memory device comprises the step 310 providing substrate, resilient coating and hard cover curtain layer.Method shown in Figure 12, also comprise bury diffusion region in being formed in a substrate step 320, along substrate deposition first dielectric fill material step 330 and remove the step 340 of the first excessive dielectric fill material on hard cover curtain layer.In certain embodiments, formed in a substrate in bury diffusion region step can comprise Doped n-type alloy in a substrate, as shown in selectable step 500.In certain embodiments, the step along substrate deposition first dielectric fill material can comprise cvd silicon oxide, as shown in selectable step 510.In certain embodiments, the step removing the first excessive dielectric fill material on hard cover curtain layer can comprise cmp first dielectric fill material, as shown in selectable step 520.The embodiment be illustrated in Figure 12 also comprise coating photoresist layer to semiconductor step 350 at least partially, carry out autoregistration patterning to form the step 360 of at least one groove and remove the step 370 of photoresist layer in the self-aligned contacts district of semiconductor.Method shown in Figure 12 also comprises the step 380 along substrate deposition second dielectric fill material.
Figure 13 illustrates according to one embodiment of the invention, the process chart of the formation method of a kind of semiconductor memory device that the Figure 12 that continues illustrates.In one exemplary embodiment of the present invention shown in Figure 13, a kind of formation method of semiconductor memory device also comprise the second excessive dielectric fill material removed on hard cover curtain layer step 390, remove the step 400 of hard cover curtain layer and remove the step 410 of the first dielectric fill material.In certain embodiments, the step removing the first dielectric fill material can comprise using has the etchant of high selectivity to carry out etching semiconductor for silicon, as selectable step 530 illustrate.Method shown in Figure 13 also comprises the step 420 of depositing first dielectric layer.In certain embodiments, the step of depositing first dielectric layer can comprise deposition oxygen nitrogen oxygen layer, as selectable step 540 illustrate.In addition, the character line formed in this embodiment is formed by the step 430 along the first dielectric layer deposition first conductive layer, the step 440 along the first conductive layer deposition second conductive layer and the step 450 that etches at least one character line in the semiconductors.In certain embodiments, the step along the first dielectric layer deposition first conductive layer can comprise along the first dielectric layer deposition polysilicon, as selectable step 550 illustrate.In certain embodiments, the step along the first conductive layer deposition second conductive layer can comprise along the first conductive layer deposition tungsten silicide, as selectable step 560 illustrate.Method of the present invention can comprise the various combination of the step be illustrated in Figure 12 and Figure 13.
The present invention can be applicable to any suitable semiconductor manufacturing.For example, method of the present invention can be applicable to manufacture any nonvolatile memory device.For example, this method can be applicable to manufacture Nbit memory cell.
An aspect of of the present present invention provides a kind of semiconductor with memory cell, uses the technique or method that have a semiconductor of memory cell for the manufacture of of the present invention to manufacture this semiconductor.In the present invention's other embodiments specific, any method for manufacturing semiconductor device that this describes can be used in.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the method and technology contents that can utilize above-mentioned announcement are made a little change or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (20)
1. reduce a manufacture method of surface undulation and character line longeron remnants, it is characterized in that it comprises the following steps:
One substrate, a resilient coating and a hard cover curtain layer are provided;
Formed in one in this substrate and bury diffusion region;
Along this substrate deposition one first dielectric fill material;
Remove this excessive first dielectric fill material on this hard cover curtain layer;
Carry out autoregistration patterning to form at least one groove in a self-aligned contacts district of semiconductor;
Along this substrate deposition one second dielectric fill material;
Remove this excessive second dielectric fill material on this hard cover curtain layer;
Remove this hard cover curtain layer; And
Remove this first dielectric fill material.
2. the manufacture method of reduction surface undulation according to claim 1 and character line longeron remnants, it is characterized in that its be also included in carry out autoregistration patterning before be coated with a photoresist layer to this semiconductor at least partially.
3. the manufacture method of reduction surface undulation according to claim 2 and character line longeron remnants, it is characterized in that its be also included in carry out autoregistration patterning after remove this photoresist layer.
4. the manufacture method of reduction surface undulation according to claim 1 and character line longeron remnants, it is characterized in that its be also included in remove this first dielectric fill material after deposition one first dielectric layer.
5. the manufacture method of reduction surface undulation according to claim 4 and character line longeron remnants, is characterized in that it also comprises along this first dielectric layer deposition one first conductive layer.
6. the manufacture method of reduction surface undulation according to claim 5 and character line longeron remnants, is characterized in that it also comprises along this first conductive layer deposition one second conductive layer.
7. the manufacture method of reduction surface undulation according to claim 6 and character line longeron remnants, is characterized in that it is also included in this semiconductor and etches at least one character line.
8. the manufacture method of reduction surface undulation according to claim 1 and character line longeron remnants, is characterized in that wherein this interior diffusion region of burying formed by Doped n-type alloy in this substrate.
9. the manufacture method of reduction surface undulation according to claim 1 and character line longeron remnants, is characterized in that wherein comprising cvd silicon oxide in the step of this first dielectric fill material of deposition.
10. the manufacture method of reduction surface undulation according to claim 1 and character line longeron remnants, is characterized in that wherein comprising cmp with this first dielectric fill material of planarization in the step removing this excessive the first dielectric fill material.
The manufacture method of 11. reduction surface undulations according to claim 1 and character line longeron remnants, is characterized in that wherein comprising this semiconductor of an etchant etching using and silicon is had to a high selectivity when removing this first dielectric fill material.
The manufacture method of 12. reduction surface undulations according to claim 4 and character line longeron remnants, is characterized in that wherein comprising deposition one oxygen nitrogen oxygen layer in the step of this first dielectric layer of deposition.
The manufacture method of 13. reduction surface undulations according to claim 5 and character line longeron remnants, is characterized in that wherein comprising deposit spathic silicon along the step of this this first conductive layer of the first dielectric layer deposition.
The manufacture method of 14. reduction surface undulations according to claim 6 and character line longeron remnants, is characterized in that wherein comprising deposition tungsten silicide in the step of this second conductive layer of deposition.
15. 1 kinds of semiconductor devices, is characterized in that it comprises:
One substrate;
Bury diffusion region in one, be arranged in this substrate, wherein this substrate and this interiorly bury the surface undulation that diffusion region has reduction; And
One character line, configures along this substrate and this interior diffusion region of burying.
16. semiconductor devices according to claim 15, is characterized in that wherein this character line comprises one first conductive layer and one second conductive layer.
17. semiconductor devices according to claim 15, is characterized in that wherein this interior diffusion region of burying comprises arsenic ion.
18. semiconductor devices according to claim 16, is characterized in that it also comprises one first dielectric layer, and it comprises an oxygen nitrogen oxygen layer.
19. semiconductor devices according to claim 16, is characterized in that wherein this first conductive layer comprises polysilicon.
20. semiconductor devices according to claim 16, is characterized in that wherein this second conductive layer comprises tungsten silicide.
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| US20070117301A1 (en) * | 2005-11-18 | 2007-05-24 | Macronix International Co., Ltd. | Method for forming non-volatile memory with inlaid floating gate |
| US20080128774A1 (en) * | 2006-11-02 | 2008-06-05 | Rustom Irani | Forming silicon trench isolation (STI) in semiconductor devices self-aligned to diffusion |
| CN101373774A (en) * | 2007-08-23 | 2009-02-25 | 三星电子株式会社 | Integrated circuit memory devices and methods of fabricating same |
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| TW469536B (en) * | 2000-12-13 | 2001-12-21 | Macronix Int Co Ltd | Method for forming a structure with inclined sidewall |
| US20070117301A1 (en) * | 2005-11-18 | 2007-05-24 | Macronix International Co., Ltd. | Method for forming non-volatile memory with inlaid floating gate |
| US20080128774A1 (en) * | 2006-11-02 | 2008-06-05 | Rustom Irani | Forming silicon trench isolation (STI) in semiconductor devices self-aligned to diffusion |
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