CN105446410A - Method for calibrating low-dropout linear voltage stabilizer - Google Patents
Method for calibrating low-dropout linear voltage stabilizer Download PDFInfo
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- CN105446410A CN105446410A CN201510848482.0A CN201510848482A CN105446410A CN 105446410 A CN105446410 A CN 105446410A CN 201510848482 A CN201510848482 A CN 201510848482A CN 105446410 A CN105446410 A CN 105446410A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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Abstract
The invention discloses a method for calibrating a low-dropout linear voltage stabilizer. According to the method, firstly, when an LDO trimming value is stored in flash, an LDO secret key is stored at the same time; after power-on, the LDO secret key is read from flash, and whether LDO output voltage is adjusted or not is determined according to whether the read LDO secret key is correct or not; when the read LDO secret key is incorrect, the LDO output voltage is adjusted into LDO_VDD through the dichotomy; when the correct LDO secret key is read, it is considered that the LDO output voltage can support normal reading of flash, then the LDO trimming value stored in flash is read, and the LDO output voltage is adjusted into a voltage center value; normal work starts. By means of the method, a chip with initial LDO output voltage beyond the voltage range required by normal work of flash can work normally, the chip yield can also be increased, and cost is reduced.
Description
Technical field
The invention belongs to the technical field of single-chip microcomputer, particularly a kind of calibration steps of low pressure difference linear voltage regulator.
Background technology
Along with the raising of market application to the erasable number of times demand of storer, flash etc. support that the storer repeatedly wiped is used widely at single-chip microcomputer.Because flash is higher to voltage request, therefore select low pressure difference linear voltage regulator LDO (lowdropoutregulator) for its power supply be a kind of commonplace method.
Due to the deviation of manufacturing process itself, cause same electrical to depress in each chips, the voltage deviation central value amplitude that LDO supplies flash is different, and part departs from larger chip and normally to work required voltage scope and cisco unity malfunction because exceeding flash.Therefore, LDO is corrected to flash normal working voltage central value by the normal method of trimming calibration that adopts, and trimming value is stored in advance in certain address of flash.Read the trimming value left in Flash after powering on to correct LDO, and then enter normal work.By the method, can reduce the chip that the reasons such as process deviation cause cannot normally work, and improves the yield of chip.But after system electrification, if LDO actual power voltage deviation flash normal working voltage scope, correctly cannot read the trimming value left in flash, thus also cannot normally work.
As patented claim 201310382976.5 discloses a kind of calibration steps being applied to the D/A of two points modulation, this calibration steps comprises: the span obtaining the control signal for calibrating D/A gain; Span described in dichotomy process is utilized also therefrom to determine the calibration output valve of described control signal.Because this application adopts the mode of dichotomy to determine the value of the control signal of calibrating D/A gain, therefore greatly can shorten the alignment time of D/A and improve the calibration efficiency of D/A.
Summary of the invention
Therefore be to provide the method for a kind of low pressure difference linear voltage regulator calibration, the method can make LDO initial output voltage drop on the flash outer segment chip of required voltage scope that normally works can normally to work, and does not become waste paper primary order of the present invention.
Be a kind of method providing low pressure difference linear voltage regulator to calibrate, this low-voltage detection circuit can improve chip yield, reduces costs another order of the present invention.
For achieving the above object, technical scheme of the present invention is:
A method for low pressure difference linear voltage regulator calibration, the method comprising the steps of has:
First 101. when storing in LDOtrimming value to flash, stores a LDO key another address to flash simultaneously;
102. power on after, first LDO hardware Trimming module reads LDO key from flash, and whether correctly determines whether adjustment LDO output voltage according to read LDO key;
The 103. LDO keys that ought read are incorrect, then by dichotomy adjustment LDO output voltage LDO_VDD, treat that LDO_VDD stablizes, again read LDO key;
104. after reading correct LDO key, thinks that current LDO output voltage can support that flash normally reads, and next reads the LDOtrimming value left in the middle of flash, LDO output voltage is adjusted to voltage center's value;
105. enter normal work.
Described LDO key can be known arbitrary sequence.
In step 102, the Trimming value corresponding ideal state LDO output voltage central value of acquiescence when powering on.
Further, described method is specially:
201, after powering to single-chip microcomputer, voltage reaches operating voltage, and LDO starts working.
202, the acquiescence Trimming value that LDO uses LDO hardware Trimming module to transmit exports " 1. LDO gives tacit consent to output voltage " LDO_VDD.
203, LDO hardware Trimming module reads the key be stored in Flash after LDO_VDD stablizes.
204, LDO hardware Trimming module judges that whether the key read is correct.
205, key is incorrect, then LDO hardware Trimming module changes and exports to the Trimming value of LDO module, makes it export the hardware corrected rear output voltage of LDO 2. successively " the hardware corrected rear output voltage of LDO 3. " the hardware corrected rear output voltage of LDO 4. " the hardware corrected rear output voltage of LDO 5. ".Jump to and perform step 203.
206, key is correct.Then read the LDOTrimming value be stored in Flash.
207, the LDOTrimming value read is sent to LDO.
208, after LDO_VDD is stable, normal work is entered.
Thus, the present invention has following technique effect:
1, LDO initial output voltage can be made to drop on the flash outer segment chip of required voltage scope that normally works can normally work, and not become waste paper.
2, improve chip yield, reduce costs.
Accompanying drawing explanation
Fig. 1 is the hardware structure diagram that the present invention implements.
Fig. 2 is the calibrating principle figure that the present invention implements.
Fig. 3 is the calibration schematic diagram of several situations that the present invention implements.
Fig. 4 is the control procedure figure that the present invention implements.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Shown in Fig. 1, implement by the present invention included by LDO hardware calibration hardware circuit.Mainly comprise LDO, LDO hardware Trimming module and storage unit flash.The function of each circuit unit is as follows:
LDO: after meeting supply voltage VDD, the trimming value sent according to LDO hardware Trimming module produces the LDO output voltage LDO_VDD for Flash.
LDO hardware Trimming module: read the LDO key, the LDOtrimming value that are stored in Flash, provide LDOTrimming value to LDO, thus change LDO_VDD.
Storage unit Flash: the LDOtrimming value corresponding to center voltage be used for depositing LDO key, making LDO_VDD equal Flash normally to work.
Main implementation is as follows:
First 101. when storing in LDOtrimming value to flash, stores a LDO key to another address simultaneously.LDO key can be known arbitrary sequence.
102. power on after, first LDO hardware Trimming module reads LDO key, and whether correctly determines whether adjustment LDO output voltage according to read LDO key.
The 103. LDO keys that ought read are incorrect, then by dichotomy adjustment LDO output voltage LDO_VDD, treat that LDO_VDD stablizes, again read LDO key.The Trimming value corresponding ideal state LDO output voltage central value of acquiescence when powering on.
104. after reading correct LDO key, thinks that current LDO output voltage can support that flash normally reads, and next reads the LDOtrimming value left in the middle of flash, LDO output voltage is adjusted to voltage center's value.Normal work is entered after voltage stabilization.
The principle of described dichotomy Trimming as shown in Figure 2.
After supply voltage VDD draws high, the acquiescence Trimming value that LDO can use LDO hardware Trimming module to provide produces LDO_VDD for FLASH, i.e. " 1. LDO gives tacit consent to output voltage " voltage in accompanying drawing 2; When this LDO_VDD voltage is not in Flash operating voltage range, then the LDO key that reads from Flash of LDO hardware Trimming module is incorrect.
After LDO hardware Trimming module judges that the LDO key that reads is incorrect, export " the hardware corrected rear output voltage of LDO 2. " in accompanying drawing 2 corresponding LDOTrimming value to LDO, to produce " the hardware corrected rear output voltage of LDO 2. " voltage LDO_VDD for Flash; After voltage stabilization, LDO hardware Trimming module reads LDO key again.
As incorrect in read key, then adjust Trimming value successively and make LDO produce the corresponding LDO_VDD continuation of " the hardware corrected rear output voltage of LDO is 3. " " the hardware corrected rear output voltage of LDO is 4. " " the hardware corrected rear output voltage of LDO is 5. " in accompanying drawing 2 reading." the hardware corrected rear output voltage of LDO 4. " " the hardware corrected rear output voltage of LDO 5. " respectively corresponding " 1. LDO gives tacit consent to output voltage " arrives 1/2nd voltages of " the hardware corrected rear output voltage of LDO 2. " and " the hardware corrected rear output voltage of LDO 3. ".
Pass through said method.The chip that " LDO give tacit consent to output voltage 1. " LDO_VDD is not in Flash normal working voltage claimed range can be calibrated, make it normally work.
It is the situation of several calibrations wherein in Fig. 3.
Concrete implementation procedure as shown in Figure 4.
201, after powering to single-chip microcomputer, voltage reaches operating voltage, and LDO starts working.
202, the acquiescence Trimming value that LDO uses LDO hardware Trimming module to transmit exports " 1. LDO gives tacit consent to output voltage " LDO_VDD.
203, LDO hardware Trimming module reads the key be stored in Flash after LDO_VDD stablizes.
204, LDO hardware Trimming module judges that whether the key read is correct.
205, key is incorrect, then LDO hardware Trimming module changes and exports to the Trimming value of LDO module, makes it export the hardware corrected rear output voltage of LDO 2. successively " the hardware corrected rear output voltage of LDO 3. " the hardware corrected rear output voltage of LDO 4. " the hardware corrected rear output voltage of LDO 5. ".Jump to and perform step 203.
206, key is correct.Then read the LDOTrimming value be stored in Flash.
207, the LDOTrimming value read is sent to LDO.
208, after LDO_VDD is stable, normal work is entered.
By the present invention, LDO initial output voltage can be made to drop on the flash outer segment chip of required voltage scope that normally works can normally work, and does not become waste paper.Can also chip yield be improved simultaneously, reduce costs.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a method for low pressure difference linear voltage regulator calibration, the method comprising the steps of has:
First 101. when storing in LDOtrimming value to flash, stores a LDO key another address to flash simultaneously;
102. power on after, first LDO hardware Trimming module reads LDO key from flash, and whether correctly determines whether adjustment LDO output voltage according to read LDO key;
The 103. LDO keys that ought read are incorrect, then by dichotomy adjustment LDO output voltage LDO_VDD, treat that LDO_VDD stablizes, again read LDO key;
104. after reading correct LDO key, thinks that current LDO output voltage can support that flash normally reads, and next reads the LDOtrimming value left in the middle of flash, LDO output voltage is adjusted to voltage center's value;
105. enter normal work.
2. the method for low pressure difference linear voltage regulator calibration as claimed in claim 1, is characterized in that described LDO key can for known arbitrary sequence.
3. the method for low pressure difference linear voltage regulator calibration as claimed in claim 1, is characterized in that in described step 102, the Trimming value corresponding ideal state LDO output voltage central value of acquiescence when powering on.
4. the method for low pressure difference linear voltage regulator calibration as claimed in claim 1, is characterized in that described method is specially:
201, after powering to single-chip microcomputer, voltage reaches operating voltage, and LDO starts working;
202, the acquiescence Trimming value that LDO uses LDO hardware Trimming module to transmit exports " 1. LDO gives tacit consent to output voltage " LDO_VDD;
203, LDO hardware Trimming module reads the key be stored in Flash after LDO_VDD stablizes;
204, LDO hardware Trimming module judges that whether the key read is correct;
205, key is incorrect, then LDO hardware Trimming module changes the Trimming value exporting to LDO module, make it export the hardware corrected rear output voltage of LDO 2. successively " the hardware corrected rear output voltage of LDO 3. " the hardware corrected rear output voltage of LDO 4. " the hardware corrected rear output voltage of LDO 5. ", then jump to perform step 203;
206, key is correct, then read the LDOTrimming value be stored in Flash;
207, the LDOTrimming value read is sent to LDO;
208, after LDO_VDD is stable, normal work is entered.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510848482.0A CN105446410B (en) | 2015-11-27 | 2015-11-27 | Method for calibrating low-dropout linear voltage stabilizer |
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| CN201510848482.0A CN105446410B (en) | 2015-11-27 | 2015-11-27 | Method for calibrating low-dropout linear voltage stabilizer |
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| CN105446410A true CN105446410A (en) | 2016-03-30 |
| CN105446410B CN105446410B (en) | 2017-03-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115427A (en) * | 2021-11-26 | 2022-03-01 | 中国电子科技集团公司第五十八研究所 | LDO (Low dropout regulator) calibration method based on EFLASH (extended edge laser absorption Spectroscopy) loading in SoC (System on chip) |
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| CN202795112U (en) * | 2012-09-11 | 2013-03-13 | 合肥华恒电子科技有限责任公司 | Constant-current square wave generating circuit |
| CN103076834A (en) * | 2012-12-28 | 2013-05-01 | 四川和芯微电子股份有限公司 | Resistor calibrating circuit |
| US8536844B1 (en) * | 2012-03-15 | 2013-09-17 | Texas Instruments Incorporated | Self-calibrating, stable LDO regulator |
| CN104063000A (en) * | 2013-03-22 | 2014-09-24 | 国民技术股份有限公司 | System for configuring output current of low-drop-out regulator and chip |
| CN104679084A (en) * | 2013-11-27 | 2015-06-03 | 展讯通信（上海）有限公司 | Voltage correction circuit and low-dropout linear regulator system |
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2015
- 2015-11-27 CN CN201510848482.0A patent/CN105446410B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8536844B1 (en) * | 2012-03-15 | 2013-09-17 | Texas Instruments Incorporated | Self-calibrating, stable LDO regulator |
| CN202795112U (en) * | 2012-09-11 | 2013-03-13 | 合肥华恒电子科技有限责任公司 | Constant-current square wave generating circuit |
| CN103076834A (en) * | 2012-12-28 | 2013-05-01 | 四川和芯微电子股份有限公司 | Resistor calibrating circuit |
| CN104063000A (en) * | 2013-03-22 | 2014-09-24 | 国民技术股份有限公司 | System for configuring output current of low-drop-out regulator and chip |
| CN104679084A (en) * | 2013-11-27 | 2015-06-03 | 展讯通信（上海）有限公司 | Voltage correction circuit and low-dropout linear regulator system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115427A (en) * | 2021-11-26 | 2022-03-01 | 中国电子科技集团公司第五十八研究所 | LDO (Low dropout regulator) calibration method based on EFLASH (extended edge laser absorption Spectroscopy) loading in SoC (System on chip) |
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Address after: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee after: Chipsea Technology (Shenzhen) Co., Ltd. Address before: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee before: Xinhai Science and Technology Co., Ltd., Shenzhen City |
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