CN1054442C - A high speed ladder instruction process system for a programmable logic controller - Google Patents
A high speed ladder instruction process system for a programmable logic controller Download PDFInfo
- Publication number
- CN1054442C CN1054442C CN93107851A CN93107851A CN1054442C CN 1054442 C CN1054442 C CN 1054442C CN 93107851 A CN93107851 A CN 93107851A CN 93107851 A CN93107851 A CN 93107851A CN 1054442 C CN1054442 C CN 1054442C
- Authority
- CN
- China
- Prior art keywords
- data
- memory
- instruction
- bus
- user
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/056—Programming the PLC
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
Abstract
A high speed instruction process system for a programmable logic controller having a first memory for storing one or more user instructions, which each instruction corresponds to a different process cycle, circuitry for processing the user instruction, a second memory for storing one or more user data, which each data corresponds to a different process cycle, circuitry for accessing a stored user data, and circuitry for processing an accessed user data in accordance with a processed user instruction, wherein the user data corresponding to a process cycle is accessed at the substantially same time as the user instruction corresponding to a different process cycle is processed.
Description
The present invention relates to a kind of high speed ladder instruction process system that is used for programmable logic controller (PLC).
In the programmable logic controller (PLC) (" PLC ") of routine, each trapezoidal instruction is to utilize an intrinsic routine processes in CPU (central processing unit) (CPU).Among the conventional PLC in having a unibus system structure, the processing of each instruction needs several microseconds (μ S), and so the Chang instruction process time brings adverse influence for total processing time of system.Particularly, when in this conventional PLC, using an auxiliary circuit, then need a plurality of bus cycles to handle each instruction, thereby this system just need a long total processing time.
The objective of the invention is to reduce to be used for the processing time of the trapezoidal instruction of a programmable logic controller (PLC).In order to achieve this end and according to purposes of the present invention, as if general description is such here, programmable logic controller (PLC) of the present invention has used a kind of instruction process system that improves programmable logic controller (PLC) instruction process speed, described programmable logic controller (PLC) comprises CPU (central processing unit) (CPU) (10), the address decoder (20) that is connected with CPU through first address bus, the memory (150 that is connected with CPU through first data bus, 160), described instruction process system, first bidirectional buffer (60) that first bus system that constitutes via described first address bus and first data bus is connected with CPU, second bidirectional buffer (100) that is connected with CPU through this first bus system, described instruction process system is characterised in that, it comprises: programmable counter (30) is used for the address that produces each user instruction that will carry out in response to clock signal and its input signal; First traffic pilot (40), an one input end is connected with CPU through first address bus, and another input end is connected to described programmable counter, and being used for provides its output to second address bus; User's memory (50) is connected with described first traffic pilot through described second address bus, is used to store the instruction in different disposal cycle and the instruction of being stored is offered second data bus; Execution command memory (70) is connected with user's memory through described second data bus, is used for the execution command that temporary transient storage is read from user's memory with designated order; Second traffic pilot (80), an one input end is connected with CPU, and another input end is connected with described execution command memory through instruction bus, is used for providing its output to the three-address bus; Data memory (90), be connected with described second traffic pilot through described three-address bus, and be connected with described second bidirectional buffer through the 3rd data bus, the user data by the address storage different disposal cycle that provides by the three-address bus is provided; Flag register (110) is used to control the execution of described execution command; Impact damper (120) is connected with described flag register, so that make CPU check the state of described flag register; Mode of operation controller (130) is connected with described flag register, is used to produce one or more control signals, controls the execution of described execution command; And logic/translator unit (140), be connected with described mode of operation controller, be used to adopt described data memory through the described user data that described the 3rd data bus provides, decipher the operation of described execution command and actuating logic; Wherein, to in described data memory, store corresponding to first visit of handling a described user data in cycle, in fact with to carrying out simultaneously in described user's memory storage corresponding to being different from described first second processing of handling a described execution command in cycle of handling the cycle.
In above-mentioned instruction process system, described user instruction comprises the instruction code of being made up of operational code and operand; Described operational code comprises the service data relevant with the execution of described user data, and described operand comprises a word address and a bit number; Described word address is represented the position of the relative users data of storing in the described data-storing apparatus; Described bit number is represented the position of a bit in the described word, and this bit is used to store the result of the described logical operation relevant with described execution command.
According to ladder instruction process system of the present invention, in order to reduce to be used to handle the time of each instruction, under the situation of using multiple bus system, at same bus in the cycle, execution/the read operation of instruction carries out simultaneously, and each bus system is made of an address bus and a data bus.
Other purpose of the present invention and advantage will be narrated in the declaratives below, may be obvious that these purposes and advantage from following declaratives, perhaps can be by recognizing in the practice of the present invention.These purposes of the present invention and advantage will realize and reach by means of element of pointing out in detail in the appended claims and combination.
Accompanying drawing combines with the instructions component part, has shown one embodiment of the present of invention, and is used from explanation principle of the present invention with instructions one.
Fig. 1 is the block scheme of the programmable logic controller (PLC) with a high speed ladder instruction process system that provides according to one embodiment of present invention;
Fig. 2 A has provided the typical set table that shows user's definable order code of being stored in user's memory of the programmable logic controller (PLC) of Figure 1A;
Fig. 2 B has provided the typical set table that shows user's definable data of being stored in the data memory of the programmable logic controller (PLC) of Figure 1B;
Fig. 3 is the typical set of the programmable logic controller (PLC) of Figure 1A and 1B in the sequential of different processing signals in period.
Describe the most preferred embodiment of the present invention shown in the accompanying drawing now in detail.Identical or similar part related in whole accompanying drawing will be used identical label.
Referring to Fig. 1, this programmable logic controller (PLC) (PLC) includes a CPU (central processing unit) (CPU) 10 that is used for controlling all operations of this PLC.Address decoder 20 is connected to CPU 10 by first address bus.Memory 150,160 is connected to CPU, is used for by first data bus with data-storing therein.The common formation of this first address and data bus first bus system.
Specifically, this PLC comprises a high speed ladder instruction process system (" instruction process system ").This instruction process system is preferable to be to comprise a programmable counter 30, and this programmable counter 30 is in response to the clock signal C 1 that is added to programmable counter 30 and input signal-L1 and provide an address to each trapezoidal instruction (back is called " execution command ").And then this instruction process system comprises first traffic pilot 40, and this first traffic pilot 40 has the input end A and the input end B who is connected to programmable counter 30 that are connected to CPU 10 by first address bus.Traffic pilot 40 is selected data according to control signal-G1 from any of input end A or B, and the data of selecting are offered second address bus.
And then this instruction process system comprises user's memory 50 that is connected to first traffic pilot 40, this user's memory 50 is used for storing the execution command by user's defined of this PLC in the address that is provided by second address bus, and the execution command that will be stored offers second data bus.The common formation of this second address and data bus second bus system.
Specifically, this PLC further comprises first bidirectional buffer 60 that is connected to CPU 10 by first bus system.As CPU 10 during, utilize impact damper 60 to cushion to user's memory 50 stored datas or from sense data wherein and when CPU 10 initialization (promptly putting initial value) programmable counter 30.
The instruction process system of this PLC then comprises an execution command memory 70 that is connected to user's memory 50.The execution command that the 70 temporary transient storages of execution command memory are visited from user's memory 50 by second data bus according to named order.This instruction process system comprises that then one has A end that is connected to CPU10 and second traffic pilot 80 that is connected to the B end of execution command memory 70 by an instruction bus.Traffic pilot 80 is selected data in any input end according to control signal-G2 from these two input ends, and selected data are offered the three-address bus.This instruction process system then comprises a data memory 90 that links to each other with second traffic pilot 80.Customer-furnished user data is provided in the address that is provided by the three-address bus data memory 90.
This PLC comprises that further one second bidirectional buffer, 100, the second bidirectional buffers 100 are connected to CPU10 through first bus system, and making CPU10 read user data and/or data memory 90 from data memory 90, to write user data more easy.The instruction process system of this PLC comprises that then is used for controlling the flag register 110 that this execution command is carried out, and one is connected with flag register 110 and is used for making the more easy impact damper 120 of state of CPU10 verification characteristics bit register 110.
This instruction process system then comprises a mode of operation controller 130 that is connected to flag register 110.According to the state of flag register 110, controller 130 produces one or more control signals and goes to control the operation relevant with the execution of executing instruction.This instruction process system then comprises a logic/decoding unit 140 that is connected to mode of operation controller 130.Decoding of 140 pairs of these execution commands of logic/decoding unit and the user data that provides from the 3rd bus system according to decoded execution command utilization and actuating logic operation.
The work with PLC of high speed ladder instruction process system of the present invention of being summarized above explaining below.
By first bidirectional buffer 60, CPU 10 provides one to have low level " L " (promptly for the input end D of programmable counter 30, " a 0000 " state) signal deinitialization programmable counter 30, just an output terminal Q with programmable counter 30 is changed to zero " 0 " value.When mode of operation controller 130 side by side respectively to the Enable Pin-E of first and second bidirectional buffers 60 and 100 and respectively to the input end A of first and second traffic pilots 40 and 80 provide have high level " H " (promptly, with " 0000 " opposite states) control signal-G1 and-during G2, then the signal on the output terminal Q of the output terminal Q of programmable counter 30 and execution command memory 70 is provided to the input end B of first and second traffic pilots 40 and 80.
When clock signal C 1 offered the clock end C1 of programmable counter 30,30 of programmable counters provided a count signal with increment amplitude, and should be provided for first traffic pilot 40 by the count signal of increment.Then, when control signal-G1 had high level " H ", the count signal of this increment offered user's memory 50 by second address bus so that in the corresponding surely address of user's storage 50 middle fingers.Then, the execution command that is stored in the user's appointment in the corresponding address in user's memory 50 is read out, and offers execution command memory 70 by second data bus.At this moment execution command memory 70 temporarily stores the execution command of putting forward from second bus system.
Referring to Fig. 2 A, this execution command includes an instruction code, and the instruction code of this standard comprises two parts: operational code and operand.This operational code comprises the service data relevant with the execution of user data, and this operand comprises a word address and a bit number.This word address refers to the position that is stored in the corresponding user data in the data memory 90, and this bit number is meant the position of a bit in this word.This bit is the result who is used for storing the logical operation relevant with execution command.
As mentioned above, this execution command temporarily is stored in the execution command memory 70, and offers second traffic pilot 80 by instruction bus.The word address of this instruction temporarily is stored in the traffic pilot 80 according to control signal-G2, and this control signal-G2 is added to the Enable Pin-E of second bidirectional buffer 100 simultaneously.The word address of storage offers data memory 90 by the three-address bus in second traffic pilot 80, and the user data of the corresponding word address of storage is read out in data memory 90, and offer the data terminal D of logic/decoding unit 140 and offer CPU 10 by first bus system through second bidirectional buffer 100 by the 3rd data bus.
By instruction bus, execution command memory 70 also offers identical execution command the instruction input end I of logic/decoding unit 140.Then, logic/decoding unit 140 utilizes operational code and the bit number in this instruction that this execution command is deciphered, and will offer the data terminal D of logic/decoding unit 140 from the user data of data memory 90 by the 3rd bus system.
If offer in the execution command string of logic/decoding unit 140 decoded corresponding to the instruction of memonic symbol " OUT " (shown in Fig. 2 A), then logic/decoding unit 140 provides a corresponding signal for mode of operation controller 130 by its output terminal OUT, thereby mode of operation controller 130 produces the appropriate operating control signal corresponding to this corresponding signal.Free drilling make the state of state controller 130 verification characteristics bit registers 110.
If trapezoidal instruction (i.e. execution command) term of execution, be provided for logic/decoding unit 140 when stopping this execution corresponding to the instruction of memonic symbol " END " (shown in Fig. 2 B), then logic/decoding unit 140 provides a high level " H " signal to remove zero clearing flag register 110 to the clear terminal CLR of flag register 110 by its END end, thereby the signal on the output terminal Q of flag register 110 becomes low level " L ".Therefore, if mode of operation controller 130 provides a control signal to go to stop this operation, then impact damper 120 is in response to an enable signal-E3 from address decoder 20, provide an output signal by first data bus to CPU 10, and whether the execution that CPU 10 removes the state of verification characteristics bit register 110 again by first data bus and determines to be stored in this instruction in user's memory 50 stops.
2A and 2B and Fig. 3 with reference to the accompanying drawings come the work of the high speed ladder instruction process system of programmable logic controller (PLC) is described in more detail according to embodiments of the invention.
In Fig. 2 A and 2B, show an exemplary program and the typical data set of customer-furnished execution command string (the trapezoidal strings of commands) when the operation beginning respectively.This instruction repertorie and user data are stored in respectively in user's memory 50 and the data memory 90.10 pairs of programmable counter 30 initialization of CPU (promptly putting initial value) are to start the execution of programs of instructions of carrying out storage in user's memory 50.In more detail, for initialize routine counter 30, by address decoder 20, CPU 10 provides a low level " L " signal to latching output terminal-L1, shown in the sequential among Fig. 3 (E).When this low level " H " signal offered the latch input terminal that latchs output terminal-L1 and programmable counter 30-L, then programmable counter 30 entered latch mode.
From the control signal-G1 with low level " L " of mode of operation controller 130 and-G2 is provided for first and second bidirectional buffers 60 and 100, to start first and second bidirectional buffers 60 and 100, shown in the sequential among Fig. 3 (E).Thereby, shown in the sequential among Fig. 3 (B), on first data bus of the data terminal D that is connected to CPU 10, " 0000 " value is offered programmable counter 30 and make the initial value of programmable counter 30 be changed to zero " 0 " value by first bidirectional buffer 60.
When programmable counter 30 is initialised, CPU10 by address decoder 20 give latch output terminal-L1 and control end-G1 and-G2 provides a high level " H " signal, shown in the sequential among Fig. 3 (E), and this high level " H " signal is offered the latch input terminal-L of programmable counter 30.Because the clock end CK of flag register 110 is connected to latch input terminal-L, so this high level " H " signal comes operating characteristics bit register 110 as a clock signal now, and this high level " H " signal is provided for a START end of mode of operation controller 130 by the output terminal Q of flag register 110.According to the signal of the START end that is provided for it from flag register 110, the execution command that mode of operation controller 130 provides appropriate control signal to go to carry out user's appointment of storage in user's memory 50 is shown in the sequential among Fig. 3 (F).
As shown in the sequential among Fig. 3 (G), mode of operation controller 130 provide have low level " L " enable signal-E6 and-E7 deactivation user memory 50 and data memory 90.And as the sequential among Fig. 3 (J), (L) with (S), mode of operation controller 130 provides clock signal C 1, C2 and C3 and read signal-RD2 and-the RD3 deactivation reads in the data of storage in user's memory 50 and the data memory 90.
First and second traffic pilots 40 and 80 have an input end A who is connected to first address bus of CPU10 jointly, and another input end B is connected respectively to programmable counter 30 and execution command memory 70.First and second traffic pilots 40 and 80 provide a signal selectively from programmable counter 30 and execution command memory 70 respectively.In addition, according to trapezoidal (execution) instruction of carrying out storage in user's memory 50 from the control signal of mode of operation controller 130.
For example, when initial zero " 0 " value of programmable counter 30 is provided to first traffic pilot 40 by second address bus, and when offering the address end A of user's memory 50 subsequently, shown in the sequential among Fig. 3 (H), the instruction that is stored in the address " 0000 " (shown in Fig. 2 A) in user's memory 50 corresponding to memonic symbol " STR0000 " of the strings of commands of storage is provided for second data bus in user's memory 50, shown in sequential among Fig. 3 (I).
Referring to sequential among Fig. 3 (J), be provided for the C2 end of execution command memory 70 from each time control signal C2 of mode of operation controller 130, control signal C2 is as clock signal work, and the execution command that execution command memory 70 will temporarily be stored in wherein offers this instruction bus.Equally, be provided to programmable counter 30 from each time control signal C1 of mode of operation controller 130 by its C1 end, control signal C1 is that the address to indicate this execution command that increases gradually is performed as the value of clock signal work and programmable counter 30.
For example, referring to the sequential among Fig. 3 (M), be provided to instruction bus corresponding to the execution command of execution command in the memory 70 that temporarily be stored in of memonic symbol " STR0000 ".Referring to the sequential among Fig. 3 (Q), a corresponding word address " 00 " (shown in Fig. 2 A) that is included in this execution command is provided for second traffic pilot 80, and be provided for the three-address bus subsequently, so that indicate (word) address and the visit corresponding user data within it of data memory 90.
Referring to the sequential among Fig. 3 (P), be included in the instruction input end I that a bit number " 00 " (shown in Fig. 2 A) in the execution command is provided for logic/decoding unit 140.Referring to the sequential among Fig. 3 (I), in above-mentioned example, when by the three-address bus when specifying word address " 00 " (shown in Fig. 2 A) in the data memory 90, by the 3rd data bus, the corresponding data " 0001 " in being stored in address " 00 " (shown in Fig. 2 B) in the data memory 90 are provided for the input end D of logic/decoding unit 140.When from the execution command of execution command memory 70 with when coming the user data of the designated word address in the comfortable data memory 90 to be provided to the I of logic/decoding unit 140 and D input end respectively, 140 pairs of logic/decoding units should execution command be deciphered, and, carry out the decoded instruction of this user data of use that offers the there in response to the control signal C3 that is provided to its clock end C3 from mode of operation controller 130.
As mentioned above, sequential (J) referring to Fig. 3, in response to the control signal C1 in it of being provided to from mode of operation controller 130, the address that is stored in the execution command in the programmable counter 30 increases gradually, and be provided to the control signal C2 in it in response to from mode of operation controller 30 time, the execution command that execution command memory 70 will store within it offers instruction bus.Corresponding to the signal that is provided for second address bus and second data bus of user execution command be shown in respectively the sequential (H) of Fig. 3 and (I) in.The user data that offers the 3rd data bus is shown in the sequential of Fig. 3 (R), is shown in from the relevant control signal of mode of operation controller 130 in the sequential (J) of Fig. 3.
As mentioned above, referring to sequential among Fig. 3 (J), mode of operation control 130 side by side offers the clock end C1 of programmable counter 30 and the clock end C2 of execution command memory 70 respectively with control signal C1 and C2.Thereby programmable counter 30 and execution command memory 70 were worked on the essentially identical time.For example, in having the conventional PLC of unibus system structure, because should execute instruction before user data is accessed must be processed, thereby the processing (promptly carrying out) and the visit (promptly reading) of user data that the user executes instruction are carried out in the cycle at different time.On the contrary, in PLC of the present invention, because its instruction process system has used the multiple bus system structure, so the processing of user's execution command and the visit of user data are to carry out in the identical processing cycle, so saved total processing time.
For example, in conventional system with unibus system structure, one have first and follow the processor cycle n of second portion of first closely during, the user U (n) that executes instruction is at first processed during the first of processor cycle n, utilizes processed instruction U (n) user data d (n) then accessed subsequently during the second portion of processor cycle n.Equally, follow closely in during the first of the next processor cycle n+1 that follows processor cycle n closely the next user instruction U (n+1) of U (n) processed and during the second portion of processor cycle n+1 corresponding user data d (n+1) then visited.Therefore, in order to handle and calling party instruction U (n) and user data d (n), and subsequent user instruction U (n+1) and user data d (n+1), needs two processing cycle n and n+1.
On the contrary, according to the present invention, during the first that handles cycle n, execution command U (n) is processed.But, during the second portion of handling cycle n, user instruction U (n+1) is processed to be visited simultaneously with user data d (n), same, during the first that handles cycle n+1, subsequent user instruction U (n+2) is processed and user data d (n+1) is simultaneously accessed.
Referring to Fig. 1,, side by side be added to programmable counter 30 and execution command memory 70 respectively from the control signal C1 of mode of operation controller 130 and C2 according to embodiments of the invention.Handling cycle n+1, in response to control signal C1, programmable counter 30 increases this count value, and by second address bus value that is increased is offered user's memory 50 as an address that is used to store corresponding execution command U (n+1) within it.Then, the corresponding execution command U (n+1) that is stored on this address in user's memory 50 is provided for execution command memory 70 by second data bus, so that temporarily be stored in wherein.At identical processing cycle n+1, in response to control signal C1 simultaneously from the control signal C2 of mode of operation controller 130, provide an execution command U (n) by three-address bus execution command memory 70 to data memory 90, this execution command U (n) be during the processing cycle n of morning, be stored in it and this execution command U (n) include the address that is used for a corresponding user data d (n).Identical processing cycle n+1 is still arranged, and in order further to handle, the user data d (n) that data memory 90 will store within it offers logic/decoding unit 140 by the 3rd data bus.Thereby, corresponding to the execute instruction execution of U (n+1) and carry out simultaneously of the user in processing cycle (n+1) corresponding to the visit of early handling the user data d (n) of cycle n.
In more detail, referring to Fig. 2 B, when clock signal C1 was triggered, if be " 0002 " from the incremental address that programmable counter C1 offers second address bus, then this address storage in user's memory 50 had the instruction corresponding to memonic symbol " OUT0016 ".Then, a corresponding instruction code " 6010 " is provided to second data bus." 6 " in the code " 6010 " are meant operational code, and " 01 " refers to that word address and " 0 " are bit numbers.When control signal C1 is triggered once more, risen to " 0003 " and offered signal shown in sequential among Fig. 3 (H) of second address bus from the address of programmable counter 30.The instruction code " 1002 " corresponding to memonic symbol " STR NOT 0002 " is pointed in this " 0003 " address, and one give put time t disappear after these " 1002 " instruct and be provided for second data bus, shown in sequential among Fig. 3 (I).
Equally, in response to control signal C1, if be provided for second data bus from user's memory 50 corresponding to the address of the execution command code " 6011 " of the memonic symbol in Fig. 2 A " OUT0017 ", then in response to control signal C2, same instructions from execution command memory 70 is provided for this instruction bus after a while, go to carry out this instruction so that give the time interval t that puts by logic/decoding unit 140, shown in sequential among Fig. 3 (N) one.Referring to Fig. 2 B, word address " 01 " is with respect to an address in data memory 90, and this address provides from execution command memory 70 by second traffic pilot 80.Operational code in this execution command code and bit number be by it input end I from the execution command memory 70 offer logic/decoding unit 140.
For example, referring to sequential among Fig. 3 (N), the term of execution of the instruction in this " OUT 0017 ", after operational code " 6 " and bit number " 1 " are provided for logic/decoding unit 140,140 pairs of execution commands of logic/decoding unit code itself is deciphered, and provide to mode of operation controller 130 by its output terminal OUT and to give a high level " H " signal of putting time interval t, until the execution of finishing this " OUT 0017 " instruction.According to the identification from high level " H " signal of logic/decoding unit 140, mode of operation controller 130 is carried out with " OUT 0017 " and is instructed relevant operation.And then, referring to sequential among Fig. 3 (J) this quilt give put time t during, control signal C1 and C2 and the second reading number of winning the confidence-RD2 are maintained at height " H " level state, when carrying out output function, stop from the storage of user's memory 50 reading within it corresponding to the address of subsequently execution command with box lunch.
Referring to the sequential among Fig. 3 (R), if specify word address " 01 " (as shown in fig. 2B) in data memory 90, then data " 5432 " (shown in Fig. 2 B) are provided for the 3rd data bus and offer logic/decoding unit 140 then.Then, logic/decoding unit 140 is carried out the logical operation corresponding to the execution command that is provided in the user data " 5432 " in it, and on the bit number with the appointment of result storage in word address " 01 " of this logical operation.The 3rd a write signal-WR3 with low-signal levels " L " gives at this and being provided by mode of operation controller 130 during putting time t, to carry out stored data in data memory 90.When the 3rd write signal-WR3 of mode of operation controller 130 remains on low " L " level, the result of this logical operation is stored in the data memory 90 by the 3rd data bus, and provide second reading signal-RD2 and control signal C1 and C2 shown in sequential among Fig. 3 (J)
After the result of this logical operation was stored in the data memory 90, logic/decoding unit 140 provided a low level " L " signal by its OUT end to mode of operation controller 130, finishes with the operation of indicating this execution.Then, mode of operation controller 130 provides third reading signal-RD3 and the 3rd write signal-WR3 shown in sequential among Fig. 3 (S) and sequential (T) again respectively, reading in the data memory 90 data of storage, and in logic/decoding unit 140, continue to carry out its corresponding operation.
If in execution command memory 70, instruction code " F000 " corresponding to memonic symbol " END " (shown in Fig. 2 A) is effectively, and the execution that then is used for stopping this execution of programs of instructions is effective.Referring to the sequential among Fig. 3 (O), 140 pairs of these END instruction decodes of logic/decoding unit also provide the clear terminal CLR zero clearing of a high level " H " signal to flag register 110 (low-signal levels " L " promptly is set) by its END end, and this END end also provides high level " H " signal in addition in the time that this program is performed.
Thereby flag register 110 provides low level " L " signal by its an output terminal Q.According to identification from low level " L " signal of flag register 110, free on the mode of operation controller 130 of output state of verification characteristics bit register 110 show that this " END " instructs and be provided, and provide a control signal to go to carry out this END operation to stop this program implementation to appropriate control end, thereby after the operation of this program was terminated, the state of 10 pairs of flag registers 110 of CPU was tested and is carried out appropriate operation.
As mentioned above, according to embodiments of the invention, owing to used multibus (being a pair of address/data bus) system to substitute unibus system, the execution of user's execution command and the visit of user data are carried out simultaneously, thereby total processing time reduce significantly, consequently saved significantly the entire process time.In addition, need not to increase cost and just can realize top mentioned improvement.
Consider that from detailed description and measure that the present invention is disclosed those of ordinary skill in the art is not difficult to obtain other embodiments of the invention.It should be noted that above-mentioned explanation and example only are that the scope and spirit accurately that the present invention had are pointed out by following claim as the typical case for example.
Claims (2)
1. instruction process system that is used to improve programmable logic controller (PLC) instruction process speed, described programmable logic controller (PLC) comprises CPU (central processing unit) (CPU) (10), the address decoder (20) that is connected with CPU through first address bus, the memory (150 that is connected with CPU through first data bus, 160), described instruction process system, first bidirectional buffer (60) that first bus system that constitutes via described first address bus and first data bus is connected with CPU, second bidirectional buffer (100) that is connected with CPU through this first bus system, described instruction process system is characterised in that it comprises:
Programmable counter (30) is used for the address that produces each user instruction that will carry out in response to clock signal and its input signal;
First traffic pilot (40), an one input end is connected with CPU through first address bus, and another input end is connected to described programmable counter, and being used for provides its output to second address bus;
User's memory (50) is connected with described first traffic pilot through described second address bus, is used to store the instruction in different disposal cycle and the instruction of being stored is offered second data bus;
Execution command memory (70) is connected with user's memory through described second data bus, is used for the execution command that temporary transient storage is read from user's memory with designated order;
Second traffic pilot (80), an one input end is connected with CPU, and another input end is connected with described execution command memory through instruction bus, is used for providing its output to the three-address bus;
Data memory (90), be connected with described second traffic pilot through described three-address bus, and be connected with described second bidirectional buffer through the 3rd data bus, the user data by the address storage different disposal cycle that provides by the three-address bus is provided;
Flag register (110) is used to control the execution of described execution command;
Impact damper (120) is connected with described flag register, so that make CPU check the state of described flag register;
Mode of operation controller (130) is connected with described flag register, is used to produce one or more control signals, controls the execution of described execution command; And
Logic/translator unit (140) is connected with described mode of operation controller, is used to adopt described data memory through the described user data that described the 3rd data bus provides, and deciphers the operation of described execution command and actuating logic;
Wherein, to in described data memory, store corresponding to first visit of handling a described user data in cycle, in fact with to carrying out simultaneously in described user's memory storage corresponding to being different from described first second processing of handling a described execution command in cycle of handling the cycle.
2. instruction process system as claimed in claim 1, wherein, described user instruction comprises the instruction code of being made up of operational code and operand; Described operational code comprises the service data relevant with the execution of described user data, and described operand comprises a word address and a bit number; Described word address is represented the position of the relative users data of storing in the described data-storing apparatus; Described bit number is represented the position of a bit in the described word, and this bit is used to store the result of the described logical operation relevant with described execution command.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920011576A KR950009687B1 (en) | 1992-06-30 | 1992-06-30 | High speed ladder instruction processing apparatus for programnable logic controller |
| KR11576/92 | 1992-06-30 | ||
| KR11576/1992 | 1992-06-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1080740A CN1080740A (en) | 1994-01-12 |
| CN1054442C true CN1054442C (en) | 2000-07-12 |
Family
ID=19335598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN93107851A Expired - Fee Related CN1054442C (en) | 1992-06-30 | 1993-06-30 | A high speed ladder instruction process system for a programmable logic controller |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5809319A (en) |
| KR (1) | KR950009687B1 (en) |
| CN (1) | CN1054442C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1094610C (en) | 1994-12-02 | 2002-11-20 | 英特尔公司 | Microprocessor with packing operation of composite operands |
| EP1014270A4 (en) * | 1996-10-24 | 2004-10-06 | Mitsubishi Electric Corp | Microcomputer with memory and processor provided on the same chip |
| US6421817B1 (en) * | 1997-05-29 | 2002-07-16 | Xilinx, Inc. | System and method of computation in a programmable logic device using virtual instructions |
| TW200428171A (en) * | 2003-06-13 | 2004-12-16 | Delta Electronics Inc | Method for controlling single step of the program in programmable logic controller |
| JP5473817B2 (en) * | 2010-07-23 | 2014-04-16 | 三菱電機株式会社 | Programmable controller and bus converter |
| US20120271968A1 (en) * | 2011-04-21 | 2012-10-25 | Microchip Technology Incorporated | Logic device for combining various interrupt sources into a single interrupt source and various signal sources to control drive strength |
| US9450585B2 (en) | 2011-04-20 | 2016-09-20 | Microchip Technology Incorporated | Selecting four signals from sixteen inputs |
| CN105843157B (en) * | 2016-03-30 | 2018-10-12 | 上海云统信息科技有限公司 | PLC system and its working method with teledata trace trap function |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3982230A (en) * | 1974-01-07 | 1976-09-21 | Texas Instruments Incorporated | Programmable logic controller with flag storage |
| US4122519A (en) * | 1976-12-14 | 1978-10-24 | Allen-Bradley Company | Data handling module for programmable controller |
| US4417304A (en) * | 1979-07-30 | 1983-11-22 | International Business Machines Corporation | Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit |
| US4742443A (en) * | 1985-03-28 | 1988-05-03 | Allen-Bradley Company | Programmable controller with function chart interpreter |
| US5125088A (en) * | 1986-09-08 | 1992-06-23 | Compaq Computer Corporation | Computer system speed control at continuous processor speed |
| US4958304A (en) * | 1987-03-02 | 1990-09-18 | Apple Computer, Inc. | Computer with interface for fast and slow memory circuits |
| US4972365A (en) * | 1987-05-01 | 1990-11-20 | Allen-Bradley Company, Inc. | Executing downloaded user programs in a programmable controller |
| JPH0810428B2 (en) * | 1988-12-26 | 1996-01-31 | 三菱電機株式会社 | Data processing device |
| US5319783A (en) * | 1989-03-31 | 1994-06-07 | Allen-Bradley Company Inc. | Programmable controller with an operator messaging function |
| JP2710994B2 (en) * | 1989-08-29 | 1998-02-10 | 三菱電機株式会社 | Data processing device |
| US5225974A (en) * | 1990-10-30 | 1993-07-06 | Allen-Bradley Company, Inc. | Programmable controller processor with an intelligent functional module interface |
| US5390350A (en) * | 1991-04-22 | 1995-02-14 | Western Digital Corporation | Integrated circuit chip core logic system controller with power saving features for a microcomputer system |
-
1992
- 1992-06-30 KR KR1019920011576A patent/KR950009687B1/en not_active IP Right Cessation
-
1993
- 1993-06-30 CN CN93107851A patent/CN1054442C/en not_active Expired - Fee Related
-
1997
- 1997-01-09 US US08/781,521 patent/US5809319A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR940000980A (en) | 1994-01-10 |
| KR950009687B1 (en) | 1995-08-26 |
| US5809319A (en) | 1998-09-15 |
| CN1080740A (en) | 1994-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6088740A (en) | Command queuing system for a hardware accelerated command interpreter engine | |
| US5437043A (en) | Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers | |
| US5379381A (en) | System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations | |
| US5386563A (en) | Register substitution during exception processing | |
| KR100227419B1 (en) | External storage device and memory access control method for the same | |
| RU2212049C2 (en) | Mixed file of vector/scalar registers | |
| US4733346A (en) | Data processor with multiple register blocks | |
| US4020471A (en) | Interrupt scan and processing system for a data processing system | |
| US6662253B1 (en) | Shared peripheral architecture | |
| EP0155211A2 (en) | System for by-pass control in pipeline operation of computer | |
| CN1161689C (en) | Performance speculative misaligned load operations | |
| CN1264083C (en) | Method and apparatus for maintaining context while executing translated instructions | |
| CN1054442C (en) | A high speed ladder instruction process system for a programmable logic controller | |
| JPS60176143A (en) | Program calling apparatus | |
| US20030120902A1 (en) | Resource management using multiply pendent registers | |
| KR930003400B1 (en) | Status register device for microprocessor | |
| WO2008043287A1 (en) | Configurable single instruction multiple data unit | |
| CN1488096A (en) | Microprocessor circuit of portable data carrier | |
| EP0240606A2 (en) | Pipe-line processing system and microprocessor using the system | |
| US7228393B2 (en) | Memory interleaving | |
| KR900005420B1 (en) | Buffer memory control system | |
| EP0465847B1 (en) | Memory access control having commonly shared pipeline structure | |
| CN1385782A (en) | Microprocessor | |
| EP0660230B1 (en) | Improvements in or relating to program counters | |
| JP2626675B2 (en) | Apparatus and method for generating data-induced state signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C53 | Correction of patent of invention or patent application | ||
| CB02 | Change of applicant information |
Address after: Gyeonggi Do, South Korea Applicant after: Samsung Electronics Co., Ltd. Address before: Gyeongnam, South Korea Applicant before: Samsung Aerospace Industries, Ltd. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: SAMSUNG AEROSPACE INDUSTRIES, LTD. TO: SAMSUNG ELECTRONICS CO., LTD |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: ROCKWELL SAMSUNG AUTOMATION Free format text: FORMER OWNER: SAMSUNG ELECTRONICS CO., LTD Effective date: 20021129 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20021129 Address after: Seoul Patentee after: Rockwell Samsung automation Address before: Gyeonggi Do, South Korea Patentee before: Samsung Electronics Co., Ltd. |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20000712 Termination date: 20100630 |