CN105428403B - A kind of indium phosphide double hetero bipolar transistor npn npn epitaxial layer structure - Google Patents
A kind of indium phosphide double hetero bipolar transistor npn npn epitaxial layer structure Download PDFInfo
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- CN105428403B CN105428403B CN201510919059.5A CN201510919059A CN105428403B CN 105428403 B CN105428403 B CN 105428403B CN 201510919059 A CN201510919059 A CN 201510919059A CN 105428403 B CN105428403 B CN 105428403B
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- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 125000005842 heteroatom Chemical group 0.000 title claims abstract description 10
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 10
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 4
- 229910052738 indium Inorganic materials 0.000 claims abstract description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000000137 annealing Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 238000001816 cooling Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 240000002329 Inga feuillei Species 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 8
- 230000007704 transition Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000012010 growth Effects 0.000 description 2
- 150000001721 carbon Chemical group 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
The present invention relates to double hetero bipolar transistor (DHBT) technical fields, more particularly, to npn type InGaAs/InP DHBT technical fields, specifically disclose a kind of indium phosphide double hetero bipolar transistor npn npn epitaxial layer structure, include n type inp collector layer, energy band graded bedding, the p-type indium gallium arsyl region layer of heavy doping and the n type inp emitter layer being lightly doped successively upwards from InP substrate, energy band graded bedding is four-layer structure, and energy band graded bedding one to three is N-type In(1‑x)GaxAsyP(1‑y)Material, from collector layer to base layer, the content gradually variational between each layer, energy band graded bedding four is the non-InGa mixedxAs materials.Structure of the invention base area also has higher hole concentration and thinner thickness.Conduction band spike is not present at structure of the invention heterojunction boundary, electron transit time is shorter, and transistor made of the structure has higher frequency performance.
Description
Technical field
The present invention relates to double hetero bipolar transistor (DHBT) technical fields, more particularly, to npn type InGaAs/InP
DHBT technical fields.
Background technology
Indium phosphide double hetero bipolar transistor npn npn (InP DHBT) can have higher breakdown voltage and spy simultaneously
Frequency is levied, occupies space of prominence in high frequency, broadband and integrated optoelectronic circuit field, in radar, space satellite, guided missile system
It leads, communication system, space defense, the fields such as high-speed intelligent weapon and electronic countermeasure are more and more widely used.
InP DHBT include mainly I type InGaAs/InP and II type two kinds of technologies of GaAsSb/InP, wherein InGaAs/InP
The InP DHBT of structure have the following disadvantages at present：
1) since base area InGaAs and the interfaces collecting zone InP are since energy band is discontinuously and there are conduction band spike, conduction band is sharp
Summit hinders electronics transporting by emitter region to collecting zone, and the transition time of electronics is made to increase, and generates current blockade effect, causes
Device frequency reduces；
2) the base area material of InP DHBT generally mixes C using InGaAs, and the diffusion coefficient very little of C can accurately control
The position of PN junction, but C belongs to both sexes doped chemical in InGaAs, can provide electronics and provide hole, so
The base area InGaAs of InP DHBT mixes C and hardly results in high hole concentration, can seriously affect the performance of transistor, leads to the string of base area
Join resistance to increase, the frequency of device is made to reduce；
3) base area thickness too conference causes electronics to become larger in the compound of base area, and transition time of the electronics in base area is elongated, leads
The DC current gain and frequency for causing device reduce.
Therefore, in order to obtain the InP DHBT of higher frequency performance, it is necessary to be made further research to above-mentioned technical problem
It improves.
Invention content
The technical problem to be solved in the present invention is to provide a kind of indium phosphide double hetero bipolar transistor npn npn epitaxial layer knots
Conduction band spike is not present at heterojunction boundary for structure, and electron transit time is shorter, and transistor made of the structure has higher frequency
Rate performance.
In order to solve the above technical problems, the technical solution used in the present invention is：A kind of indium phosphide double hetero bipolar
Transistor npn npn epitaxial layer structure includes the n type inp collector layer being lightly doped, energy band gradual change successively upwards from InP substrate
Layer, the p-type indium gallium arsyl region layer of heavy doping and n type inp emitter layer, the energy band graded bedding are four layers, are located at current collection
Structure between region layer and base layer is as shown in the table,
Further, doped carbon in the base layer InGaAs, doping concentration 2E19-5E19cm-3。
Further, the base layer by carrying out in-situ annealing, annealing way in a nitrogen environment after the completion of MOCVD growths
It anneals for cooling, annealing temperature drops to 400 DEG C from 550 DEG C, time 5min.
Further, the base area layer thickness is 20nm-40nm, and InGaAs materials laterally emit from energy band graded bedding one
Region layer content gradually variational, by In0.55Ga0.45As fades to In0.45Ga0.55As。
Further, time collector layer is equipped between the collector layer and substrate, the secondary collector layer is doping Si
N-type InGaAs, thickness 0.3-0.5um, doping concentration 5E18-2E19cm-3。
Further, the top of emitter layer is equipped with emitter region contact layer and surface electrode contact layer successively；The transmitting
Area's contact layer is the N-type InP materials for adulterating Si, thickness 100nm-200nm, doping concentration 5E18-2E19cm-3；The table
Face contact electrode layer is the N-type InGaAs materials for adulterating Si, thickness 50nm-150nm, doping concentration 5E18-2E19cm-3。
Further, the substrate is the semi-insulating type InP materials of (100) crystal face, thickness 620um.
It is using advantageous effect caused by above-mentioned technical proposal：The present invention uses the energy band graded bedding of four-layer structure,
The conduction band spike of base area and current collection regional boundary face can be eliminated, the obstruction to electron motion is reduced, improves device frequency.Energy of the present invention
Thickness with the graded bedding number of plies and layer is moderate, is suitable for MOCVD and grows, production difficulty is low, and quality is easy to control.
Description of the drawings
Fig. 1 is that bipolar transistor of the embodiment of the present invention tests I-V characteristic curve；
Fig. 2, Fig. 3 are bipolar transistor high frequency characteristics curve of the embodiment of the present invention.
Specific implementation mode
For the epitaxial layer structure of the InP DHBT of InGaAs/InP structures, the present invention considers from the following aspects to it
It advanced optimizes and improves：In order to improve the frequency characteristic of device, base epitaxial layer thickness is thinned and improve its doping concentration, with
It reduces carrier Base Transit Time and reduces base series resistor；In order to reduce the collector junction base areas interface I nGaAs and InP collection
Electric area due to conduction band discontinuously caused by current blockade effect, between the base region and the collector be inserted into content gradually variational InGaAsP
Energy band graded bedding, to eliminate conductive spike；The thickness of collecting zone appropriate is chosen to optimize the collecting zone transition time of carrier.
The present invention is described in further detail below.
Embodiment
A kind of indium phosphide double hetero bipolar transistor npn npn epitaxial layer structure is shown in that Fig. 1, substrate are the half of (100) crystal face
Insulated type InP materials, thickness 620um are used for isolating device in transistor arrangement, prevent that short circuit effect occurs between device
Answer, from substrate upwards successively be equipped be lightly doped n type inp collector layer, energy band graded bedding, heavy doping p-type indium gallium arsyl
Region layer and n type inp emitter layer, each layer structure see the table below.
Secondary collector layer is collecting zone contact electrode layer, is made on substrate, and secondary collector layer is the N-type for adulterating Si
InGaAs, thickness 0.3-0.5um, doping concentration 5E18-2E19cm-3.It is highly doped to be advantageously implemented good Ohmic contact,
Reduce series resistance.
Collector layer is the non-InP materials mixed, it is therefore an objective to collect the electronics transmitted by emitter region；There are electric fields for inside, make
Electronics accelerates；Reduce capacitance.InP materials improve the breakdown voltage of device instead of traditional InGaAs materials.
Energy band graded bedding uses four-layer structure, and wherein energy band graded bedding one to energy band graded bedding three is N-type In(1-x)
GaxAsyP(1-y)Material, from collector layer to base layer, the content gradually variational between each layer, energy band graded bedding four is non-to be mixed
InGaxAs materials, each layer have different band gap widths, play conduction band smoothing effect, eliminate leading for base area and current collection regional boundary face
Band spike, reduces the obstruction to electron motion, improves device frequency.
Doped carbon in base layer InGaAs, doping concentration 2E19-5E19cm-3, dense to obtain high hole in base layer
Degree, base layer are that cooling is annealed by carrying out in-situ annealing, annealing way after the completion of MOCVD growths in a nitrogen environment, annealing temperature
Degree uniformly drops to 400 DEG C from 550 DEG C, time 5min so that the carbon atom in base layer InGaAs is fully activated, and is obtained
High-dopant concentration reduces the resistance of base area, improves device frequency.
For base layer thickness control in 20nm-40nm, narrow base area thickness can reduce electronics in the complex effect of base area, reduce
The transition time of electronics improves device gain and frequency.
The ratio of base layer InGaAs material components is inhomogenous in layer, from one lateral emitter layer component of energy band graded bedding
Gradual change, by In0.55Ga0.45As fades to In0.45Ga0.55As.Base area content gradually variational can form internal electric field in base area, make electricity
Son accelerates, and improves device frequency.
Emitter layer is N-type InP materials, and effect is launching electronics.
Emitter region contact layer is highly doped N-type InP materials, highly doped to be advantageously implemented good Ohmic contact, is reduced
Series resistance.
Surface electrode contact layer is highly doped N-type InGaAs materials, highly doped to be advantageously implemented good Ohmic contact, is subtracted
Small series resistance, InGaAs materials can reduce the Surface combination effect of electronics.
I-V characteristic curve is tested to the bipolar transistor of the embodiment epitaxial layer structure：
Test condition：Vce=[0,4] V, step=0.1V；Ib=[0,100] uA, step=10uA；Ve=0V；Output
Base voltage Vbe, collector current Ice.
Test spectrogram is shown in Fig. 1, it can be seen that it, which tests DC current gain, reaches 80 from figure.
The bipolar transistor of the embodiment epitaxial layer structure is surveyed using Network Analyzer and Ic-cap analysis softwares
Try the high frequency characteristics of device：
Test frequency range：1E9Hz to 4E10Hz.
Test spectrogram is shown in that Fig. 2 and Fig. 3, wherein curve a are test curve, and straight line b is test curve a prolonging at its inflection point
The intersection point of long line, extended line and x-axis is frequency characteristic numerical value.It can be seen that its test cutoff frequency Ft reaches from figure
220GHz, maximum operation frequency Fmax reach 400GHz.
Claims (7)
1. a kind of indium phosphide double hetero bipolar transistor npn npn epitaxial layer structure includes non-mix successively upwards from InP substrate
Miscellaneous n type inp collector layer, energy band graded bedding, the p-type indium gallium arsyl region layer of heavy doping and n type inp emitter layer,
It is characterized in that, the energy band graded bedding is four layers, the structure between collector layer and base layer is as shown in the table.
2. epitaxial layer structure according to claim 1, which is characterized in that doped carbon in the base layer InGaAs is mixed
Miscellaneous a concentration of 2E19-5E19cm-3。
3. epitaxial layer structure according to claim 2, which is characterized in that the base layer grown by MOCVD after the completion of
Carry out in-situ annealing under nitrogen environment, annealing way is that cooling is annealed, and annealing temperature drops to 400 DEG C from 550 DEG C, and the time is
5min。
4. epitaxial layer structure according to claim 2, which is characterized in that the base area layer thickness is 20nm-40nm,
InGaAs materials are from one lateral emitter layer content gradually variational of energy band graded bedding, by In0.55Ga0.45As fades to In0.45Ga0.55As。
5. epitaxial layer structure according to claim 4, which is characterized in that be equipped with time collection between the collector layer and substrate
Electric region layer, the secondary collector layer are the N-type InGaAs, thickness 0.3-0.5um, doping concentration 5E18- for adulterating Si
2E19cm-3。
6. epitaxial layer structure according to claim 4, which is characterized in that the top of emitter layer connects equipped with emitter region successively
Contact layer and surface electrode contact layer；The emitter region contact layer be adulterate Si N-type InP materials, thickness 100nm-200nm,
Doping concentration is 5E18-2E19cm-3；The surface electrode contact layer is the N-type InGaAs materials for adulterating Si, thickness 50nm-
150nm, doping concentration 5E18-2E19cm-3。
7. epitaxial layer structure according to claim 5, which is characterized in that the substrate is the semi-insulating type of (100) crystal face
InP materials, thickness 620um.
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| CN110660666A (en) * | 2019-09-27 | 2020-01-07 | 厦门市三安集成电路有限公司 | Transistor epitaxial growth method and preparation method of transistor |
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