CN105428318B - The manufacture method of flash memory structure - Google Patents

The manufacture method of flash memory structure Download PDF

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Publication number
CN105428318B
CN105428318B CN201610033975.3A CN201610033975A CN105428318B CN 105428318 B CN105428318 B CN 105428318B CN 201610033975 A CN201610033975 A CN 201610033975A CN 105428318 B CN105428318 B CN 105428318B
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Prior art keywords
developer
word line
flash memory
layer
wordline
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CN201610033975.3A
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CN105428318A (en
Inventor
徐涛
陈宏�
王卉
曹子贵
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

Abstract

A kind of manufacture method of flash memory structure, including：Substrate, including logic area and memory cell areas are provided；Word line layer is formed on substrate；Neutralisation treatment is carried out to wordline layer surface using developer；After carrying out neutralisation treatment, patterned photoresist layer is formed in wordline layer surface by exposure imaging technique, patterned photoresist layer exposes the wordline layer surface of logic area；Using patterned photoresist layer as mask, the word line layer of logic area is removed, wordline is formed in memory cell areas.The present invention is before developing process is exposed, neutralisation treatment is first carried out to the wordline layer surface using developer, with wordline layer surface acid-base neutralization reaction occurs for the ion for the developer for avoiding using in the exposure imaging technique, so as to improve the development effect of the developer, the developer of exposure imaging technique fully develops to photoresist layer, avoiding the wordline layer surface of logic area has photoetching glue residua, the word line layer of logic area is removed completely, and then improves the yield of flash memory structure.

Description

The manufacture method of flash memory structure
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of manufacture method of flash memory structure.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type：Analog circuit, digital circuit With D/A hybrid circuit, wherein, memory device is an important kind in digital circuit.And in memory device, in recent years The development of flash memory (Flash Memory, abbreviation flash memory) is particularly rapid.Flash memory is mainly characterized by not powered feelings The information of storage can be kept under condition for a long time；And have the advantages that integrated level is high, access speed is fast, be easy to wipe and rewrite, thus It is widely used in the multinomial field such as microcomputer, Automated condtrol.
Flash memory structure mainly includes gate stack (Stack Gate) structure and divides grid (Split Gate) structure.Wherein, Grid dividing structure is transported extensively due to that with higher programming efficiency, can avoid excessive erasable problem in erasable function In the electronic products such as all kinds of smart cards, SIM card, microcontroller, mobile phone.
But the yield of flash memory structure has much room for improvement in the prior art.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of manufacture method of flash memory structure, improve the yield of flash memory structure.
To solve the above problems, the present invention provides a kind of manufacture method of flash memory structure, comprise the following steps：Lining is provided Bottom, the substrate include logic area and memory cell areas；Word line layer is formed over the substrate；Using developer to the wordline Layer surface carries out neutralisation treatment；After carrying out the neutralisation treatment, formed and schemed in the wordline layer surface by exposure imaging technique The photoresist layer of shape, the patterned photoresist layer expose the wordline layer surface of the logic area；With described graphical Photoresist layer be mask, remove the word line layer of the logic area, memory cell areas formed wordline.
Optionally, the material of the word line layer is the polysilicon of heavy doping.
Optionally, in the step of carrying out neutralisation treatment to the wordline layer surface using developer, the developer is alkali Property developer.
Optionally, the alkaline developer is tetramethyl ammonium hydroxide solution.
Optionally, the mass concentration of the tetramethyl ammonium hydroxide solution is 2% to 2.5%.
Optionally, in the step of carrying out neutralisation treatment to the wordline layer surface using developer, the temperature of the developer Spend for 20 DEG C to 40 DEG C.
Optionally, in the exposure imaging technique, developed using the developer comprising alkali ion.
Optionally, the alkali ion is hydroxide ion.
Optionally, the technique for removing the word line layer of the logic area is plasma dry etch process.
Optionally, the developer is identical with the developer used in the exposure imaging technique.
Compared with prior art, technical scheme has advantages below：
The present invention is first carried out at neutralization before developing process is exposed using developer to the wordline layer surface Reason, the developer for avoiding using in the exposure imaging technique occur acid-base neutralization reaction with the wordline layer surface and consume institute The problem of stating developer, so as to improve the development effect of the developer, make the developer of the exposure imaging technique to described Photoresist layer fully develops, so that the word line layer of logic area can be removed completely, and then improves the yield of flash memory structure.
In alternative, neutralisation treatment is carried out to the wordline layer surface using developer, avoids developing in developing process The problem of ion of agent occurs acid-base neutralization reaction with the wordline layer surface and consumes developer neutral and alkali ion, makes the exposure The developer of photo development processes fully develops to the photoresist layer, so as to avoid the wordline layer surface of logic area from having photoresist residual Stay, and then reduce quantity the defects of when developing visual inspection.
In alternative, the developer is identical with the developer used in the exposure imaging technique, so as to keep away Exempt to introduce foreign ion into developing process.
Brief description of the drawings
Fig. 1 and Fig. 2 is structural representation corresponding to prior art wordline forming process；
Fig. 3 is the schematic flow sheet of the embodiment of manufacture method one of flash memory structure of the present invention；
Fig. 4 and Fig. 5 is structural representation corresponding to the embodiment of wordline forming process one of the present invention；
Fig. 6 be using flash memory structure of the present invention manufacture method after develop visual inspection when the defects of quantity figure.
Embodiment
From background technology, the flash memory structure yield that prior art is formed has much room for improvement.Word is stored with reference to prior art Wire forming proces analyze its reason.With reference to figure 1 and Fig. 2, structural representation corresponding to prior art wordline forming process is shown.
Specifically, it refer to Fig. 1, there is provided substrate 100, wherein, the substrate 100 includes logic area II and memory cell areas Ⅰ.Formed with floating gate layer 200 and floating gate dielectric layer 300 on the substrate 100 of the memory cell areas I；In the He of logic area II Word line layer 400 ' is formed on the substrate 100 of memory cell areas I, patterned photoresist layer is formed on the surface of word line layer 400 ' (not shown), the patterned photoresist layer expose the word line layer 400 ' of the logic area II.
With reference to figure 2, using the patterned photoresist layer as mask, the word line layer 400 ' of the logic area II is removed (such as Shown in Fig. 2), form wordline 400 in the memory cell areas I.
With continued reference to Fig. 2, after forming the word line layer 400 ', the surface attachment of the word line layer 400 ' has the group of acidity And make the surface of word line layer 400 ' in acidity, when forming patterned photoresist layer by exposure imaging technique, due to development Developer includes alkali ion in technique, therefore the developer is easily anti-in the surface of word line layer 400 ' generation acid-base neutralization Answer and consume the alkali ion in the developer, this easily weakens the development effect of developer, causes the exposure imaging work The developer of skill is insufficient to photoresist layer development, so as to cause the surface of word line layer 400 ' of logic area II to have photoresist residual Stay, and then easily cause the word line layer 400 ' of logic area II to remove not exclusively, logic area II is had word line layer residue 410 ".Institute Stating the defects of presence of wordline residue 410 " not only makes during development visual inspection quantity increases, and is also easy to reduce the good of flash memory structure Rate.
In order to solve the technical problem, the present invention provides a kind of manufacture method of flash memory structure, including：Substrate is provided, The substrate includes logic area and memory cell areas；Word line layer is formed over the substrate；Using developer to the word line layer Surface carries out neutralisation treatment；After carrying out the neutralisation treatment, figure is formed in the wordline layer surface by exposure imaging technique The photoresist layer of change, the patterned photoresist layer expose the wordline layer surface of the logic area；With described patterned Photoresist layer is mask, removes the word line layer of the logic area, and wordline is formed in memory cell areas.
The present invention is first carried out at neutralization before developing process is exposed using developer to the wordline layer surface Reason, the developer for avoiding using in the exposure imaging technique occur acid-base neutralization reaction with the wordline layer surface and consume institute The problem of stating developer, so as to improve the development effect of the developer, make the developer of the exposure imaging technique to described Photoresist layer fully develops, so that the word line layer of logic area can be removed completely, and then improves the yield of flash memory structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
Fig. 3 is the schematic flow sheet of the embodiment of manufacture method one of flash memory structure of the present invention, and Fig. 4 and Fig. 5 are words of the present invention Structural representation corresponding to the embodiment of wire forming proces one, the manufacture method of the present embodiment flash memory structure include following basic step Suddenly：
Step S1：Substrate is provided, the substrate includes logic area and memory cell areas；
Step S2：Word line layer is formed over the substrate；
Step S3：Neutralisation treatment is carried out to the wordline layer surface using developer；
Step S4：After carrying out neutralisation treatment, patterned light is formed in the wordline layer surface by exposure imaging technique Photoresist layer, the patterned photoresist layer expose the wordline layer surface of the logic area；
Step S5：Using the patterned photoresist layer as mask, the word line layer of the logic area is removed, in memory cell Area forms wordline.
In order to which the manufacture method of flash memory structure of the present invention is better described, below in conjunction with reference to figure 4 and Fig. 5, to this hair Bright specific embodiment is further described.
With reference to reference to figure 4, step S1 is first carried out, there is provided substrate 500, the substrate 500 include logic area II and storage Cellular zone I.
The material of the substrate 500 can be silicon, germanium, SiGe, carborundum, GaAs or gallium indium, the substrate 500 It can also be the germanium substrate on the silicon substrate or insulator on insulator.In the present embodiment, the substrate 500 is silicon substrate.
In the present embodiment, formed with floating gate layer 600 and floating gate dielectric layer on the substrate 500 of the memory cell areas I 700, for storage information.
With continued reference to Fig. 4, step S2 is then performed, word line layer 800 ' is formed on the substrate 500.
The word line layer 800 ' provides Process ba- sis subsequently to form wordline in the memory cell areas I.
In the present embodiment, the material of the word line layer 800 ' is the polysilicon of heavy doping, using furnace process in the lining The word line layer 800 ' is formed on bottom 500.
It should be noted that the word line layer 800 ' is not only formed on the substrate 500 of the memory cell areas I, shape is gone back On the substrate 500 of logic area II described in Cheng Yu, the word line layer 800 ' also covers the surface of floating gate dielectric layer 700.
It should also be noted that, after forming the word line layer 800 ', the surface attachment of the word line layer 400 ' has acidity Group and make the surface of word line layer 800 ' in acidity.
Then step S3 is performed, neutralisation treatment is carried out to the surface of word line layer 800 ' using developer.
In the present embodiment, the surface attachment of the word line layer 400 ' has the group of acidity, therefore the table of word line layer 800 ' Face is acidic surface, accordingly, surface neutralisation treatment is carried out to the word line layer 800 ' using alkaline developer.
In the present embodiment, the alkaline developer is tetramethyl ammonium hydroxide solution.
It should be noted that the mass concentration of the tetramethyl ammonium hydroxide solution is unsuitable excessive, and it is also unsuitable too small, it is described The temperature of alkaline developer is unsuitable too high, also unsuitable too low, otherwise can influence surface neutralisation treatment and follow-up development effect. Therefore, in the present embodiment, the mass concentration of the tetramethyl ammonium hydroxide solution is 2% to 2.5%, the alkaline-based developer Temperature is 20 DEG C to 40 DEG C.
Then step S4 is performed, after carrying out the neutralisation treatment, by exposure imaging technique in the table of word line layer 800 ' Face forms patterned photoresist layer (not shown), and the patterned photoresist layer exposes the word line layer of the logic area II 800 ' surfaces.
In the present embodiment, in the exposure imaging technique, developed using the developer comprising alkali ion, specifically Ground, the alkali ion are hydroxide ion.
It should be noted that neutralisation treatment is carried out to the surface of word line layer 800 ' using alkaline developer due to above-mentioned, In order to avoid the introducing of foreign ion, in addition, after exposure imaging technique, the alkali can be removed in same step cleaning Property developer and the exposure imaging technique in the developer that uses, the developer is with using in the exposure imaging technique Developer is identical.
In the present embodiment, the alkaline developer is tetramethyl ammonium hydroxide solution, accordingly, the exposure imaging technique The middle developer used is tetramethyl ammonium hydroxide solution.
It should be noted that make the word line layer because the surface attachment of the word line layer 400 ' has the group of acidity 800 ' surfaces before developing process is exposed, are first entered in acidity using alkaline developer to the surface of word line layer 800 ' With the surface of word line layer 800 ' soda acid occurs for row neutralisation treatment, the developer ion for avoiding using in the exposure imaging technique Neutralization reaction and the problem of consume the developer ion, so as to improve the development effect of the developer, make the exposure aobvious The developer of shadow technique fully develops to the photoresist layer, is removed the photoresist layer of the logic area II, avoids There is photoetching glue residua on the surface of word line layer 800 ' of logic area II, and then reduces quantity the defects of when developing visual inspection.
As shown in fig. 6, the defects of showing different samples after exposure imaging technique quantitative comparison schemes.Wherein, X-axis representative sample Product, Y-axis represent defects count.Sample shown in the E of region is surface treated sample, the sample outside the E of region be without The sample of surface treatment is crossed, quantity may be up to 1000 the defects of without the sample of surface treatment when developing visual inspection, and pass through The defects of sample of surface treatment is when developing visual inspection quantity is less than 100, or even close to zero.Thus, it will be seen that by table Face processing after sample when developing visual inspection the defects of quantity be decreased obviously.
With reference to reference to figure 5, step S5 is finally performed, using the patterned photoresist layer as mask, removes the logic The word line layer 800 ' (as shown in Figure 4) in area II, wordline 800 is formed in memory cell areas I.
The wordline 800 is used to attract the carrier being stored in the floating gate layer 600, and described float is stored in so as to cause Carrier in gate layer 600 is lost in, and reaches the effect of data erasing.
In the present embodiment, the technique for removing the word line layer 800 ' of the logic area II is plasma dry etch process.
It should be noted that due to before developing process is exposed, first using developer to the word line layer 800 ' Surface carries out neutralisation treatment, avoids the ion of developer that is used in the exposure imaging technique and the surface of word line layer 800 ' Generation acid-base neutralization reaction and the problem of consume the developer ion, so as to improve the development effect of the developer, avoid There is photoetching glue residua on the surface of word line layer 800 ' of logic area II, avoids the word line layer 800 ' of the logic area II because of the light remained The problem of photoresist layer blocks and is difficult to remove, makes the word line layer 800 ' of logic area II can be removed completely, and then improves flash memory The yield of structure.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (9)

  1. A kind of 1. manufacture method of flash memory structure, it is characterised in that including：
    Substrate is provided, the substrate includes logic area and memory cell areas；
    Word line layer is formed over the substrate；
    Neutralisation treatment is carried out to the wordline layer surface using the developer comprising alkali ion；
    After carrying out the neutralisation treatment, patterned photoresist layer is formed in the wordline layer surface by exposure imaging technique, The patterned photoresist layer exposes the wordline layer surface of the logic area；
    Using the patterned photoresist layer as mask, the word line layer of the logic area is removed, wordline is formed in memory cell areas.
  2. 2. the manufacture method of flash memory structure as claimed in claim 1, it is characterised in that the material of the word line layer is heavy doping Polysilicon.
  3. 3. the manufacture method of flash memory structure as claimed in claim 1, it is characterised in that using developer to the word line layer table Face was carried out in the step of neutralisation treatment, and the developer is alkaline developer.
  4. 4. the manufacture method of flash memory structure as claimed in claim 3, it is characterised in that the alkaline developer is hydroxide four Methyl ammonium salt solution.
  5. 5. the manufacture method of flash memory structure as claimed in claim 4, it is characterised in that the tetramethyl ammonium hydroxide solution Mass concentration is 2% to 2.5%.
  6. 6. the manufacture method of flash memory structure as claimed in claim 1, it is characterised in that using developer to the word line layer table Face was carried out in the step of neutralisation treatment, and the temperature of the developer is 20 DEG C to 40 DEG C.
  7. 7. the manufacture method of flash memory structure as claimed in claim 1, it is characterised in that the alkali ion be hydroxyl from Son.
  8. 8. the manufacture method of flash memory structure as claimed in claim 1, it is characterised in that remove the word line layer of the logic area Technique is plasma dry etch process.
  9. 9. the manufacture method of flash memory structure as claimed in claim 1, it is characterised in that the developer and the exposure imaging The developer used in technique is identical.
CN201610033975.3A 2016-01-19 2016-01-19 The manufacture method of flash memory structure Active CN105428318B (en)

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CN105428318B true CN105428318B (en) 2018-02-16

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050042828A1 (en) * 2003-08-21 2005-02-24 Jung-Ho Moon Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device
CN101717939A (en) * 2008-10-09 2010-06-02 关东化学株式会社 Alkaline aqueous solution composition for treating a substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050042828A1 (en) * 2003-08-21 2005-02-24 Jung-Ho Moon Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device
CN101717939A (en) * 2008-10-09 2010-06-02 关东化学株式会社 Alkaline aqueous solution composition for treating a substrate

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