CN105426324B

CN105426324B - The memory access control method and device of terminal device

Info

Publication number: CN105426324B
Application number: CN201410235544.6A
Authority: CN
Inventors: 湛振波
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2014-05-29
Filing date: 2014-05-29
Publication date: 2018-04-27
Anticipated expiration: 2034-05-29
Also published as: CN105426324A

Abstract

The memory access control method and device of a kind of terminal device, the memory include at least two access paths, the described method includes：According to the different product application form of terminal device, corresponding memory access patterns are selected to be allocated access request on each access path, memory access patterns include high performance mode, low-power consumption mode and balanced mode；High performance mode is suitable for realizing that the alternating expression of access request accesses in the whole memory space of memory；Low-power consumption mode is suitable for the whole memory space of memory is divided into the first sub- memory space corresponding with each access path by storage address scope, and the noninterlaced for realizing access request in each first sub- memory space accesses；Balanced mode can then take into account the advantages of both high performance mode and low-power consumption mode.Technical solution of the present invention can realize the requirements for access for meeting the types of applications of terminal device in flexibility, performance boost and power consumption control for memory.

Description

The memory access control method and device of terminal device

Technical field

The present invention relates to computer realm, the memory access control method and device of more particularly to a kind of terminal device.

Background technology

Increasingly abundanter with the application of consumption electronic product, the function that chip provides is also more and more, so for core Piece performance also has very high requirement.The processing speed of central processing unit (CPU, Central Processing Unit), also has Other are also more and more similar to the quantity of the bus master unit (Master) of CPU, and the access that each master is sent is to bandwidth Requirement it is also higher and higher, such memory gradually become efficiency bottleneck.Especially for mobile communication terminal device (such as hand Machine), on the one hand, as the high speed network formats such as Long Term Evolution (LTE, Long Term Evolution) are released, web database technology It is increasing；On the other hand, the multimedia of the reinforcement of multimedia function, such as 4k2k, HD high definition display resolution, to bandwidth It is it is required that higher and higher.

The access efficiency of traditional single channel memory technology is as shown in Figure 1, consumer (such as CPU bus masters unit) is needed Supplier's (memory) is wanted constantly to provide data.If consumer is excessive, will result in the performance of supplier becomes current bottle Neck, this is urgent problem.For this, it may be considered that whole using binary channels (Dual-channel) memory techniques lifting system The runnability of body.The access efficiency of dual access memory technology as shown in Fig. 2, by provide multiple suppliers and it is improved in Memory controller so that the degree of parallelism of transmission is strengthened, and the bandwidth of memory can be caused to be unlikely to very low.One transmission request can interlock It is assigned to supplier's (internal storage access passage) or supplier's (another internal storage access in the lower right corner in the lower left corner in Fig. 2 Passage).

Dual access memory technology is a kind of Memory control and administrative skill in fact, it depends on the Memory Controller Hub of chipset Have an effect, the bandwidth that can be provided two equivalent specifications memories in theory doubles.It is applied to take earliest It is engaged in device and workstation system, later in order to solve the increasingly poverty-stricken memory bandwidth bottleneck problem of desktop computer, it has gone to platform again The foreground of formula owner's plate technique.

Nowadays, as mobile terminal kind equipment is also increasingly prominent for the bottleneck problem of internal memory performance, dual access memory is visited Ask that control strategy also gradually has applied to mobile terminal kind equipment.However, due to common dual access memory access control policy For be more the equipment such as PC (PC, Personal Computer), and this kind equipment for power problems substantially Need not excessively be paid close attention to, so the general simply lifting in performance more paid close attention to, but for some power problems compared with For sensitive terminal device, existing internal storage access control strategy obviously can not be applicable in well；It is in addition, of the prior art Some binary channels, multichannel memory access control policy, which also exist, realizes the shortcomings that complex.

Therefore, the prior art can not be realized meets all kinds of of terminal device in flexibility, performance boost and power consumption control Using the requirements for access for memory.

The content of the invention

The problem to be solved in the present invention is that the prior art can not be realized and met in flexibility, performance boost and power consumption control Requirements for access of the types of applications of terminal device for memory.

To solve the above problems, technical solution of the present invention provides a kind of memory access control method of terminal device, it is described Memory includes at least two access paths, the described method includes：

According to the different product application form of the terminal device, corresponding memory access patterns are selected to exist access request It is allocated on each access path, the memory access patterns include high performance mode, low-power consumption mode and the first balance mould Formula；

The high performance mode is suitable for realizing that the alternating expression of access request accesses in the whole memory space of the memory；

The low-power consumption mode be suitable for by storage address scope by the whole memory space of the memory be divided into it is each The corresponding first sub- memory space of access path, the noninterlaced for realizing access request in each first sub- memory space are visited Ask；

First balanced mode is suitable for the whole memory space of the memory being divided into the first access region and the second visit Ask region, the alternating expression for realizing access request in first access region accesses, and it is right respectively that second access region includes It should be accessed in the sub- access region of each access path, the noninterlaced for realizing access request in every sub- access region.

Optionally, first access region and size and second access region that wherein alternating expression accesses is big It is small to be determined by system emulation and test.

Optionally, first access region and size and second access region that wherein alternating expression accesses is big It is small to determine to include by system emulation and test：

Go out application high to performance requirement in every application of the terminal device by system emulation and test statistics Quantity and each required storage size, determine the size of first access region with this, the memory it is whole The size that the size of memory space subtracts first access region is the size of second access region；

Corresponding bus master unit is sent out during high to performance requirement application operation described with test assessment by system emulation Go out the transmission characteristic of access request, the size of the alternating expression access is determined with this.

Optionally, the memory access patterns further include the second balanced mode, under second balanced mode, by storage The whole memory space of the memory is divided into the second sub- memory space corresponding with each access path by address realm, is accessed Request includes the extended address after extension process to target access address, by being translated into row address the extended address Code is with definite corresponding access mode；The access mode includes the first access mode and the second access mode, and described first visits It is to realize that the noninterlaced of access request accesses in each second sub- memory space to ask mode, and second access mode is The alternating expression for realizing access request in the 3rd access region accesses, and the access address in the 3rd access region is with alternating expression The size of access is unit, the virtual memory that the physical storage address alternative mapping of each second sub- memory space is formed Address.

Optionally, the storage address scope by the corresponding each piece choosing of each access path external physical memory it is big It is small to determine.

Optionally, the extension process, which includes adding the target access address, accesses selection extension bits, the access It is first access mode or second access mode to select extension bits to be suitable for identifying the access mode.

Optionally, the highest order for accessing selection extension bits and making an addition to the extended address.

Optionally, the memory access control method of the terminal device further includes：

The register for being suitable for configuring the size that the alternating expression accesses is set；

It is different for the transmission characteristic for the bus master unit for sending access request, phase is respectively configured by the register The size that the alternating expression answered accesses.

Optionally, the memory access control method of the terminal device further includes：Under second balanced mode, it will visit Ask that request is assigned to before corresponding access path, detect whether the corresponding storage address of the access path allows, and do not permitting Interrupt signal notice system is sent when perhaps.

Optionally, the memory access control method of the terminal device further includes：Realizing the noninterlaced of access request During access, if depositing the access path of unassigned access request in the given time, the access path is set to enter battery saving mode.

Optionally, each memory access patterns respective stored in the form of static allocation list is described in the terminal device Select corresponding memory access patterns to be allocated access request on each access path by configuring corresponding static state to match somebody with somebody Put table realization.

Optionally, for each access path, the size that alternating expression accesses is all equal.

Optionally, the terminal device is mobile communication terminal, and the mobile communication terminal includes Communication processor and should With processor, when the memory access patterns are low-power consumption mode, the Communication processor and application processor are sent Access request is allocated in different access paths respectively, and realizes that the noninterlaced of access request accesses.

Optionally, the products application form of the terminal device includes：Terminal device is in application for power consumption and property The sensitivity of energy.

To solve the above problems, technical solution of the present invention also provides a kind of internal storage access control device of terminal device, institute State memory and include at least two access paths, described device includes：

Selecting unit, suitable for the different product application form according to the terminal device, selects corresponding internal storage access mould Formula；

Storage unit, suitable for storing the memory access patterns, the memory access patterns include high performance mode, low work( Consumption pattern and the first balanced mode；

Control unit, suitable for being led to the selected memory access patterns of the selecting unit to access request in each access It is allocated on road；

Compared with prior art, technical scheme at least has the following advantages：

By the different product application form according to terminal device, simply, corresponding memory access patterns are configured flexibly Access request is allocated on each access path, high performance mode that the memory access patterns include, low can be made Power consumption mode and the first balanced mode, can adapt to high performance requirements, low-power consumption requirement respectively and take into account high-performance low-power-consumption It is required that terminal device different internal storage access demands, it is achieved thereby that meeting in flexibility, performance boost and power consumption control Requirements for access of the types of applications of terminal device for memory.

Further, by providing the second balanced mode in memory access patterns, high-performance and low work(can either be taken into account The internal storage access demand of consumption, and first balanced mode can be overcome to need just to can determine that each memory is visited based on emulation and test Ask the configuration parameter in region, and configure the shortcomings that parameter is once fixed among chip but can not arbitrarily change, any bus Main control unit can be not only restricted to chip, be optimized according to the effect that actual software is adjusted.

Under second balanced mode, by setting the register for being suitable for configuring the size that the alternating expression accesses, pin The transmission characteristic of bus master unit to sending access request is different, and corresponding alternating expression, which is respectively configured, with the register visits The size asked, so that each bus master unit can have the size that the peculiar alternating expression of oneself accesses.

Internal storage access under the second balanced mode of protection is monitored by address, so as to play safety guarantee, debugging optimizes Benefit.

When the noninterlaced for realizing access request accesses, by monitoring the access situation of each access path, make pre- timing The access path of interior unassigned access request enters battery saving mode, so as to achieve the purpose that to save power consumption.

Brief description of the drawings

Fig. 1 is the schematic diagram of the access efficiency of single channel memory technology；

Fig. 2 is the schematic diagram of the access efficiency of dual access memory technology；

Fig. 3 is the flow diagram of the memory access control method of the terminal device of the embodiment of the present invention；

Fig. 4 is the structure diagram of the dual access memory of the embodiment of the present invention；

Fig. 5 is the schematic diagram of the internal storage access configuration of the high performance mode of the embodiment of the present invention；

Fig. 6 is the schematic diagram of the internal storage access configuration of the low-power consumption mode of the embodiment of the present invention；

Fig. 7 is the schematic diagram of the internal storage access configuration of the first balanced mode of the embodiment of the present invention；

Fig. 8 is the schematic diagram of the internal storage access configuration of the second balanced mode of the embodiment of the present invention.

Embodiment

It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

In order to meet visit of the types of applications of terminal device for memory in flexibility, performance boost and power consumption control Ask demand, the embodiment of the present invention provides a kind of memory access control method of terminal device, and the memory includes at least two visits Ask passage, by the different product application form according to the terminal device, select corresponding memory access patterns please to accessing Ask and be allocated on each access path, the memory access patterns include high performance mode, low-power consumption mode and balance mould Formula, can adapt to different access demand of the types of applications for memory of the terminal device.This method uses foolproof Mode realizes multichannel memory access control, lifting total system runnability at the same time so that can with flexible configuration, and Also it disclosure satisfy that the demand of low-power consumption in power consumption, be especially suitable for mobile terminal device.

As shown in figure 3, the memory access control method of terminal device provided in an embodiment of the present invention includes：

Step S10 is performed, judges terminal device for which kind of products application form；In the present embodiment, the terminal device Products application form includes：Terminal device is in application for the sensitivity of power consumption and performance；For the sensitive journey of power consumption Degree is higher, then shows terminal device requirement with low-power consumption in application, higher for the sensitivity of performance, then shows end End equipment requirement with high performance in application, it is higher for the sensitivity of power consumption and performance, then show that terminal is set It is standby in application with the requirement for taking into account high-performance and low-power consumption；

If the products application form of terminal device is high performance requirements, step S21 is performed, selects high performance mode to visiting Ask that request is allocated on each access path；The high performance mode is suitable for realizing in the whole memory space of the memory The alternating expression of access request accesses；

If the products application form of terminal device is low-power consumption requirement, step S22 is performed, selects low-power consumption mode to visiting Ask that request is allocated on each access path；The low-power consumption mode is suitable for pressing storage address scope by the whole of the memory A memory space is divided into the first sub- memory space corresponding with each access path, real in each first sub- memory space The noninterlaced of existing access request accesses；

If the products application form of terminal device is taken into account for the requirement of both high-performance and low-power consumption, step S23, choosing are performed Balanced mode is selected to be allocated access request on each access path；In the present embodiment, the balanced mode includes first Balanced mode, first balanced mode are suitable for the whole memory space of the memory being divided into the first access region and the second visit Ask region, the alternating expression for realizing access request in first access region accesses, and it is right respectively that second access region includes It should be accessed in the sub- access region of each access path, the noninterlaced for realizing access request in every sub- access region.

In the present embodiment, the terminal device is specially mobile communication terminal device, such as mobile phone, has communication module Tablet computer etc., in other embodiments, the terminal device can also be palm PC, car-mounted terminal, desktop computer etc..Institute Memory is stated with more common Double Data Rate synchronous DRAM (DDR SDRAM, Double Date Rate now Synchronous Dynamic Random Access Memory), illustrate exemplified by abbreviation DDR memories, other embodiment In, the memory can also be the memory of other support binary channels or multichannel memory technology.

Above-mentioned memory access patterns are described in detail below in conjunction with the accompanying drawings.

It should be noted that in the present embodiment to illustrate exemplified by supporting the DDR of dual access memory access technique, but this hair The memory access control method for the terminal device that bright embodiment provides is not limited solely to binary channels, can be that multichannel (wraps Containing more than two internal storage access passages).

The structure of the dual access memory of the embodiment of the present invention is as shown in figure 4, DDR controller A, DDR PHY A and A0, A1 An internal storage access passage is formed, DDR controller B, DDR PHY B and B0, B1 form another internal storage access passage, pass through One layer of i.e. interconnection logic layer (interconnect logic) on DDR controller comes from multiple Master (such as to distribute M0, M1 ... Mn shown in Fig. 4) read-write requests (i.e. described access request).

Certainly, in the present embodiment, an internal storage access passage corresponds to a DDR controller respectively, in other embodiment In, DDR controller A and DDR controller B can also be developed and be merged into a DDR controller, i.e., all internal storage access passages are all right A DDR controller is answered, but the function of DDR controller offer is the function with all DDR controller offers before merging The same.In addition, in other embodiments, the function that interconnection logic layer is realized can also be also incorporated into a DDR controller The inside is gone.Therefore, dual access memory realizes that structure is not limited to the example that the present embodiment is provided.

With continued reference to Fig. 4, DDR PHY A and DDR PHY B are that binary channels DDR is necessary, and " DDR PHY " are processing Component in terms of sequential and in terms of frequency, corresponding with DDR controller, how many general DDR controller is a with regard to how many DDR PHY, because herein " implication of DDR PHY " and effect are known to those skilled in the art, are not described in detail.

In addition, each internal storage access passage usually all has piece choosing (CS, Chip Select), for selecting external DDR Physical memory, generally, piece choosing are exactly the DDR slice, thin pieces that selection outside connects, using the initialization object as future.A0 in Fig. 4 First CS of access path 0 is represented, A1 represents second CS of access path 0；B0 represents first CS of access path 1, B1 represents second CS of access path 1.In Fig. 4, for different CS, distinguished respectively with different filling patterns with showing, Wherein A0 represents that A1 is represented with lattice filling with blank filling, and B0 represents that B1 fills table with backslash with the filling of positive oblique line Show.Certainly, in actual implementation, each access path can also all have more CS.

In the present embodiment, all the structure of dual access memory with reference to shown in Fig. 4 is said for every kind of memory access patterns It is bright.

(1) high performance mode

The high performance mode is adapted to the terminal device insensitive to power consumption such as super phone or tablet computer, that is, Say, this kind equipment is since battery capacity is larger, so being generally more concerned with runnability, then seems relatively less for power consumption It is sensitive.Under the high performance mode, the alternating expression by realizing access request in the whole memory space of the memory accesses, So as to realize the concurrent access of each access path to the full extent, system performance is set to get a promotion.

It should be noted that the alternating expression accesses is properly termed as interleaving access (interleaving) or interactive mode again Access, be to speed up a kind of memory access technology of parallel work-flow of memory speed.In interleaving access mode, memory is to be in In different blocks, as long as read-write operation will carry out in two blocks, they can be carried out at the same time.For example, will deposit Odd address and the even address part of storage body separate, and when such current byte is refreshed, can not influence next byte Access.The implication that is accessed due to the alternating expression and it act as known to a person skilled in the art, is not described in detail herein.

When an access request comes from interconnection (Interconnect), it is distributed to by the logic on Interconnect Two access paths as shown in Figure 4.For convenience of explanation, it is assumed that only have A0 and B0 to connect exterior DDR physical memories in Fig. 4, The size (interleaved size) so just accessed according to the alternating expression of regulation accesses the corresponding memory blocks of A0 and B0 respectively Domain, by carrying out concurrent access to improve system performance.

The internal storage access configuring condition of the high performance mode is as shown in figure 5, each adjacent grid in Fig. 5 represents The external continuous storage address of DDR physical memories, the storage size of each grid are the size that alternating expression accesses.With figure Filling pattern in 4 represented by the two CS of A0 and B0 is corresponding is, for the memory space of blank spacer-frame subrepresentation Access derives from A0, and the access for the memory space of positive oblique line spacer-frame subrepresentation comes from B0.Fig. 5 is software and hardware mould The address space view that block can see, for software and hardware module be it is transparent, they be not aware that data source in Which access path.

In the present embodiment, under the high performance mode, the size that alternating expression accesses is equal, that is to say, that in Fig. 5 The area of blank filling grid is equal to the area of positive oblique line filling grid.

Under the high performance mode, all memory spaces all carry out alternating expression access, are usually highest for performance , but power consumption is larger, because most access has all been distributed on two access paths so that two access paths all cannot Into battery saving mode, so as to consume excessive power consumption.Those skilled in the art know that the battery saving mode generally can be by DDR Controller provides, such as selects to close some clocks and power supply according to DDR controller, to achieve the purpose that to save power consumption.

It should be noted that Fig. 5, which illustrate only A0, has connect exterior DDR physical memories, B0 has connect exterior DDR physical memories Situation, for A1 can also external DDR physical memories external with A0 of equal value in the case of, B1 can also external equivalence it is external with B0 The situation of DDR physical memories.Certainly, it will be readily appreciated by those skilled in the art that in other embodiments, if each access Passage all includes more CS, then the situation of each external DDR physical memories of CS may be referred to the side provided in the present embodiment Formula.

(2) low-power consumption mode

The low-power consumption mode is more suitable for those because limited battery capacity or cruising ability requirement are high and more quick to power consumption The mobile terminal device of sense.Under the low-power consumption mode, the whole memory space of the memory is divided by storage address scope For the first sub- memory space corresponding with each access path, the non-of access request is realized in each first sub- memory space Alternating expression accesses.In the present embodiment, the storage address scope is by the external physics of the corresponding each piece choosing institute of each access path The size of memory determines.

Compared with the high performance mode, the characteristics of low-power consumption mode is maximum, is realized most in whole memory space Small alternating expression accesses.The internal storage access configuring condition of the low-power consumption mode is as shown in fig. 6, it is still assumed that only A0 and B0 connect Exterior DDR physical memories, then under low-power consumption mode, whole memory space includes two parts access region, one is A0 Memory space corresponding to external DDR physical memories, this is determined according to the storage address scope of the external DDR physical memories of A0 With 0 corresponding first sub- memory space of access path, i.e. in Fig. 6 with blank filling grid represented by region, The second is the memory space corresponding to the external DDR physical memories of B0, this is the storage address model according to the external DDR physical memories of B0 Identified another described first sub- memory space corresponding with access path 1 is enclosed, i.e. positive oblique line fills grid institute table in Fig. 6 The region shown.

From fig. 6, it can be seen that the whole memory space formed for the summation by the external DDR physical memories of A0 and B0 Lai Say, be accomplished that twin-channel alternating expression is visited between the corresponding first sub- memory spaces of A0 the first sub- memory space corresponding with B0 Ask, and inside the corresponding first sub- memory space of A0 and B0, then realized in a manner of noninterlaced accesses.

Those skilled in the art know, for the read-write requests of random access memory, can all include its storage to be accessed Address, for Memory Controller Hub, program will access any storage address, and the storage address of arriving goes for data to program.

By access request, the storage address to be accessed is known as target access address in the present embodiment.In the low-power consumption mode Under, since the storage address scope of the first sub- memory space corresponding with each access path is all a sheet of continuous storage Location, the target access address included according to some access request, judges that it is in which storage address scope, can be true The fixed access request should access the corresponding first sub- memory space of A0 corresponding first sub- memory space or B0.

For example, general CPU, which is accessed, can only send a bit of continuous storage address access, and each access path pair The storage address scope for the first sub- memory space answered is usually very big, then otherwise the small sector address that CPU is sent usually falls In the corresponding regions of A0 as shown in Figure 6, otherwise fall region corresponding in B0, it is assumed that fall in corresponding A0 regions, then just only Access corresponding A0 regions, it is assumed that fall region corresponding in B0, then just only access the corresponding regions of B0.

In actual implementation, it is assumed that the size of the external DDR physical memories of A0 in Fig. 6 is 1G, the external DDR physical memories of B0 Size be 1G, and the storage address of external DDR physical memories is continuous between the two, then any Mater read and write access 0-1G storage address will all fall the first sub- memory space corresponding in A0, accessing the storage address of 1G-2G will all fall at B0 pairs The the first sub- memory space answered.In this way, when software system design is carried out, designer can be according to demand by memory Access arrangement and be assigned to the corresponding first sub- memory spaces of A0 or B0.

It should be noted that in other embodiments, the size of the respective external DDR physical memories of A0 and B0 can not also phase Deng, and the storage address of external DDR physical memories can also be discrete between the two, such as：In the external DDR physics of A0 The size deposited is 1G, and corresponding storage address scope is 0-1G, and the size of the external DDR physical memories of B0 is 2G, corresponding to deposit Storage address realm is 2-4G.

In the present embodiment, since the terminal device is mobile communication terminal, and mobile communication terminal now is much all It can include Communication processor and application processor, then, then can be by institute when the memory access patterns are low-power consumption mode State the access request that Communication processor and application processor are sent and be allocated in different access paths respectively, and realize access request Noninterlaced access, so as to achieve the purpose that power consumption control.

As an example it is assumed that the application processor definition of mobile communication terminal (such as mobile phone) only accesses the corresponding areas of A0 Domain, and defined for Communication processor and only access the corresponding regions of B0, the size in A0 and the corresponding regions of B0 can not phase Deng.In general, A0 corresponding regions are not accessed when application processor is generally in idle condition (idle), Communication processor is It can be spaced with base station synchronization and access the corresponding regions of B0, can so cause the corresponding regions of most of the time A0 to enter power saving Pattern, so as to achieve the purpose that to save power consumption；And the Master of high bandwidth requirements is needed for multimedia etc., then it can distribute straight Memory access (DMA, Direct Memory Access) physical memory is connect on the corresponding regions of A0 and B0, that is, at the same time Use two regions represented by the sub and positive oblique line filling grid of blank spacer-frame in Fig. 6, so that can meet high bandwidth need Ask.

(3) first balanced modes

Although high performance mode and low-power consumption mode there are it is respective the advantages of, there is also respective deficiency, therefore can be with Both of which above is combined by consideration, obtains the mixed mode of high performance mode and low-power consumption mode, or is referred to as to balance Pattern, can obtain the advantages of above two kinds of memory access patterns protrude under the pattern at the same time：Performance and power consumption.Described first is flat Weighing apparatus pattern can be adapted to those needs to take into account the mobile terminal device of performance boost and power consumption control.

First balanced mode is a kind of implementation of the balanced mode, described interior under first balanced mode The whole memory space deposited includes the first access region and the second access region, and access request is realized in first access region Alternating expression access, second access region includes corresponding respectively to the sub- access region of each access path, in every height Access region realizes that the noninterlaced of access request accesses.

The internal storage access configuring condition of first balanced mode is as shown in fig. 7, for convenience of explanation, it is still assumed that only A0 and B0 has connect exterior DDR physical memories, then under the first balanced mode, whole memory space includes two large divisions access region Domain, one is first access region, i.e., being filled out with multiple staggeredly adjacent blank filling sub-box and positive oblique lines shown in Fig. 7 The access region that sub-box is formed is filled, the size of the access region is represented with " size0 ", the second is second access region Domain, i.e., a blank shown in Fig. 7 fills big grid and a positive oblique line fills the access region that big grid is formed, the access Region includes a sub- access region for corresponding to access path 0, which is represented with " An ", the sub- access region Size represents that the access region further includes another sub- access region for corresponding to access path 1, the sub- access with " size1 " Region represents that the size of the sub- access region is represented with " size2 " with " Bn ".

For first access region, access of the access request to memory is realized in a manner of alternating expression accesses, with Fig. 7 The corresponding access for being, region represented by sub-box being filled for blank of filling pattern represented by middle the two CS of A0 and B0 A01, a02 in A0, such as Fig. 7, the access for region represented by positive oblique line filling sub-box come from B0, such as B01, b02 in Fig. 7.The size in region is the size that alternating expression accesses represented by each sub-box, can also use " entry Size " is indicated (not shown in Fig. 7).The specific implementation of first access region is accessed in a manner of alternating expression accesses also The associated description in the high performance mode is may be referred to, both realizes that alternating expression accesses in predetermined memory space, Difference, the former predetermined memory space is whole memory space, and simply whole storage is empty for the predetermined memory space of the latter Between in a part.

For second access region, access of the access request to memory is realized in a manner of noninterlaced accesses, with Filling pattern in Fig. 7 represented by the two CS of A0 and B0 is corresponding to be, the son represented by big grid is filled for blank and is visited Ask that the access of region An derives from A0, the access that the sub- access region Bn represented by big grid is filled for positive oblique line comes from B0.The specific implementation of second access region is accessed in a manner of alternating expression accesses to be referred in the low-power consumption mode Associated description, both predetermined memory space realize noninterlaced access, otherwise varied, the former predetermined storage Space is whole memory space, and the predetermined memory space of the latter is the part in whole memory space.

Under first balanced mode, size (such as size0) for the first access region and wherein alternating expression The definite right and wrong of the size (such as entry size) of access and the size (such as size1+size2) of second access region It is often important, because this directly influences desired level of the terminal device for performance boost and power consumption control.

In the present embodiment, first access region and the wherein size of alternating expression access and second access region The size in domain is determined by system emulation and test.

In the present embodiment, by system emulation and test, determine the first access region and wherein alternating expression access it is big The small and size of second access region, that is, determine which region is the region that bulk is used for realization alternating expression access (i.e. size0), the size that alternating expression accesses for it is how many relatively it is appropriate (the static configuration size equal to any Master, i.e., Entry size), bulk be not carried out alternating expression access region for it is much (or for be used for realization noninterlaced access area Domain, i.e. size1+size2).

When it is implemented, size and second access region that first access region and wherein alternating expression access Size by system emulation and test determine can include：

After system emulation and test, if size0 is determined, due to the size of the whole memory space of memory That can select the size of external physical memory according to all and be readily available, then the whole memory space of memory it is big Small to subtract size0 be then size1+size2, is respectively how many size as size1 and size2, then by corresponding access path Piece selects the size of external physical memory to determine, if the piece of two access paths selects the size phase of external physical memory Deng, then size1 and size2 is also equal, if the piece of two access paths selects the size of external physical memory not phase Deng, then also need to be determined according to entry size, since entry size are can to assess institute by system emulation and test The transmission characteristic that corresponding bus master unit sends access request when stating the application operation high to performance requirement comes definite, and institute It is again usually equal to state the size that the alternating expression in the first access region accesses, then the piece of the corresponding access paths of size1 It is size1 that the size of the external physical memory of choosing, which subtracts the result obtained after [(size0) * (1/2)], similarly, size2 phases The piece of corresponding access path selects the size of external physical memory to subtract the result obtained after [(size0) * (1/2)] size2。

On sending the transmission characteristic of access request by system emulation and test assessment Master, the alternating expression is determined The size of access, it is how many that can specifically assess Master and send most sizes of access, whom highest frequency is, whose is excellent First level highest.For example image processor once accesses the access for sending 128 bytes (Byte, is usually represented with " B "), still CPU at most can only once access 64 Byte, because image procossing is bad, human eye can observe flicker, so general just select The size that 128 Byte are accessed as alternating expression.Which kind of actual situation is best, by the emulation testing during chip development Lai really Surely select much.

Present inventor thinks, if test is abundant, or very clear application scenarios, it is possible to obtain above-mentioned parameter (such as size0, entry size, size1+size2), so that performance and power consumption all reach ideal value.For example, make performance It is required that high application scenarios, are positioned over the first access region for being used for realization alternating expression and accessing as shown in Figure 7, and make performance will Ask not high application scenarios only to access the An in the second access region or access Bn.Access An and access Bn and place respectively less The application scenarios accessed at the same time, can so make it that only An is accessed and Bn does not have when the first access region does not access Any access, then the corresponding access paths of Bn can enter battery saving mode.Conversely, when the first access region does not access, Only Bn is accessed and An does not have any access, then the corresponding access paths of An can enter battery saving mode.

In actual implementation, above-mentioned high performance mode, low-power consumption mode and the first balanced mode can be matched somebody with somebody by static state The form respective stored of table is put in the terminal device, the corresponding memory access patterns of selection are to access request each It is allocated on access path and is realized by configuring corresponding static allocation list.

Specifically, describe how access request carries out in binary channels or multichannel by defining multiple static allocation lists Distribution, after static allocation list completes configuration, energy height optimization, software configuration only need when chip generates specific logic Corresponding configuration is carried out when system starts according to different products application forms.

In the present embodiment, so-called " static configuration ", that is to say, that terminal device start is completed after starting, for having completed Configuration cannot change, the access request that Master is sent can be assigned on corresponding access path according to configuration, this pass System is static.For example under the low-power consumption mode, for some address, the corresponding access paths of A0 are always accessed, and it is right The corresponding access paths of B0 are then always accessed in another address.For another example under first balanced mode, there is most Region be it is total access a passage, it is short grained division to have most, and some addresses access the corresponding access paths of A0, Some addresses access the corresponding access paths of B0.

Static allocation list is that requirement chip realizes one section of configuration register, and then software configuration is good.Table 1 is static allocation list A kind of example：

Table 1

(4) second balanced modes

Since first balanced mode needs, based on the size for obtaining alternating expression access on the basis of emulation and test, to go back There is which region to need to carry out alternating expression access, which region need not carry out alternating expression access, be respectively necessary for specifying fixation Size.Once after chip production, after software selects this memory access patterns, the concrete configuration parameter (example under the pattern Such as size0, entry size, size1 and size2) it can not change.

To solve the above problems, in the present embodiment, the balanced mode can also include the second balanced mode.Described Two balanced modes are another implementations of the balanced mode, under second balanced mode, by storage address scope The whole memory space of the memory is divided into the second sub- memory space corresponding with each access path, is wrapped in access request The extended address after extension process to target access address is included, by being determined to extended address progress address decoding Corresponding access mode；The access mode includes the first access mode and the second access mode, and first access mode is The noninterlaced for realizing access request in each second sub- memory space accesses, and second access mode is to be visited the 3rd Ask that the alternating expression for realizing access request in region accesses, the access address in the 3rd access region is with the big of alternating expression access Small is unit, the virtual memory address that the physical storage address alternative mapping of each second sub- memory space is formed.

Fig. 8 shows the internal storage access configuring condition of second balanced mode, it is assumed that still only has A0 and B0 to connect outer Portion's DDR physical memories, then under the second balanced mode, whole memory space includes two parts access region, one is outside A0 The memory space corresponding to DDR physical memories is connect, this is according to determined by the storage address scope of the external DDR physical memories of A0 With 0 corresponding second sub- memory space of access path, i.e. area represented by thick sash is filled with blank in Fig. 8 Domain, the second is the memory space corresponding to the external DDR physical memories of B0, this is the storage according to the external DDR physical memories of B0 Another described second sub- memory space corresponding with access path 1 determined by the scope of location, the i.e. just thick frame of oblique line filling in Fig. 8 Region represented by grid.

Although from the point of view of the division of the whole memory space singly formed with regard to external DDR physical memories, described second is flat Weighing apparatus pattern is more similar with the low-power consumption mode, still, for the access side of two the second sub- memory spaces in the present embodiment Formula but and differs, the access mode of the latter with the access mode under the low-power consumption mode for two the first sub- memory spaces Uniquely determine, and the former access mode is not then unique.In the present embodiment, the access request that Master is sent includes The storage address to be accessed form and common target access address in the prior art it is different, in the second balanced mode Under, what access request included is the extended address after extension process to target access address, by the extension ground Location carries out address decoding to determine corresponding access mode, and the access mode includes two kinds, and one kind can be realized in each institute State the second sub- memory space realize access request noninterlaced access (i.e. described first access mode), it is another then can be real Now the alternating expression in whole memory space accesses (i.e. described second access mode).

For first access mode, it is similar with the access control scheme under the low-power consumption mode, can pass through The mode of address decoding, identifies the address part that addressing is adapted in the extended address that some access request is included, and judges It is in which storage address scope, can determine that the access request should access the corresponding second sub- memory spaces of A0 also It is the corresponding second sub- memory spaces of B0.The specific implementation of first access mode may be referred under the low-power consumption mode The associated description of access control is deposited, is not described in detail herein.

For second access mode, in order to realize that the alternating expression in whole memory space accesses, therefore An independent virtual memory space defined in the present embodiment, i.e., described 3rd access region, as shown in Figure 8 is " virtual to visit Ask region ", it is not actual amount of physical memory, and a kind of simply virtual controlling, the access in the virtual access region Location is in units of the size that alternating expression accesses, and by way of address of cache, the physics of each second sub- memory space is deposited The virtual memory address that storage address interleaving mapping forms, therefore the access address in the virtual access region is deposited based on the second son Virtual memory address determined by the physical storage address in space is stored up, and the size in the virtual access region is whole storage The size in space.For example, it is assumed that the size of the corresponding second sub- memory spaces of A0 is 1G, the corresponding second sub- memory spaces of B0 Size is 1G, then the size in virtual access region is 1G+1G=2GB, is illustrated in the present embodiment as example.

Fig. 8 can be referred to, in " the virtual access region " shown on the left of Fig. 8, each sub-box is a virtual memory Address, its size are the size that alternating expression accesses, and lowermost sub-box is the initial address in virtual memory address, i.e. " 0 ground Location ", the mapping between virtual memory address in the physical storage address and virtual access region of each second sub- memory space For relation as shown in the four-headed arrow in Fig. 8, the address k0 in the corresponding second sub- memory spaces of A0 is mapped as virtual memory address In 0 address, the address k2 in the corresponding second sub- memory spaces of B0 is then mapped as the successor virtual adjacent with " 0 address " and stores Address (assuming that be known as " 1 address ", Fig. 8 is not shown), the address k1 in the corresponding second sub- memory spaces of A0 are mapped as and " 1 ground The adjacent successor virtual storage address in location " (assuming that be known as " 2 address ", Fig. 8 is not shown), in the corresponding second sub- memory spaces of B0 Address k3 be mapped as with " 2 address " adjacent successor virtual storage address, and so on, deposited so as to fulfill by each second son The physical storage address alternative mapping for storing up space is each virtual memory address in virtual access region.

In actual implementation, DDR controller is by way of address decoding, after determining corresponding access mode, according to each The mapping relations between virtual memory address in the physical storage address and virtual access region of a second sub- memory space, just It can determine the storage address of the external DDR physical memories finally accessed, therefore, realize to access in the virtual access region and ask The alternating expression asked accesses, and is the equal of that the alternating expression realized in whole amount of physical memory accesses.

By the introduction to above two access mode it is recognized that while the address that two kinds of access modes finally access all is outer The storage address of DDR physical memories is connect, but is more intuitively understood to have to both access modes, in the present embodiment In the region being made of shown on the right side of Fig. 8 two thick sashes that will can directly be accessed under first access mode Referred to as normal areas, and this void in shown virtual access region on the left of Fig. 8 that will be accessed under second access mode Intend control and be known as access region of interlocking at a high speed.

In the present embodiment, the extension process, which specifically includes to add the target access address, accesses selection extension bits, It is first access mode or second access mode that the access selection extension bits, which are suitable for identifying the access mode,. For example, if it is 0 to access selection extension bits, then it represents that access mode is the first access mode, if it is 1 to access selection extension bits, Expression access mode is the second access mode.

In the present embodiment, for the ease of identification, the highest order for accessing selection extension bits and making an addition to the extended address. In other embodiments, the time high-order of the extended address as described access can also be selected extension bits, and by the expansion The highest order of site of an exhibition location is reserved, for other purposes.It should be noted that since those skilled in the art are accustomed to visiting some Ask that low level in address is used to address, thus by it is extra it is increased access selection extension bits be set in the high position of extended address can The extended address is set to have more versatility.

Further, since the transmission characteristic that each Master is sent is different, in order to allow each Master to have oneself The size that peculiar alternating expression accesses, therefore, the memory access control method of the terminal device further includes：Set and be suitable for configuration institute State the register of the size of alternating expression access；It is different for the transmission characteristic for the bus master unit for sending access request, pass through The size that corresponding alternating expression accesses is respectively configured in the register.

In actual implementation, the table of an extended address highest order and the size extension bits of alternating expression access can be defined In interconnection logic, example such as table 2：

Table 2

The memory access process under second balanced mode is exemplified below：

Such as table 2, extended address highest order indicates whether that access access region of interlocking at a high speed, such as the position then represents for " 1 " Access region of interlocking at a high speed is accessed, which then represents to access normal areas for " 0 ".The size extension bits that alternating expression accesses represent each The size that class Master is accessed using the alternating expression of which kind of size, for example it is 1,512B 2 to define 256B.

Assuming that when some Master A sends access, since the size that its corresponding alternating expression accesses is configured to 1, then such as Fruit falls can access in access region of interlocking at a high speed, the then size that alternating expression accesses by interval of 256B.Assuming that it have issued 0 ground The access of location, then can directly have access to blank shown on the right side of Fig. 8 and fill the initial address in region represented by thick sash (commonly Region) k0.Assuming that the access of 0+256B is have issued, since extended address highest order is 0, then still fall in normal areas The local k1 of 256B offsets, similarly, shown normal areas on the right side of Fig. 8 can all be fallen by sending the access of 0-2GB.As Master A Highest order is sent as 1 (can fall in access region of interlocking at a high speed, subsequent space is that possess staggeredly access function), for extension Low 32 in address be 0 access, then the high speed that can fall in virtual memory address is interlocked access region, finally has access to thing Manage storage address k0.It is 1 when Master A send highest order, for the access that low 32 in extended address are 256B, then The high speed that can fall in virtual memory address is interlocked access region, finally has access to physical storage address k2.

To sum up, at least there are following characteristics for second balanced mode：

1) any Master can be not only restricted to chip, be optimized according to the effect that actual software is adjusted, you can with Determine to access interlock at a high speed access region or normal areas by the selection of address.Under this internal storage access mode, use The size of the corresponding external DDR of one access path of minimum under more access paths is equivalent in the region for realizing alternating expression access, It is very flexible.

2) transmission characteristic sent due to each Master is different, such as most of access that CPU is sent is cache lines The size of (Cache line), such as 64B, and other Master send the size of 128B, so can have for each Master The size that the peculiar alternating expression of oneself accesses.

Therefore, by providing the second balanced mode in memory access patterns, high-performance and low-power consumption can either be taken into account Internal storage access demand, and first balanced mode can be overcome to need just to can determine that each internal storage access area based on emulation and test The configuration parameter in domain, and configure the shortcomings that parameter is once fixed among chip but can not arbitrarily change, any bus master Unit can be not only restricted to chip, be optimized according to the effect that actual software is adjusted.

In addition, under second balanced mode, since the DDR somewheres of physics can be accessed by 2 different addresses Location, that is to say, that there are 2 addresses to correspond to a real physical address, can all go to have access to this according to virtual address true Existing physical address, once software has many problems, will cause to debug relatively difficult, therefore there are certain safety wind Danger.To solve the problems, such as this, the memory access control method of the terminal device provided in this embodiment further includes：Described second Under balanced mode, before access request is assigned to corresponding access path, detecting the corresponding storage address of the access path is No permission, and interrupt signal notice system is sent when not allowing.In the specific implementation, described detection access path is corresponding Whether storage address allows the selection of scope, read and write operation by address to be judged.

Skilled artisans appreciate that it is, in actual implementation, to be supervised by increasing bus address in DDR controller Module (bus monitor) is controlled, security monitoring can be carried out to the address of access, so as to reduce above-mentioned security risk.The module Function it is very simple, by before access request to be distributed to some specific access path, detecting whether its address allows, such as Fruit does not allow to be issued by interrupt notification system, and the high speed that can so distinguish is will access virtual controlling is interlocked access region, Still go to access normal areas.The detection whether address is allowed to substantially is embodied as：Scope there is provided address, read and write Selection, when chip finds to have reading or write operation, can trigger interruption and tell programmer, perhaps there is illegal visit here Ask.This mode can play safety guarantee, debug the benefit of optimization.

It should be noted that in the present embodiment, for each access path, the size that alternating expression accesses is all equal, such as This can make it that the overall utilization rate of the corresponding external DDR physical memories of each access path is higher.Those skilled in the art can Understand, in other embodiments, for any two access path, the size that alternating expression accesses can not also be equal, i.e., In above-mentioned several memory access patterns, it can be adapted to asymmetric DDR, specific address distribution depends on external DDR physics The actual size of memory.The maximum region of interactive visit is that the DDR being equivalent under multichannel under a minimum access path is big It is small.

In addition, in the present embodiment, the memory access control method of the terminal device further includes：Realizing access request Noninterlaced access when, if depositing the access path of unassigned access request in the given time, make the access path into Enter battery saving mode.

, can be by adding a chip mechanism, there is provided a register is configured to software in actual implementation.Such as A register for being used to record idle (idle) time is provided, software configuration is 200 milliseconds (ms), when 200ms does not have Master accesses certain access path, then the access path will enter battery saving mode.

Corresponding to the memory access control method of above-mentioned terminal device, the present embodiment also provides a kind of memory of terminal device Access control apparatus, the memory include at least two access paths, and described device includes：

In the present embodiment, the products application form of the terminal device includes：Terminal device application when for power consumption with And the sensitivity of performance.

In the present embodiment, the memory access patterns can also include the second balanced mode, and described control unit is described Under second balanced mode, the whole memory space of the memory is divided into by storage address scope corresponding with each access path The second sub- memory space, access request includes the extended address after extension process to target access address, by right The extended address carries out address decoding to determine corresponding access mode；The access mode includes the first access mode and the Two access modes, first access mode are to realize that the noninterlaced of access request is visited in each second sub- memory space Ask, second access mode is to realize that the alternating expression of access request accesses in the 3rd access region, the 3rd access region In access address be by alternating expression access size in units of, by the physical storage address of each second sub- memory space The virtual memory address that alternative mapping forms.

Under second balanced mode, the internal storage access control device of the terminal device can also include：Suitable for Put the register for the size that the alternating expression accesses；Dispensing unit, suitable for for the bus master unit for sending access request Transmission characteristic is different, and the size of corresponding alternating expression access is respectively configured by the register.

Under second balanced mode, the internal storage access control device of the terminal device can also include：Detection is single Member, suitable under second balanced mode, before access request is assigned to corresponding access path, detecting the access path Whether corresponding storage address allows；Interrupt location, suitable for detecting the corresponding storage of access path in the detection unit When location does not allow, interrupt signal notice system is sent.

Under any memory access patterns, the internal storage access control device of the terminal device can also include：Access prison Unit is controlled, suitable for when realizing the noninterlaced access of access request, judging whether unassigned access in the scheduled time The access path of request；Electric unit is saved, suitable for judging to deposit the access path of unassigned access request in the given time When, the access path is entered battery saving mode.

During actual implementation, under high performance mode, low-power consumption mode and the first balanced mode, each memory access patterns are with quiet For the form respective stored of state allocation list in the storage unit, the selecting unit selects corresponding memory access patterns to visiting Ask that request is allocated on each access path to realize by configuring corresponding static allocation list.

The terminal that the specific implementation of the internal storage access control device of the terminal device may be referred to described in the present embodiment is set The implementation of standby memory access control method, details are not described herein again.

It will be understood by those skilled in the art that realize the complete of the internal storage access control device of terminal device in above-described embodiment Portion or part are relevant hardware can be instructed to complete by program, and the program can be stored in computer-readable deposit In storage media, the storage medium can be ROM, RAM, magnetic disc, CD etc..

Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the scope of restriction.

Claims

A kind of 1. memory access control method of terminal device, it is characterised in that the memory includes at least two access paths, The described method includes：

According to the different product application form of the terminal device, select corresponding memory access patterns to access request each It is allocated on access path, the memory access patterns include high performance mode, low-power consumption mode and the first balanced mode；

The high performance mode is suitable for realizing that the alternating expression of access request accesses in the whole memory space of the memory, described During alternating expression accesses, memory is in different blocks, as long as read-write operation will carry out in two blocks, the read-write Operation can be just carried out at the same time；

The low-power consumption mode is suitable for being divided into the whole memory space of the memory and each access by storage address scope The corresponding first sub- memory space of passage, the noninterlaced for realizing access request in each first sub- memory space access, The storage address scope by the corresponding each piece choosing of each access path the size of external physical memory determine；

First balanced mode is suitable for the whole memory space of the memory being divided into the first access region and the second access region Domain, the alternating expression for realizing access request in first access region access, and second access region includes corresponding respectively to The sub- access region of each access path, the noninterlaced for realizing access request in every sub- access region access.
2. the memory access control method of terminal device according to claim 1, it is characterised in that first access region The size of the size that domain and wherein alternating expression access and second access region is determined by system emulation and test.
3. the memory access control method of terminal device according to claim 2, it is characterised in that first access region The size of size and second access region that domain and wherein alternating expression access determines to include by system emulation and test：

Go out the quantity of application high to performance requirement in every application of the terminal device by system emulation and test statistics And respective required storage size, the size of first access region, the whole storage of the memory are determined with this The size that the size in space subtracts first access region is the size of second access region；

Corresponding bus master unit sends visit during high to performance requirement application operation described with test assessment by system emulation Ask the transmission characteristic of request, the size of the alternating expression access is determined with this.
4. the memory access control method of terminal device according to claim 1, it is characterised in that the internal storage access mould Formula further includes the second balanced mode, under second balanced mode, by the storage address scope by the whole of the memory Memory space is divided into the second sub- memory space corresponding with each access path, and access request is included to target access address Extended address after extension process, by determining corresponding access mode to extended address progress address decoding； The access mode includes the first access mode and the second access mode, and first access mode is in each second son Memory space realizes that the noninterlaced of access request accesses, and second access mode is to realize to access in the 3rd access region to ask The alternating expression asked accesses, the access address in the 3rd access region be in units of the size that alternating expression accesses, will be each The virtual memory address that the physical storage address alternative mapping of the second sub- memory space forms.
5. the memory access control method of terminal device according to claim 4, it is characterised in that the extension process bag Include to add the target access address and access selection extension bits, the selection extension bits that access are suitable for identifying the access mode It is first access mode or second access mode.
6. the memory access control method of terminal device according to claim 5, it is characterised in that described to access selection expansion Exhibition position makes an addition to the highest order of the extended address.
7. the memory access control method of terminal device according to claim 4, it is characterised in that further include：

The register for being suitable for configuring the size that the alternating expression accesses is set；

It is different for the transmission characteristic for the bus master unit for sending access request, it is respectively configured accordingly by the register The size that alternating expression accesses.
8. the memory access control method of terminal device according to claim 4, it is characterised in that further include：Described Under second balanced mode, before access request is assigned to corresponding access path, the corresponding storage of the access path is detected Whether location allows, and interrupt signal notice system is sent when not allowing.
9. the memory access control method of the terminal device according to claim 1 or 4, it is characterised in that further include：In reality When the noninterlaced of existing access request accesses, if depositing the access path of unassigned access request in the given time, make this Access path enters battery saving mode.
10. the memory access control method of terminal device according to claim 1, it is characterised in that each internal storage access mould Respective stored is in the terminal device in the form of static allocation list for formula, and the corresponding memory access patterns of selection are to accessing Request is allocated on each access path to be realized by configuring corresponding static allocation list.
11. the memory access control method of the terminal device according to claim 1 or 4, it is characterised in that for each visit Ask passage, the size that alternating expression accesses is all equal.
12. the memory access control method of terminal device according to claim 1, it is characterised in that the terminal device For mobile communication terminal, the mobile communication terminal includes Communication processor and application processor, when the memory access patterns For low-power consumption mode when, the access request that the Communication processor and application processor are sent is allocated in different access respectively Passage, and realize that the noninterlaced of access request accesses.
13. the memory access control method of terminal device according to claim 1, it is characterised in that the terminal device Products application form include：Terminal device is in application for the sensitivity of power consumption and performance.
14. the internal storage access control device of a kind of terminal device, it is characterised in that the memory, which includes at least two and accesses, to be led to Road, described device include：

Selecting unit, suitable for the different product application form according to the terminal device, selects corresponding memory access patterns；

Storage unit, suitable for storing the memory access patterns, the memory access patterns include high performance mode, low-power consumption mould Formula and the first balanced mode；

Control unit, suitable for the selected memory access patterns of the selecting unit to access request on each access path It is allocated；

The high performance mode is suitable for realizing that the alternating expression of access request accesses in the whole memory space of the memory, described During alternating expression accesses, memory is in different blocks, as long as read-write operation will carry out in two blocks, the read-write Operation can be just carried out at the same time；

The low-power consumption mode is suitable for being divided into the whole memory space of the memory and each access by storage address scope The corresponding first sub- memory space of passage, the noninterlaced for realizing access request in each first sub- memory space access, The storage address scope by the corresponding each piece choosing of each access path the size of external physical memory determine；

First balanced mode is suitable for the whole memory space of the memory being divided into the first access region and the second access region Domain, the alternating expression for realizing access request in first access region access, and second access region includes corresponding respectively to The sub- access region of each access path, the noninterlaced for realizing access request in every sub- access region access.
15. the internal storage access control device of terminal device according to claim 14, it is characterised in that the internal storage access Pattern further includes the second balanced mode, and described control unit, will by the storage address scope under second balanced mode The whole memory space of the memory is divided into the second sub- memory space corresponding with each access path, and access request includes To extended address of the target access address after extension process, by determining phase to extended address progress address decoding The access mode answered；The access mode includes the first access mode and the second access mode, first access mode be Each second sub- memory space realizes that the noninterlaced of access request accesses, and second access mode is to be accessed the 3rd Region realizes that the alternating expression of access request accesses, and the access address in the 3rd access region is the size accessed with alternating expression For unit, the virtual memory address that the physical storage address alternative mapping of each second sub- memory space is formed.
16. the internal storage access control device of terminal device according to claim 15, it is characterised in that further include：

Suitable for configuring the register for the size that the alternating expression accesses；

Dispensing unit, it is different suitable for the transmission characteristic for the bus master unit for sending access request, pass through the register The size that corresponding alternating expression accesses is respectively configured.
17. the internal storage access control device of terminal device according to claim 15, it is characterised in that further include：

Detection unit, suitable under second balanced mode, before access request is assigned to corresponding access path, detecting Whether the corresponding storage address of the access path allows；

Interrupt location, suitable for when the detection unit detects that the corresponding storage address of access path does not allow, sending interruption Signal notifies system.
18. the internal storage access control device of the terminal device according to claims 14 or 15, it is characterised in that further include：

Access monitoring unit, suitable for when realizing the noninterlaced access of access request, judging whether in the scheduled time not It is allocated the access path of access request；

Electric unit is saved, suitable for when judging to deposit the access path of unassigned access request in the given time, making the access Passage enters battery saving mode.
19. the internal storage access control device of terminal device according to claim 14, it is characterised in that each internal storage access mould For respective stored in the storage unit, the selecting unit selects corresponding internal storage access mould to formula in the form of static allocation list Formula is allocated access request on each access path and is realized by configuring corresponding static allocation list.
20. the internal storage access control device of terminal device according to claim 14, it is characterised in that the terminal device Products application form include：Terminal device is in application for the sensitivity of power consumption and performance.