CN105426324A

CN105426324A - Memory access control method and apparatus of terminal device

Info

Publication number: CN105426324A
Application number: CN201410235544.6A
Authority: CN
Inventors: 湛振波
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2014-05-29
Filing date: 2014-05-29
Publication date: 2016-03-23
Anticipated expiration: 2034-05-29
Also published as: CN105426324B

Abstract

The present invention provides a memory access control method and apparatus of a terminal device. The memory comprises at least two access channels. The method comprises: selecting a corresponding memory access mode according to different product application states of the terminal device, and allocating access requests to the access channels, wherein the memory access modes include a high performance mode, a low power consumption mode, and a balancing mode. The high performance mode is suitable for implementing interleaved access of the access requests to the entire storage space of the memory; the low power consumption mode is suitable for dividing the entire storage space of the memory into first sub-storage spaces in one-to-one correspondence with the access channels according to a storage address range and implementing non-interleaved access of the access requests to each first sub-storage space; and the balancing mode combines the advantages of both the high performance mode and the low power consumption mode. According to the technical solutions of the present invention, access requirements of various applications of the terminal device for the memory can be met from the aspects of flexibility, performance improvement, and power consumption control.

Description

The memory access control method of terminal device and device

Technical field

The present invention relates to computer realm, particularly a kind of memory access control method of terminal device and device.

Background technology

Along with the application of consumption electronic product is more and more abundanter, the function that chip provides also gets more and more, and also has very high requirement like this for chip performance.Central processing unit (CPU, CentralProcessingUnit) processing speed, the quantity of the bus master unit (Master) of other similar CPU is also had also to get more and more, the requirement of the access that each master sends to bandwidth is also more and more higher, and such internal memory becomes the bottleneck of efficiency gradually.Especially for mobile communication terminal device (such as mobile phone), on the one hand, along with the high speed network formats such as Long Term Evolution (LTE, LongTermEvolution) are released, web database technology is increasing; On the other hand, the reinforcement of multimedia function, as the multimedia of the high definition display resolutions such as 4k2k, HD, more and more higher to the requirement of bandwidth.

As shown in Figure 1, consumer (as bus master unit such as CPU) needs supplier's (internal memory) constantly to provide data to the access efficiency of traditional single channel memory technology.If consumer is too much, will cause the bottleneck that the performance of supplier becomes current, this is urgent problem.For this reason, the runnability adopting binary channels (Dual-channel) memory techniques elevator system entirety can be considered.The access efficiency of dual access memory technology as shown in Figure 2, by providing the Memory Controller Hub of multiple supplier and improvement, making the degree of parallelism transmitted strengthen, the bandwidth of internal memory can be made to be unlikely to very low.A transmission request can interlock supplier's (another internal storage access passage) in supplier's (internal storage access passage) of being assigned to the lower left corner in Fig. 2 or the lower right corner.

Dual access memory technology is a kind of Memory control and administrative skill in fact, and the Memory Controller Hub that it depends on chipset is had an effect, and the bandwidth that two equivalent specifications internal memories can be made to provide in theory doubles.It is applied in server and workstation system the earliest, and afterwards in order to solve the day by day poverty-stricken memory bandwidth bottleneck problem of desktop computer, it had gone to again the foreground of desktop computer mother board technologies.

Nowadays, along with the bottleneck problem of mobile terminal kind equipment for internal memory performance also highlights day by day, dual access memory access control policy is also applied to mobile terminal kind equipment gradually.But, due to conventional dual access memory access control policy for are mostly PC (PC, the equipment such as PersonalComputer), and this kind equipment is do not need to carry out too much paying close attention to for power problems substantially, so the lifting in the just performance generally more paid close attention to, but for the terminal device that some power problemses are comparatively responsive, existing internal storage access control strategy obviously can not be suitable for well; In addition, also there is the comparatively complicated shortcoming of realization in binary channels more of the prior art, multichannel memory access control policy.

Therefore, prior art cannot realize the requirements for access of types of applications for internal memory meeting terminal device in dirigibility, performance boost and power consumption control.

Summary of the invention

The problem to be solved in the present invention is the requirements for access of types of applications for internal memory that prior art cannot realize meeting terminal device in dirigibility, performance boost and power consumption control.

For solving the problem, technical solution of the present invention provides a kind of memory access control method of terminal device, and described internal memory at least comprises two access paths, and described method comprises:

According to the different product application form of described terminal device, select corresponding memory access patterns to distribute on each access path request of access, described memory access patterns comprises high performance mode, low-power consumption mode and the first balanced mode;

Described high performance mode is suitable for the alternating expression access realizing request of access at the whole storage space of described internal memory;

Described low-power consumption mode is suitable for, by memory address scope, the whole storage space of described internal memory is divided into the first sub-storage space corresponding with each access path, realizes the noninterlaced access of request of access at each described first sub-storage space;

Described first balanced mode is suitable for the whole storage space of described internal memory to be divided into the first access region and the second access region, the alternating expression access of request of access is realized in described first access region, described second access region comprises the sub-access region corresponding respectively to each access path, realizes the noninterlaced access of request of access every sub-access region.

Optionally, the size of described first access region and wherein alternating expression access and the size of described second access region are determined by system emulation and test.

Optionally, the size of described first access region and wherein alternating expression access and the size of described second access region are determined to comprise by system emulation and test:

The quantity of application high to performance requirement in every application of described terminal device and storage size required is separately gone out by system emulation and test statistics, determine the size of described first access region with this, the size that the size of the whole storage space of described internal memory deducts described first access region is the size of described second access region;

When being run by application high to performance requirement described in system emulation and testing evaluation, corresponding bus master unit sends the transport property of request of access, determines with this size that described alternating expression is accessed.

Optionally, described memory access patterns also comprises the second balanced mode, under described second balanced mode, by memory address scope, the whole storage space of described internal memory is divided into the second sub-storage space corresponding with each access path, request of access comprises the extended address of target access address after extension process, by carrying out address decoding to described extended address to determine corresponding access mode; Described access mode comprises the first access mode and the second access mode, described first access mode is the noninterlaced access realizing request of access at each described second sub-storage space, described second access mode is the alternating expression access realizing request of access in the 3rd access region, reference address in described 3rd access region is in units of the size of alternating expression access, by the virtual memory address of the physical storage address alternative mapping of the second sub-storage space described in each.

Optionally, described memory address scope by each access path corresponding each choosing the size of external physical memory determine.

Optionally, described extension process comprises adds access selection extension bits to described target access address, and it is described first access mode or described second access mode that described access selects extension bits to be suitable for identifying described access mode.

Optionally, described access selects extension bits to make an addition to the most significant digit of described extended address.

Optionally, the memory access control method of described terminal device also comprises:

The register being suitable for the size configuring the access of described alternating expression is set;

Transport property for the bus master unit sending request of access is different, is configured the size of corresponding alternating expression access by described register respectively.

Optionally, the memory access control method of described terminal device also comprises: under described second balanced mode, before request of access is assigned to corresponding access path, detects memory address corresponding to this access path and whether allow, and send look-at-me notice system when not allowing.

Optionally, the memory access control method of described terminal device also comprises: when the noninterlaced access realizing request of access, if deposit the access path not being assigned with request of access in the given time, then make this access path enter battery saving mode.

Optionally, each memory access patterns is with the form respective stored of static allocation list in described terminal device, and the corresponding memory access patterns of described selection is dispensing by the corresponding static allocation list of configuration to request of access and realizes on each access path.

Optionally, for each access path, the size of alternating expression access is all equal.

Optionally, described terminal device is mobile communication terminal, described mobile communication terminal comprises Communication processor and application processor, when described memory access patterns is low-power consumption mode, the request of access described Communication processor and application processor sent is allocated in different access paths respectively, and realizes the noninterlaced access of request of access.

Optionally, the products application form of described terminal device comprises: terminal device when applying for the sensitivity of power consumption and performance.

For solving the problem, technical solution of the present invention also provides a kind of internal storage access control device of terminal device, and described internal memory at least comprises two access paths, and described device comprises:

Selection unit, is suitable for the different product application form according to described terminal device, selects corresponding memory access patterns;

Storage unit, is suitable for storing described memory access patterns, and described memory access patterns comprises high performance mode, low-power consumption mode and the first balanced mode;

Control module, is suitable for distributing on each access path request of access with the memory access patterns selected by described selection unit;

Compared with prior art, technical scheme of the present invention at least has the following advantages:

By the different product application form according to terminal device, simply, configure corresponding memory access patterns neatly to distribute on each access path request of access, the high performance mode that described memory access patterns can be made to comprise, low-power consumption mode and the first balanced mode, high performance requirements, low-power consumption requirement can be adapted to respectively and take into account the different internal storage access demands of terminal device of high-performance low-power-consumption requirement, thus achieve the requirements for access of types of applications for internal memory meeting terminal device in dirigibility, performance boost and power consumption control.

Further, by providing the second balanced mode in memory access patterns, the internal storage access demand of high-performance and low-power consumption can either be taken into account, the configuration parameter that described first balanced mode needs could determine based on emulation and test each internal storage access region can be overcome again, and but configuration parameter is once be fixed on the shortcoming cannot arbitrarily changed among chip, any bus master unit can not be limited to chip, is optimized according to the effect that actual software regulates.

Under described second balanced mode, by arranging the register being suitable for the size configuring the access of described alternating expression, transport property for the bus master unit sending request of access is different, configure the size of corresponding alternating expression access with described register respectively, thus make each bus master unit can have the size of the peculiar alternating expression access of oneself.

By the internal storage access under address monitoring and protection second balanced mode, thus play the benefit of safety guarantee, debugging optimization.

When the noninterlaced access realizing request of access, by monitoring the access situation of each access path, make the access path not being assigned with request of access in the schedule time enter battery saving mode, thus reach the object of saving power consumption.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of the access efficiency of single channel memory technology;

Fig. 2 is the schematic diagram of the access efficiency of dual access memory technology;

Fig. 3 is the schematic flow sheet of the memory access control method of the terminal device of the embodiment of the present invention;

Fig. 4 is the structural representation of the dual access memory of the embodiment of the present invention;

Fig. 5 is the schematic diagram of the internal storage access configuration of the high performance mode of the embodiment of the present invention;

Fig. 6 is the schematic diagram of the internal storage access configuration of the low-power consumption mode of the embodiment of the present invention;

Fig. 7 is the schematic diagram of the internal storage access configuration of the first balanced mode of the embodiment of the present invention;

Fig. 8 is the schematic diagram of the internal storage access configuration of the second balanced mode of the embodiment of the present invention.

Embodiment

For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.

In order in dirigibility, performance boost and power consumption control meet the requirements for access of types of applications for internal memory of terminal device, the embodiment of the present invention provides a kind of memory access control method of terminal device, described internal memory at least comprises two access paths, by the different product application form according to described terminal device, corresponding memory access patterns is selected to distribute on each access path request of access, described memory access patterns comprises high performance mode, low-power consumption mode and balanced mode, the different access demand of types of applications for internal memory of described terminal device can be adapted to.The method uses foolproof mode to realize multichannel memory access control, promoting the runnability of total system simultaneously, making it possible to flexible configuration, and power consumption also can meet the demand of low-power consumption, be especially applicable to mobile terminal device.

As shown in Figure 3, the memory access control method of terminal device that the embodiment of the present invention provides comprises:

Perform step S1, judge terminal device is as which kind of products application form; In the present embodiment, the products application form of described terminal device comprises: terminal device when applying for the sensitivity of power consumption and performance; Sensitivity for power consumption is higher, then show that terminal device has the requirement of low-power consumption when applying, sensitivity for performance is higher, then show that terminal device has high performance requirement when applying, sensitivity for power consumption and performance is all higher, then show that terminal device has when applying the requirement taking into account high-performance and low-power consumption;

If the products application form of terminal device is high performance requirements, then perform step S21, select high performance mode to distribute on each access path request of access; Described high performance mode is suitable for the alternating expression access realizing request of access at the whole storage space of described internal memory;

If the products application form of terminal device is low-power consumption requirement, then perform step S22, select low-power consumption mode to distribute on each access path request of access; Described low-power consumption mode is suitable for, by memory address scope, the whole storage space of described internal memory is divided into the first sub-storage space corresponding with each access path, realizes the noninterlaced access of request of access at each described first sub-storage space;

If the products application form of terminal device requires to take into account for high-performance and low-power consumption, then perform step S23, select balanced mode to distribute on each access path request of access; In the present embodiment, described balanced mode comprises the first balanced mode, described first balanced mode is suitable for the whole storage space of described internal memory to be divided into the first access region and the second access region, the alternating expression access of request of access is realized in described first access region, described second access region comprises the sub-access region corresponding respectively to each access path, realizes the noninterlaced access of request of access every sub-access region.

In the present embodiment, described terminal device is specially mobile communication terminal device, such as mobile phone, there is the panel computer etc. of communication module, in other embodiments, described terminal device also can be palm PC, car-mounted terminal, desktop computer etc.Described internal memory is with Double Data Rate synchronous DRAM (DDRSDRAM comparatively conventional now, DoubleDateRateSynchronousDynamicRandomAccessMemory), save as example in abbreviation DDR to be described, in other embodiments, described internal memory also can support the storer of binary channels or multichannel memory technology for other.

Below in conjunction with accompanying drawing, above-mentioned memory access patterns is described in detail.

It should be noted that, in the present embodiment to support that the DDR of dual access memory access technique illustrates, but the memory access control method of the terminal device that the embodiment of the present invention provides not only is confined to binary channels, it can be hyperchannel (namely comprising plural internal storage access passage).

The structure of the dual access memory of the embodiment of the present invention as shown in Figure 4, DDR controller A, DDRPHYA and A0, A1 form an internal storage access passage, DDR controller B, DDRPHYB and B0, B1 form another internal storage access passage, distributed come from multiple Master (M0, M1 as shown in Figure 4 by the one deck on DDR controller and interconnect logic layer (interconnectlogic) ... Mn) read-write requests (i.e. described request of access).

Certainly, in the present embodiment, an an internal storage access passage corresponding DDR controller respectively, in other embodiments, DDR controller A and DDR controller B also can develop and merge into a DDR controller, the i.e. all corresponding DDR controller of all internal storage access passages, but the function that this DDR controller provides is the same with the function that all DDR controllers before merging provide.In addition, in other embodiments, the function that interconnect logic layer realizes also can also be incorporated into inside a DDR controller and go.Therefore, the structure that realizes of dual access memory is not limited to the example that the present embodiment provides.

Continue to consult Fig. 4, DDRPHYA and DDRPHYB is that binary channels DDR is necessary, " DDRPHY " is the parts of some sequential aspects of process and frequency aspect, corresponding with DDR controller, how many DDR controllers are generally had just to have how many DDRPHY, due to " DDRPHY " implication and act as conventionally known to one of skill in the art, be not described in detail herein.

In addition, each internal storage access passage usually all has sheet and selects (CS, ChipSelect), and for selecting external DDR physical memory, generally, sheet choosing is exactly the DDR slice, thin piece selecting outside to connect, using the initialization object as future.First CS, A1 that in Fig. 4, A0 represents access path 0 represent second CS of access path 0; First CS, B1 that B0 represents access path 1 represent second CS of access path 1.In the diagram, for different CS, respectively with different filling patterns to show difference, wherein A0 with blank fill represents, A1 with lattice fill represent, B0 shows with positive oblique line ST Stuffing Table, B1 with backslash filling represent.Certainly, when reality is implemented, each access path all can also have more CS.

In the present embodiment, the structure of dual access memory shown in composition graphs 4 is all described by often kind of memory access patterns.

(1) high performance mode

Described high performance mode is applicable to super phone or panel computer etc. to the insensitive terminal device of power consumption, and that is, this kind equipment is comparatively large due to battery capacity, so what generally more pay close attention to is runnability, then seems relatively not too responsive for power consumption.Under described high performance mode, by realizing the alternating expression access of request of access at the whole storage space of described internal memory, thus the concurrent access of each access path can be realized to the full extent, system performance is got a promotion.

It should be noted that, described alternating expression access can be called again interleaving access (interleaving) or interactive visit, is the memory access technology of a kind of parallel work-flow accelerating memory speed.In interlace mode, internal memory is in different blocks, as long as read-write operation will carry out in two blocks, they just can carry out simultaneously.For example, the odd address of memory bank and even address part are separated, when such current byte is refreshed, the access of next byte can not be affected.The implication of accessing due to described alternating expression and effect dawn known to those skilled in the art, be not described in detail herein.

When a request of access comes from interconnection (Interconnect), be distributed to two access paths as shown in Figure 4 by the logic on Interconnect.For convenience of description, outside DDR physical memory of supposing to have only had A0 and B0 to connect in Fig. 4, so just access storage area corresponding to A0 and B0 respectively, by carrying out concurrent access to improve system performance according to the size (interleavedsize) of the alternating expression access of regulation.

As shown in Figure 5, each the adjacent grid in Fig. 5 represents external DDR physical memory continuous print memory address to the internal storage access configuring condition of described high performance mode, and the storage size of each grid is the size of alternating expression access.Corresponding with the filling pattern represented by these two CS of A0 and B0 in Fig. 4, the access for the storage space of blank spacer-frame subrepresentation derives from A0, and the access for the storage space of positive oblique line spacer-frame subrepresentation comes from B0.Fig. 5 is the address space view that software and hardware module can be seen, is transparent concerning software and hardware module, and which access path they also do not know data from.

In the present embodiment, under described high performance mode, the size of alternating expression access is equal, and that is, the area of Fig. 5 empty filling grid equals the area of positive oblique line spacer-frame.

Under described high performance mode, all storage spaces all carry out alternating expression access, are generally the highest with regard to performance, but power consumption is larger, because most access has all been distributed on two access paths, makes two access paths all can not enter battery saving mode, thus consumed too much power consumption.Those skilled in the art know, and described battery saving mode generally can be provided by DDR controller, such as, select to close some clocks and power supply according to DDR controller, to reach the object of saving power consumption.

It should be noted that, Fig. 5 illustrate only A0 and has connect outside DDR physical memory, B0 has connect the situation of outside DDR physical memory, also can the situation of external equivalence and the external DDR physical memory of A0 for A1, and B1 also can the situation of external equivalence and the external DDR physical memory of B0.Certainly, those skilled in the art are it is easily understood that in other embodiments, if each access path comprises more CS, so the situation of the external DDR physical memory of each CS can with reference to the mode provided in the present embodiment.

(2) low-power consumption mode

Described low-power consumption mode is more suitable for those because of limited battery capacity or flying power and requires high and comparatively responsive to power consumption mobile terminal device.Under described low-power consumption mode, the whole storage space of described internal memory is divided into the first sub-storage space corresponding with each access path by memory address scope, realizes the noninterlaced access of request of access at each described first sub-storage space.In the present embodiment, described memory address scope by each access path corresponding each choosing the size of external physical memory determine.

Compared with described high performance mode, the maximum feature of described low-power consumption mode realizes minimum alternating expression access at whole storage space.The internal storage access configuring condition of described low-power consumption mode as shown in Figure 6, still the hypothesis outside DDR physical memory that only had A0 and B0 to connect, so under low-power consumption mode, whole storage space comprises two parts access region, storage space corresponding to the external DDR physical memory of first A0, this is according to the determined described first sub-storage space corresponding with access path 0 of the memory address scope of A0 external DDR physical memory, namely the region represented by grid is filled with blank in Fig. 6, it two is storage spaces corresponding to the external DDR physical memory of B0, this is first sub-storage space according to the memory address scope of B0 external DDR physical memory another corresponding with access path 1 determined, namely the region in Fig. 6 represented by positive oblique line spacer-frame.

As can be seen from Figure 6, for the whole storage space be made up of the summation of A0 and B0 external DDR physical memory, what realize between the first sub-storage space that the first sub-storage space that A0 is corresponding is corresponding with B0 is the access of twin-channel alternating expression, and inner at each self-corresponding first sub-storage space of A0 and B0, then all realize in the mode of noninterlaced access.

Those skilled in the art know, and for the read-write requests of random access internal memory, all can comprise its memory address that will access, for Memory Controller Hub, what memory address is program will access, and this memory address of arriving goes for data to program.

In the present embodiment, the memory address that request of access will be accessed is called target access address.Under described low-power consumption mode, memory address scope due to the corresponding with each access path first sub-storage space is all a sheet of continuous print memory address, according to the target access address that certain request of access comprises, judge that it is in which memory address scope, just can determine that this request of access should access the first sub-storage space corresponding to A0 or the first sub-storage space corresponding to B0.

For example, general CPU access only can send the access of a bit of continuous print memory address, and the memory address scope of the first sub-storage space corresponding to each access path is generally very large, so the little sector address that sends of CPU usually or drop on region corresponding to A0 as shown in Figure 6, drop on the region that B0 is corresponding, suppose to drop on corresponding A0 region, the A0 region that so just only access is corresponding, suppose to drop on region corresponding to B0, the region that so just only access B0 is corresponding.

When reality is implemented, the size supposing the external DDR physical memory of A0 in Fig. 6 is 1G, the size of the external DDR physical memory of B0 is 1G, and the memory address of external DDR physical memory is continuous print between the two, the 0-1G memory address of so any Mater read and write access all will drop on the first sub-storage space corresponding to A0, and the memory address of access 1G-2G all will drop on the first sub-storage space corresponding to B0.So, when carrying out software system design, deviser can will be assigned to the first sub-storage space corresponding to A0 or B0 according to demand to the access arrangement of internal memory.

It should be noted that, in other embodiments, the size of A0 and B0 external DDR physical memory separately also can be unequal, and the memory address of external DDR physical memory between the two also can be discrete, such as: the size of the external DDR physical memory of A0 is 1G, corresponding memory address scope is 0-1G, and the size of the external DDR physical memory of B0 is 2G, and corresponding memory address scope is 2-4G.

In the present embodiment, because described terminal device is mobile communication terminal, and mobile communication terminal now much all can comprise Communication processor and application processor, so when described memory access patterns is low-power consumption mode, the request of access that then described Communication processor and application processor can be sent is allocated in different access paths respectively, and realize the noninterlaced access of request of access, thus reach the object of power consumption control.

For example, suppose the application processor definition region that only access A0 is corresponding of mobile communication terminal (such as mobile phone), and for the Communication processor definition region that only access B0 is corresponding, the size in each self-corresponding region of A0 and B0 can be unequal.In general, region corresponding to A0 is not accessed when application processor is in idle condition (idle) usually, Communication processor in order to and base station synchronization can region corresponding to access B0, interval, region corresponding to most of the time A0 can be made like this to enter battery saving mode, thus reach the object of saving power consumption; And multimedia etc. is needed to the Master of high bandwidth requirements, then can distribute direct memory access (DMA, DirectMemoryAccess) physical memory is on the region that A0 and B0 is corresponding, namely use Fig. 6 empty to fill grid and two regions represented by positive oblique line spacer-frame simultaneously, make like this to meet high bandwidth requirements.

(3) first balanced modes

Although there is respective advantage in high performance mode and low-power consumption mode, but also there is respective deficiency, therefore kind of the pattern of two above can be considered to combine, obtain the mixed mode of high performance mode and low-power consumption mode, or be referred to as balanced mode, the advantage that two kinds of memory access patterns are outstanding can be obtained under this pattern above: performance and power consumption simultaneously.Described first balanced mode can be applicable to the mobile terminal device that those needs take into account performance boost and power consumption control.

First balanced mode is a kind of implementation of described balanced mode, under described first balanced mode, the whole storage space of described internal memory comprises the first access region and the second access region, the alternating expression access of request of access is realized in described first access region, described second access region comprises the sub-access region corresponding respectively to each access path, realizes the noninterlaced access of request of access every sub-access region.

The internal storage access configuring condition of described first balanced mode as shown in Figure 7, for convenience of description, still the hypothesis outside DDR physical memory that only had A0 and B0 to connect, so under the first balanced mode, whole storage space comprises two large divisions's access region, first access region described in the first, namely the access region formed with multiple staggered adjacent blank filling sub-boxes and positive oblique line filling sub-box shown in Fig. 7, the size of this access region represents with " size0 ", it two is described second access region, namely shown in Fig. 7 one blank fills large grid and positive oblique line and fills the access region that large grid forms, this access region comprises the sub-access region that corresponds to access path 0, this sub-access region represents with " An ", the size of this sub-access region represents with " size1 ", this access region also comprises the sub-access region that another corresponds to access path 1, this sub-access region represents with " Bn ", the size of this sub-access region represents with " size2 ".

For described first access region, the access of request of access to internal memory is realized in the mode of alternating expression access, corresponding with the filling pattern represented by these two CS of A0 and B0 in Fig. 7 is, the access of blank being filled to region represented by sub-box derives from A0, such as, a01, a02 in Fig. 7, the access of positive oblique line being filled to region represented by sub-box comes from B0, such as, b01, b02 in Fig. 7.The size in region represented by each sub-box is the size of alternating expression access, also can carry out representing (not shown in Fig. 7) with " entrysize ".The concrete enforcement of accessing described first access region in the mode of alternating expression access can also with reference to the associated description in described high performance mode, both realize alternating expression access in predetermined memory space, what distinguish to some extent is, the former predetermined memory space is whole storage space, and the predetermined memory space of the latter is the part in whole storage space.

For described second access region, the access of request of access to internal memory is realized in the mode of noninterlaced access, corresponding with the filling pattern represented by these two CS of A0 and B0 in Fig. 7 is, the access of the sub-access region An filled represented by large grid for blank derives from A0, and the access of the sub-access region Bn filled represented by large grid for positive oblique line comes from B0.The concrete enforcement of accessing described second access region in the mode of alternating expression access can also with reference to the associated description in described low-power consumption mode, both realize noninterlaced access in predetermined memory space, what distinguish to some extent is, the former predetermined memory space is whole storage space, and the predetermined memory space of the latter is the part in whole storage space.

Under described first balanced mode, determination for the size (such as size1+size2) of the size (such as size0) of the first access region and size (such as entrysize) and described second access region of wherein alternating expression access is very important, because this directly has influence on the desired level of terminal device for performance boost and power consumption control.

In the present embodiment, the size of described first access region and wherein alternating expression access and the size of described second access region are determined by system emulation and test.

In the present embodiment, by system emulation and test, determine size and the size of described second access region of the first access region and wherein alternating expression access, namely determine which region is that bulk is for realizing the region (i.e. size0) of alternating expression access, the size of alternating expression access be how many relatively appropriate (the static configuration size equal to any Master, i.e. entrysize), the region that bulk does not realize alternating expression access is much (or being called the region accessed for realizing noninterlaced, i.e. size1+size2).

During concrete enforcement, described first access region and the wherein size of alternating expression access and the size of described second access region are determined to comprise by system emulation and test:

After system emulation and test, if size0 is determined, size due to the whole storage space of internal memory to select the size of external physical memory according to all and to be easy to obtain, so the size of the whole storage space of internal memory deducts size0 is then size1+size2, how many sizes are respectively as size1 and size2, then the size of external physical memory is selected to determine by the sheet of corresponding access path, if the equal and opposite in direction of the physical memory that the sheet choosing of two access paths is external, then size1 and size2 is also equal, if the size of the physical memory that the sheet choosing of two access paths is external is unequal, so also need to determine according to entrysize, due to entrysize be can by running the high application of performance requirement described in system emulation and testing evaluation time the corresponding bus master unit transport property that sends request of access determine, and the size that the alternating expression in described first access region is accessed is again equal usually, the result obtained after so the size of the physical memory that the sheet choosing of the corresponding access path of size1 is external deducts [(size0) * (1/2)] is size1, in like manner, the result obtained after the size of the external physical memory of sheet choosing of the corresponding access path of size2 deducts [(size0) * (1/2)] is size2.

About the transport property being sent request of access by system emulation and testing evaluation Master, determine the size that described alternating expression is accessed, it is how many for specifically can assessing maximum size that Master sends access, and what frequency was the highest is whom, and whose priority is the highest.Such as image processor is once accessed and is sent 128 byte (Byte, usually represent with " B ") access, but CPU at most once can only access 64 Byte, because image procossing is bad, human eye can observe flicker, the size just selecting 128 Byte to access as alternating expression so general.Which kind of situation actual is best, determines that selection is much by the emulation testing in chip development process.

Present inventor thinks, as long as test fully, or knows application scenarios very much, just can obtain above-mentioned parameter (such as size0, entrysize, size1+size2), thus make performance and power consumption all reach ideal value.Such as, make the application scenarios that performance requirement is high, be positioned over the first access region for realizing alternating expression access as shown in Figure 7, and make the not high application scenarios of performance requirement only access the An in the second access region or access Bn.Access An and access Bn places the application scenarios of not too simultaneously accessing respectively, can make like this when the first access region no access time, only have An access and Bn without any access, then the access path that Bn is corresponding can enter battery saving mode.Otherwise, when the first access region no access time, only have Bn to access and An without any access, then the access path that An is corresponding can enter battery saving mode.

When reality is implemented, above-mentioned high performance mode, low-power consumption mode and the first balanced mode can by the form respective stored of static allocation list in described terminal devices, and the corresponding memory access patterns of described selection is dispensing by the corresponding static allocation list of configuration to request of access and realizes on each access path.

Particularly, describe request of access how to distribute in binary channels or hyperchannel by defining multiple static allocation list, after static allocation list completes configuration, can height optimization time chip generates concrete logic, software merit rating only needs to carry out corresponding configuration according to different products application forms when system starts.

In the present embodiment, so-called " static configuration ", after that is startup started shooting by terminal device, can not change for completed configuration, and the request of access that Master sends can be assigned on corresponding access path according to configuration, and this relation is static.Such as under described low-power consumption mode, for certain address, always access access path corresponding to A0, then access path corresponding to B0 is always accessed for another address.For another example under described first balanced mode, there is the region of most to be total access passage, have most to be short grained division, the access path that some address access A0 are corresponding, the access path that some address access B0 are corresponding.

Static allocation list is that requirement chip realizes one section of configuration register, and then software merit rating is good.Table 1 is a kind of example of static allocation list:

Table 1

(4) second balanced modes

Because described first balanced mode needs the size based on the basis emulated and test obtaining alternating expression access, also have which region to need to carry out alternating expression access, which region does not need to carry out alternating expression access, needs respectively to specify the size of fixing.Once after chip production, after this memory access patterns selected by software, the concrete configuration parameter (such as size0, entrysize, size1 and size2) under this pattern cannot be changed.

For solving the problem, in the present embodiment, described balanced mode can also comprise the second balanced mode.Described second balanced mode is the another kind of implementation of described balanced mode, under described second balanced mode, by memory address scope, the whole storage space of described internal memory is divided into the second sub-storage space corresponding with each access path, request of access comprises the extended address of target access address after extension process, by carrying out address decoding to described extended address to determine corresponding access mode; Described access mode comprises the first access mode and the second access mode, described first access mode is the noninterlaced access realizing request of access at each described second sub-storage space, described second access mode is the alternating expression access realizing request of access in the 3rd access region, reference address in described 3rd access region is in units of the size of alternating expression access, by the virtual memory address of the physical storage address alternative mapping of the second sub-storage space described in each.

Fig. 8 shows the internal storage access configuring condition of described second balanced mode, outside DDR physical memory of supposing still only had A0 and B0 to connect, so under the second balanced mode, whole storage space comprises two parts access region, storage space corresponding to the external DDR physical memory of first A0, this is according to the determined described second sub-storage space corresponding with access path 0 of the memory address scope of A0 external DDR physical memory, namely the region represented by thick sash is filled with blank in Fig. 8, it two is storage spaces corresponding to the external DDR physical memory of B0, this is second sub-storage space according to the memory address scope of B0 external DDR physical memory another corresponding with access path 1 determined, namely in Fig. 8, positive oblique line fills the region represented by thick sash.

Although, if the division of the whole storage space that single just external DDR physical memory is formed, described second balanced mode and described low-power consumption mode comparatively similar, but, but not identical for the access mode of two the first sub-storage spaces with under described low-power consumption mode for the access mode of two the second sub-storage spaces in the present embodiment, the access mode of the latter is well-determined, and the former access mode is then not unique.In the present embodiment, in the form of the memory address that will access that the request of access that Master sends comprises and prior art, common target access address is different, under the second balanced mode, what request of access comprised is to the extended address of target access address after extension process, by carrying out address decoding to described extended address to determine corresponding access mode, described access mode comprises two kinds, a kind of noninterlaced that can realize realizing at each described second sub-storage space request of access accesses (i.e. described first access mode), another kind of then the alternating expression that can realize in whole storage space accesses (i.e. described second access mode).

For described first access mode, access control scheme under itself and described low-power consumption mode is similar, can by the mode of address decoding, identify the address portion being suitable for carrying out addressing in the extended address that certain request of access comprises, judge that it is in which memory address scope, just can determine that this request of access should access the second sub-storage space corresponding to A0 or the second sub-storage space corresponding to B0.The specific implementation of described first access mode with reference to the associated description of internal storage access control under described low-power consumption mode, can be not described in detail herein.

For described second access mode, in order to the alternating expression access in whole storage space can be realized, therefore an independently virtual memory space is defined in the present embodiment, i.e. described 3rd access region, " virtual access region " as shown in Figure 8, its not actual amount of physical memory, and be a kind of virtual controlling, reference address in this virtual access region is in units of the size of alternating expression access, by the mode of address maps, by the virtual memory address of the physical storage address alternative mapping of each the second sub-storage space, therefore the reference address in this virtual access region is the determined virtual memory address of physical storage address based on the second sub-storage space, and the size in this virtual access region is the size of whole storage space.Such as, suppose that the size of the second sub-storage space that A0 is corresponding be the size of the second sub-storage space that 1G, B0 are corresponding is 1G, so the size in virtual access region is 1G+1G=2GB, is described in the present embodiment as example.

Fig. 8 can be consulted, in " the virtual access region " that illustrate on the left of Fig. 8, each sub-box is a virtual memory address, its size is the size of alternating expression access, lowermost sub-box is the start address in virtual memory address, i.e. " 0 address ", mapping relations between virtual memory address in the physical storage address of each the second sub-storage space and virtual access region are as shown in the four-headed arrow in Fig. 8, address k0 in the second sub-storage space that A0 is corresponding is mapped as 0 address in virtual memory address, address k2 in the second sub-storage space that B0 is corresponding is then mapped as the successor virtual memory address adjacent with " 0 address " and (supposes to be called " 1 address ", Fig. 8 is not shown), address k1 in the second sub-storage space that A0 is corresponding is mapped as the successor virtual memory address adjacent with " 1 address " and (supposes to be called " 2 address ", Fig. 8 is not shown), address k3 in the second sub-storage space that B0 is corresponding is mapped as the successor virtual memory address adjacent with " 2 address ", by that analogy, thus realize the physical storage address alternative mapping of each the second sub-storage space being each virtual memory address in virtual access region.

When reality is implemented, DDR controller is by the mode of address decoding, after determining corresponding access mode, according to the mapping relations between the virtual memory address in the physical storage address of each the second sub-storage space and virtual access region, just the memory address of the external DDR physical memory of final access can be determined, therefore, realizing the alternating expression access of request of access in described virtual access region, is the equal of the alternating expression access achieved in whole amount of physical memory.

By known to introducing of above-mentioned two kinds of access modes, although the address that two kinds of access modes are finally accessed is all the memory address of external DDR physical memory, but understand more intuitively to have these two kinds of access modes, in the present embodiment can by under described first access mode directly access as shown on the right side of Fig. 8 by two thick sash the region that forms be called normal areas, and this virtual controlling as virtual access region shown on the left of Fig. 8 of accessing under described second access mode is called staggered access region at a high speed.

In the present embodiment, described extension process specifically comprises adds access selection extension bits to described target access address, and it is described first access mode or described second access mode that described access selects extension bits to be suitable for identifying described access mode.Such as, if access selects extension bits to be 0, then represent that access mode is the first access mode, if access selects extension bits to be 1, then represent that access mode is the second access mode.

In the present embodiment, for the ease of identifying, described access selects extension bits to make an addition to the most significant digit of described extended address.In other embodiments, also a time high position for described extended address can be selected extension bits as described access, and the most significant digit of described extended address be reserved, for other purposes.It should be noted that, because the low level in certain reference address is used for addressing by those skilled in the art's custom, therefore described extended address can be made to have more versatility the high position that the access additionally increased selects extension bits to be set in extended address.

In addition, the transport property sent due to each Master is different, in order to the size making each Master can have the peculiar alternating expression access of oneself, therefore, the memory access control method of described terminal device also comprises: arrange the register being suitable for the size configuring the access of described alternating expression; Transport property for the bus master unit sending request of access is different, is configured the size of corresponding alternating expression access by described register respectively.

When reality is implemented, can define the table of the size extension bits of an extended address most significant digit and alternating expression access in interconnect logic, example is as table 2:

Table 2

Illustrate the memory access process under described second balanced mode below:

As table 2, extended address most significant digit represents whether access staggered access region at a high speed, and such as this position is that " 1 " then represents access staggered access region at a high speed, and this position is that " 0 " then represents access normal areas.The size extension bits of alternating expression access represents the size that all kinds of Master adopts the alternating expression of which kind of size and access, and such as definition 256B is 1,512B is 2.

Suppose to send access as certain MasterA, the size configure that the alternating expression due to its correspondence is accessed is 1, if so drop on staggered access region at a high speed, then the size of alternating expression access can be that interval conducts interviews with 256B.Suppose the access that have issued 0 address, blank start address (normal areas) k0 filling region represented by thick sash shown in so directly having access on the right side of Fig. 8.Suppose the access that have issued 0+256B, because extended address most significant digit is 0, so still drop on the local k1 of the 256B skew of normal areas, in like manner, the access sending 0-2GB all can drop on normal areas shown on the right side of Fig. 8.Being 1 when MasterA sends most significant digit (can drop on staggered access region at a high speed, space subsequently possesses staggered access function), be the access of 0 for low 32 in extended address, the high speed that so can drop on virtual memory address is interlocked access region, finally has access to physical storage address k0.Being 1 when MasterA sends most significant digit, is the access of 256B for low 32 in extended address, and the high speed that so can drop on virtual memory address is interlocked access region, finally has access to physical storage address k2.

To sum up, at least there is following characteristics in described second balanced mode:

1) any Master can not be limited to chip, is optimized according to the effect that actual software regulates, and namely can decide access staggered access region or normal areas at a high speed by the selection of address.Under this internal storage access mode, the size of the external DDR that a minimum access path is corresponding under the region for realizing alternating expression access is equivalent to many access paths, very flexibly.

2) transport property sent due to each Master is different, the major part access that such as CPU sends is the size of cache lines (Cacheline), as 64B, and other Master send the size of 128B, so the size of the peculiar alternating expression access of oneself can be had for each Master.

Therefore, by providing the second balanced mode in memory access patterns, the internal storage access demand of high-performance and low-power consumption can either be taken into account, the configuration parameter that described first balanced mode needs could determine based on emulation and test each internal storage access region can be overcome again, and but configuration parameter is once be fixed on the shortcoming cannot arbitrarily changed among chip, any bus master unit can not be limited to chip, is optimized according to the effect that actual software regulates.

In addition, under described second balanced mode, owing to can be visited the DDR address of physics by 2 different addresses, that is, there is the physical address that 2 addresses correspondences one are real, all can remove the physical address having access to this necessary being according to virtual address, once software has a lot of problem, just debugging can be caused more difficult, therefore there is certain security risk.For solving this problem, the memory access control method of the described terminal device that the present embodiment provides also comprises: under described second balanced mode, before request of access is assigned to corresponding access path, detect memory address corresponding to this access path whether to allow, and send look-at-me notice system when not allowing.In the specific implementation, whether the memory address that this access path of described detection is corresponding allows is judged by the scope of address, the selection of read and write operation.

Those skilled in the art can understand, and when reality is implemented, by increasing bus address monitoring module (busmonitor) in DDR controller, can carry out security monitoring, thus reduce above-mentioned security risk to the address of access.The function of this module is very simple, by before request of access being distributed to certain access path concrete, detecting its address and whether allow, if do not allow just to send interrupt notification system, can distinguish like this is that the high speed controlled by accesses virtual is interlocked access region, still goes to access normal areas.Roughly being embodied as of the detection whether address is allowed to: be provided with the scope of address, the selection of read and write, when chip find that there is read or write operation time, can triggered interrupts tell programmer, perhaps there is unauthorized access here.This mode can play safety guarantee, the benefit that debugging is optimized.

It should be noted that, in the present embodiment, for each access path, the size of alternating expression access is all equal, and the overall utilization rate of the external DDR physical memory that each access path so can be made corresponding is higher.Those skilled in the art it is understood that, in other embodiments, for any two access paths, the size of alternating expression access also can be unequal, namely in above-mentioned several memory access patterns, all can be applicable to asymmetric DDR, specific address distributes the actual size depending on external DDR physical memory.The maximum region of interactive visit is the DDR size under being equivalent to hyperchannel under a minimum access path.

In addition, in the present embodiment, the memory access control method of described terminal device also comprises: when the noninterlaced access realizing request of access, if deposit the access path not being assigned with request of access in the given time, then make this access path enter battery saving mode.

When reality is implemented, can interpolation chip mechanism be passed through, provide a register to configure to software.Such as provide one for recording the free time register of (idle) time, software merit rating is 200 milliseconds (ms), and when 200ms does not have Master to visit certain access path, so this access path will enter battery saving mode.

Corresponding to the memory access control method of above-mentioned terminal device, the present embodiment also provides a kind of internal storage access control device of terminal device, and described internal memory at least comprises two access paths, and described device comprises:

In the present embodiment, the products application form of described terminal device comprises: terminal device when applying for the sensitivity of power consumption and performance.

In the present embodiment, described memory access patterns can also comprise the second balanced mode, described control module is under described second balanced mode, by memory address scope, the whole storage space of described internal memory is divided into the second sub-storage space corresponding with each access path, request of access comprises the extended address of target access address after extension process, by carrying out address decoding to described extended address to determine corresponding access mode; Described access mode comprises the first access mode and the second access mode, described first access mode is the noninterlaced access realizing request of access at each described second sub-storage space, described second access mode is the alternating expression access realizing request of access in the 3rd access region, reference address in described 3rd access region is in units of the size of alternating expression access, by the virtual memory address of the physical storage address alternative mapping of the second sub-storage space described in each.

Under described second balanced mode, the internal storage access control device of described terminal device can also comprise: the register being suitable for the size configuring the access of described alternating expression; Dispensing unit, the transport property be suitable for for the bus master unit sending request of access is different, is configured the size of corresponding alternating expression access by described register respectively.

Under described second balanced mode, the internal storage access control device of described terminal device can also comprise: detecting unit, be suitable under described second balanced mode, before request of access is assigned to corresponding access path, detects memory address corresponding to this access path and whether allow; Interrupt location, is suitable for when described detecting unit detects that the memory address that access path is corresponding does not allow, and sends look-at-me notice system.

Under any memory access patterns, the internal storage access control device of described terminal device can also comprise: access monitoring unit, be suitable for, when the noninterlaced access realizing request of access, judging whether to deposit the access path not being assigned with request of access in the given time; Economize electric unit, being suitable for when judging to deposit the access path not being assigned with request of access in the given time, making this access path enter battery saving mode.

During actual enforcement, under high performance mode, low-power consumption mode and the first balanced mode, each memory access patterns is with the form respective stored of static allocation list in described storage unit, and described selection unit selects corresponding memory access patterns on each access path, to be dispensing by the corresponding static allocation list realization of configuration to request of access.

The concrete enforcement of the internal storage access control device of described terminal device with reference to the enforcement of the memory access control method of the terminal device described in the present embodiment, can repeat no more herein.

It will be appreciated by those skilled in the art that, realizing all or part of of the internal storage access control device of terminal device in above-described embodiment is that the hardware that can carry out instruction relevant by program has come, described program can be stored in computer-readable recording medium, and described storage medium can be ROM, RAM, magnetic disc, CD etc.

Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims

1. a memory access control method for terminal device, is characterized in that, described internal memory at least comprises two access paths, and described method comprises:

2. the memory access control method of terminal device according to claim 1, is characterized in that, described first access region and the wherein size of alternating expression access and the size of described second access region are determined by system emulation and test.

3. the memory access control method of terminal device according to claim 2, is characterized in that, described first access region and the wherein size of alternating expression access and the size of described second access region are determined to comprise by system emulation and test:

4. the memory access control method of terminal device according to claim 1, it is characterized in that, described memory access patterns also comprises the second balanced mode, under described second balanced mode, by memory address scope, the whole storage space of described internal memory is divided into the second sub-storage space corresponding with each access path, request of access comprises the extended address of target access address after extension process, by carrying out address decoding to described extended address to determine corresponding access mode; Described access mode comprises the first access mode and the second access mode, described first access mode is the noninterlaced access realizing request of access at each described second sub-storage space, described second access mode is the alternating expression access realizing request of access in the 3rd access region, reference address in described 3rd access region is in units of the size of alternating expression access, by the virtual memory address of the physical storage address alternative mapping of the second sub-storage space described in each.

5. the memory access control method of the terminal device according to claim 1 or 4, is characterized in that, described memory address scope by each access path corresponding each choosing the size of external physical memory determine.

6. the memory access control method of terminal device according to claim 4, it is characterized in that, described extension process comprises adds access selection extension bits to described target access address, and it is described first access mode or described second access mode that described access selects extension bits to be suitable for identifying described access mode.

7. the memory access control method of terminal device according to claim 6, is characterized in that, described access selects extension bits to make an addition to the most significant digit of described extended address.

8. the memory access control method of terminal device according to claim 4, is characterized in that, also comprises:

9. the memory access control method of terminal device according to claim 4, it is characterized in that, also comprise: under described second balanced mode, before request of access is assigned to corresponding access path, detect memory address corresponding to this access path whether to allow, and send look-at-me notice system when not allowing.

10. the memory access control method of the terminal device according to claim 1 or 4, it is characterized in that, also comprise: when the noninterlaced access realizing request of access, if deposit the access path not being assigned with request of access in the given time, then make this access path enter battery saving mode.

The memory access control method of 11. terminal devices according to claim 1, it is characterized in that, each memory access patterns is with the form respective stored of static allocation list in described terminal device, and the corresponding memory access patterns of described selection is dispensing by the corresponding static allocation list of configuration to request of access and realizes on each access path.

The memory access control method of 12. terminal devices according to claim 1 or 4, is characterized in that, for each access path, the size of alternating expression access is all equal.

The memory access control method of 13. terminal devices according to claim 1, it is characterized in that, described terminal device is mobile communication terminal, described mobile communication terminal comprises Communication processor and application processor, when described memory access patterns is low-power consumption mode, the request of access described Communication processor and application processor sent is allocated in different access paths respectively, and realizes the noninterlaced access of request of access.

The memory access control method of 14. terminal devices according to claim 1, is characterized in that, the products application form of described terminal device comprises: terminal device when applying for the sensitivity of power consumption and performance.

The internal storage access control device of 15. 1 kinds of terminal devices, is characterized in that, described internal memory at least comprises two access paths, and described device comprises:

The internal storage access control device of 16. terminal devices according to claim 15, it is characterized in that, described memory access patterns also comprises the second balanced mode, described control module is under described second balanced mode, by memory address scope, the whole storage space of described internal memory is divided into the second sub-storage space corresponding with each access path, request of access comprises the extended address of target access address after extension process, by carrying out address decoding to described extended address to determine corresponding access mode; Described access mode comprises the first access mode and the second access mode, described first access mode is the noninterlaced access realizing request of access at each described second sub-storage space, described second access mode is the alternating expression access realizing request of access in the 3rd access region, reference address in described 3rd access region is in units of the size of alternating expression access, by the virtual memory address of the physical storage address alternative mapping of the second sub-storage space described in each.

The internal storage access control device of 17. terminal devices according to claim 16, is characterized in that, also comprise:

Be suitable for the register of the size configuring the access of described alternating expression;

Dispensing unit, the transport property be suitable for for the bus master unit sending request of access is different, is configured the size of corresponding alternating expression access by described register respectively.

The internal storage access control device of 18. terminal devices according to claim 16, is characterized in that, also comprise:

Whether detecting unit, is suitable under described second balanced mode, before request of access is assigned to corresponding access path, detects memory address corresponding to this access path and allow;

Interrupt location, is suitable for when described detecting unit detects that the memory address that access path is corresponding does not allow, and sends look-at-me notice system.

The internal storage access control device of 19. terminal devices according to claim 15 or 16, is characterized in that, also comprise:

Access monitoring unit, is suitable for, when the noninterlaced access realizing request of access, judging whether to deposit the access path not being assigned with request of access in the given time;

Economize electric unit, being suitable for when judging to deposit the access path not being assigned with request of access in the given time, making this access path enter battery saving mode.

The internal storage access control device of 20. terminal devices according to claim 15, it is characterized in that, each memory access patterns is with the form respective stored of static allocation list in described storage unit, and described selection unit selects corresponding memory access patterns on each access path, to be dispensing by the corresponding static allocation list realization of configuration to request of access.

The internal storage access control device of 21. terminal devices according to claim 15, is characterized in that, the products application form of described terminal device comprises: terminal device when applying for the sensitivity of power consumption and performance.