CN105405875A - 一种低关态电流隧穿场效应晶体管 - Google Patents

一种低关态电流隧穿场效应晶体管 Download PDF

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CN105405875A
CN105405875A CN201510792258.4A CN201510792258A CN105405875A CN 105405875 A CN105405875 A CN 105405875A CN 201510792258 A CN201510792258 A CN 201510792258A CN 105405875 A CN105405875 A CN 105405875A
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grid
effect transistor
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唐明华
钟兴宏
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Xiangtan University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391Gated diode structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0895Tunnel injectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种低关态电流隧穿场效应晶体管,包括源区、沟道区、漏区、第一栅介质层,沟道区上设有第一栅介质层,第一栅介质层上设有第一栅极,源区位于沟道区下方且紧靠沟道区下部,源区上设有源极,沟道区一侧设有漏区,漏区右端设有漏极,沟道区与漏区之间设有调节区,沟道区与调节区之间设有过渡区,调节区上设有第二栅介质层,第二栅介质层上设有第二栅极,第一栅极和第二栅极通过导线连接在一起作为整个场效应晶体管的栅极,过渡区上设有隔离区。本发明在沟道区与漏区之间引入调节区,调节区的等效电阻作用使得低关态电流隧穿场效应晶体管获得了更低的亚阈值摆幅和静态功耗,从而提升了低关态电流隧穿场效应晶体管的性能。

Description

一种低关态电流隧穿场效应晶体管
技术领域
本发明涉及一种场效应晶体管,特别涉及一种低关态电流隧穿场效应晶体管。
背景技术
随着集成电路技术的不断向前发展,器件特征尺寸不断缩小,传统金属-氧化物-半导体场效应晶体管(MOSFET,Metal-oxide-semiconductorFieldEffectTransistor)由于受到热电子注入的限制,使得亚阈值摆幅SS(SubthresholdSwing)不得低于极限值60mV/decade,阻碍了器件的进一步缩小,并且在该过程中,功耗也逐渐成为首要考虑的一个重要因素。而隧道场效应晶体管(TFET,TunnelingFieldEffectTransistor)由于利用带间隧穿(BTBT,Band-to-bandTunneling)机制,亚阈值摆幅能够低于60mV/decade,在集成度要求更高的电路系统中,有望替代传统的MOSFET。
通过设计更有效的横向隧穿或纵向隧穿或两者皆有来提升TFET的亚阈值性能,亦可通过采用窄禁带的半导体材料(如III-V族的InAs,或者二维材料石墨烯等)或介电常数较高的栅介质等材料来获得更高性能的TFET,但是通过这些途径获得的TFET的性能的提升总是有限的。
发明内容
为了解决上述技术问题,本发明提供一种结构简单、能够降低亚阈值摆幅和静态功耗的低关态电流隧穿场效应晶体管。
本发明解决上述问题的技术方案是:一种低关态电流隧穿场效应晶体管,包括源区、沟道区、漏区、第一栅介质层,所述沟道区上设有第一栅介质层,第一栅介质层上设有第一栅极,所述源区位于沟道区下方且紧靠沟道区下部,源区上设有源极,沟道区一侧设有漏区,漏区右端设有漏极,所述沟道区与漏区之间设有调节区,沟道区与调节区之间设有过渡区,所述调节区上设有第二栅介质层,第二栅介质层上设有第二栅极,所述第一栅极和第二栅极通过导线连接在一起作为整个场效应晶体管的栅极,所述过渡区上设有用于隔离第一栅极和第二栅极的隔离区。
上述低关态电流隧穿场效应晶体管中,所述沟道区与源区之间设有重掺杂源区。
上述低关态电流隧穿场效应晶体管中,所述过渡区与沟道区的掺杂类型相同,且掺杂浓度相同。
上述低关态电流隧穿场效应晶体管中,所述调节区与过渡区的掺杂类型不同。
上述低关态电流隧穿场效应晶体管中,所述调节区与过渡区的掺杂类型相同且调节区的掺杂浓度小于过渡区的掺杂浓度。
本发明的有益效果在于:本发明在原有低关态电流隧穿场效应晶体管的基础上,在沟道区与漏区之间引入调节区,为了更好提升调节区的调节能力,在沟道区与调节区之间设过渡区,在能带上起到缓冲作用,降低了调节区对隧穿发生区能带的影响,这样调节区可以在器件关闭状态时能带上弯,类似于场效应晶体管关闭时沟道的能带上弯,可以有效降低漏极电流,使得关态电流受到抑制;而在器件导通状态时能带下弯,类似于场效应晶体管导通时沟道的能带下沉,对漏极电流影响可忽略,使得开态电流基本不变或甚至可达到增加开态电流的目的。调节区的等效电阻作用使得低关态电流隧穿场效应晶体管在原有的基础上,获得了更低的亚阈值摆幅和静态功耗,从而达到提升低关态电流隧穿场效应晶体管性能的目的。
附图说明
图1为现有低关态电流隧穿场效应晶体管的结构示意图。
图2为本发明的结构示意图。
图3是本发明应用前后的低关态电流隧穿场效应晶体管在关闭状态时,沿着剖线(图2中的点画线)的导带和价带的能带分布对比图。
图4是本发明应用前后的低关态电流隧穿场效应晶体管在导通状态时,沿着剖线(图2中的点画线)的导带和价带的能带分布对比图。
图5是本发明应用前后的低关态电流隧穿场效应晶体管的传输特性曲线对比图。
具体实施方式
下面结合附图和实施例对本发明作进一步的说明。
如图2所示,本发明包括沟道区101、漏区102、源区103、第一栅介质层104、隔离区105、重掺杂源区106、调节区107、过渡区109,沟道区101采用n型砷化铟(InAs),浓度为5E17cm-3,所述沟道区101上设有第一栅介质层104,第一栅介质层104采用二氧化硅(SiO2),第一栅介质层104上设有第一栅极111,所述源区103位于沟道区101下方且紧靠沟道区101下部,所述源区103采用p型锑化镓(GaSb),浓度为4E18cm-3,源区103上设有源极113,沟道区101与源区103之间设有重掺杂源区106,重掺杂源区106采用p型锑化镓(GaSb),浓度为4E19cm-3,沟道区101一侧设有漏区102,漏区102采用n型砷化铟(InAs),浓度为5E17cm-3,漏区102右端设有漏极112,所述沟道区101与漏区102之间设有调节区107,调节区107的掺杂类型采用n型砷化铟(InAs),浓度为5E15cm-3,沟道区101与调节区107之间设有过渡区109,过渡区109与沟道区101的掺杂类型相同,掺杂采用n型砷化铟(InAs),浓度为5E17cm-3;所述调节区107上设有第二栅介质层108,第二栅介质层108采用二氧化硅(SiO2)作为介电材料,第二栅介质层108上设有第二栅极110,所述第一栅极111和第二栅极110通过金属或多晶硅等导线连接在一起作为整个场效应晶体管的栅极,所述过渡区109上设有用于隔离第一栅极111和第二栅极110的隔离区105,隔离区105采用二氧化硅(SiO2)。
图3是本发明应用前后的低关态电流隧穿场效应晶体管(TFET)在关闭状态时,沿着剖线(图2中的点画线)的导带和价带的能带分布对比图。本发明应用后的导带和价带(图中实线)均比本发明应用前的导带和价带(图中虚线)要高,且在BC段(调节区107)尤其明显。参考本发明应用前后的TFET传输特性曲线对比图(图5)中的栅电压较低(V g=-1.4V)处,发现漏极112电流下降了4个数量级,可知,调节区107在此时起到了一个很大的阻抗作用,极大地降低了漏极112电流。
图4是本发明应用前后的低关态电流隧穿场效应晶体管(TFET)在导通状态时,沿着剖线(图2中的点画线)的导带和价带的能带分布对比图。本发明应用后的导带和价带(图中实线)均比本发明应用前的导带和价带(图中虚线)要低,且在BC段(调节区107)尤其明显。参考本发明应用前后的TFET传输特性曲线对比图(图5)中的栅电压较高(V g=-0.1V)处,发现漏极112电流基本不变,可知,调节区107在此时起到的作用很小,基本保持了原有TFET导通电流的特性。
以上实施例中的调节区107可采用与过渡区109不同的掺杂类型,如p型掺杂,掺杂杂质亦可为其它,如锑化铟(InSb)、锑化镓(GaSb)等。调节区107上的栅介质层亦可采用其它,如氧化铝(Al2O3)、氧化铪(HfO2)等。
以上所述具体实施例,旨在进一步详细说明本发明的使用,帮助进一步理解本发明,而不是为了限制本发明的范围。本领域的技术人员应该理解,在不脱离本发明的精神和原则的情况下,各种修改和替换均应包含在本发明的保护范围之内。

Claims (5)

1.一种低关态电流隧穿场效应晶体管,包括源区、沟道区、漏区、第一栅介质层,所述沟道区上设有第一栅介质层,第一栅介质层上设有第一栅极,所述源区位于沟道区下方且紧靠沟道区下部,源区上设有源极,沟道区一侧设有漏区,漏区右端设有漏极,其特征在于:所述沟道区与漏区之间设有调节区,沟道区与调节区之间设有过渡区,所述调节区上设有第二栅介质层,第二栅介质层上设有第二栅极,所述第一栅极和第二栅极通过导线连接在一起作为整个场效应晶体管的栅极,所述过渡区上设有用于隔离第一栅极和第二栅极的隔离区。
2.根据权利要求1所述的低关态电流隧穿场效应晶体管,其特征在于:所述沟道区与源区之间设有重掺杂源区。
3.根据权利要求1或2所述的低关态电流隧穿场效应晶体管,其特征在于:所述过渡区与沟道区的掺杂类型相同,且掺杂浓度相同。
4.根据权利要求1或2所述的低关态电流隧穿场效应晶体管,其特征在于:所述调节区与过渡区的掺杂类型不同。
5.根据权利要求1或2所述的低关态电流隧穿场效应晶体管,其特征在于:所述调节区与过渡区的掺杂类型相同且调节区的掺杂浓度小于过渡区的掺杂浓度。
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Cited By (5)

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CN106206703A (zh) * 2016-07-26 2016-12-07 电子科技大学 一种增加开态电流的隧穿场效应晶体管
CN107342320A (zh) * 2017-07-18 2017-11-10 清华大学 无结型隧穿场效应晶体管及制备方法
CN107731684A (zh) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN108389896A (zh) * 2018-01-22 2018-08-10 电子科技大学 一种有效抑制双极性电流的双栅隧穿场效应晶体管
WO2018214170A1 (zh) * 2017-05-26 2018-11-29 华为技术有限公司 隧穿场效应晶体管及其制备方法

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206703A (zh) * 2016-07-26 2016-12-07 电子科技大学 一种增加开态电流的隧穿场效应晶体管
CN107731684A (zh) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
WO2018214170A1 (zh) * 2017-05-26 2018-11-29 华为技术有限公司 隧穿场效应晶体管及其制备方法
CN107342320A (zh) * 2017-07-18 2017-11-10 清华大学 无结型隧穿场效应晶体管及制备方法
CN107342320B (zh) * 2017-07-18 2021-02-02 清华大学 无结型隧穿场效应晶体管及制备方法
CN108389896A (zh) * 2018-01-22 2018-08-10 电子科技大学 一种有效抑制双极性电流的双栅隧穿场效应晶体管
CN108389896B (zh) * 2018-01-22 2020-12-29 电子科技大学 一种有效抑制双极性电流的双栅隧穿场效应晶体管

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Application publication date: 20160316