CN105405388B - Pixel-driving circuit, display base plate and display device - Google Patents
Pixel-driving circuit, display base plate and display device Download PDFInfo
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- CN105405388B CN105405388B CN201610006936.4A CN201610006936A CN105405388B CN 105405388 B CN105405388 B CN 105405388B CN 201610006936 A CN201610006936 A CN 201610006936A CN 105405388 B CN105405388 B CN 105405388B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention relates to a kind of pixel-driving circuit, including：Signal output transistor and other transistors, the width of the signal output transistor source are less than the width of other transistor sources, and the width of the signal output transistor drain is more than the width of other transistor drains.Technique according to the invention scheme can reduce the facing area of source electrode and grid, so as to reduce the gate-source capacitance of signal output transistor by reducing the source width of signal output transistor.On the other hand by increasing the drain width of signal output transistor, so as to improve the gate leakage capacitance of signal output transistor, and then coupled voltages are reduced.The grid avoided in signal output transistor produces larger coupled voltages, improves the high temperature AD problems of signal output transistor.
Description
Technical field
The present invention relates to display technology field, in particular to a kind of pixel-driving circuit, a kind of display base plate and one
Kind display device.
Background technology
GOA (Gate on Array) technology can effectively improve the integrated level of pixel-driving circuit, and one of which pixel is driven
Dynamic circuit exports clock signal by signal output transistor, and the source electrode of the signal output transistor connects clock signal terminal, when
During grid input high level, clock signal can be exported by draining.Namely in normal operation, when signal output is brilliant
During the grid input high level of body pipe, signal output transistor can be opened, so as to which clock signal be exported by drain electrode.
But in the grid input low level of signal output transistor, because coupled capacitor is deposited in pixel-driving circuit
The high level signal of clock signal terminal can impact to the grid of signal output transistor, in signal output transistor
Grid forms coupled voltages.Particularly under high temperature operating conditions, the Vth (threshold voltage) of signal output transistor can float
Move so that signal output transistor can be opened when grid voltage is smaller, cause the grid of signal output transistor by then
The influence of clock signal high level is more serious, so that in the grid defeated such as low level stage of signal output transistor, high temperature occurs
AD (Abnormal Display, display are bad).
The content of the invention
The technical problems to be solved by the invention are that it is defeated to signal to reduce coupled voltages caused by clock signal terminal high level
Go out the influence of transistor.
For this purpose, the present invention proposes a kind of pixel-driving circuit, including：
Signal output transistor and other transistors, the width of the signal output transistor source are less than other described crystalline substances
The width of body pipe source electrode, the width of the signal output transistor drain are more than the width of other transistor drains.
Preferably, the signal output transistor includes N number of sub- transistor, one end of n-th of sub- transistor drain and the
N-1 sub- transistor drains are connected, and the other end is connected with (n+1)th sub- transistor drain, and 1<n<N.
Preferably, the source width of at least one sub- transistor is less than other described transistors in N number of sub- transistor
Source width, the width of drain electrode is more than the width of other transistor drains.
Preferably, the source width of every sub- transistor is less than the source of other transistors in N number of sub- transistor
Pole width, the width of drain electrode are more than the width of other transistor drains.
Preferably, the width of the signal output transistor is equal with the width of other transistors, and the signal output is brilliant
The length of body pipe and the equal length of other transistors.
Preferably, the source width of the signal output transistor smaller than the source width of other transistors 0.3 to
0.5 micron.
Preferably, the width of the signal output transistor drain bigger than the width of other transistor drains 0.3 to
0.5 micron.
Preferably, foregoing circuit also includes：First signal input part, secondary signal input, the first input end of clock,
Two input end of clock, input and output end are reset,
The first transistor, grid and source electrode are connected to the first signal input part, and drain electrode is connected to the signal output crystal
The grid of pipe；
Second transistor, grid are connected to second clock input, and source electrode is connected to the first signal input part, drain electrode connection
To the grid of the signal output transistor；
Third transistor, grid and source electrode are connected to second clock input, and drain electrode is connected to the source electrode of the 7th transistor；
4th transistor, grid are connected to the drain electrode of third transistor, and source electrode is connected to second clock input, and drain electrode connects
It is connected to the source electrode of the 8th transistor；
5th transistor, grid are connected to replacement input, and source electrode is connected to the grid of the signal output transistor, leakage
Pole is connected to secondary signal input；
6th transistor, grid are connected to the source electrode of the 8th transistor, and source electrode is connected to the signal output transistor
Grid, grid are connected to secondary signal input；
7th transistor, grid are connected to the grid of the signal output transistor, and drain electrode is connected to secondary signal input
End；
8th transistor, grid are connected to the grid of the signal output transistor, and drain electrode is connected to secondary signal input
End；
9th transistor, grid are connected to second clock input, and source electrode is connected to output end, and drain electrode is connected to the second letter
Number input；
Tenth transistor, grid are connected to the source electrode of the 8th transistor, and source electrode is connected to output end, and drain electrode is connected to second
Signal input part；
11st transistor, grid are connected to reset signal end, and source electrode is connected to output end, and drain electrode is connected to secondary signal
Input；
First input end of clock is connected to the source electrode of the signal output transistor.
The present invention also proposes a kind of display base plate, including the pixel-driving circuit described in any of the above-described.
The invention also provides a kind of display device, including above-mentioned display base plate.
According to above-mentioned technical proposal, by reducing the source width of signal output transistor, source electrode and grid can be reduced
Facing area, so as to reduce the gate-source capacitance Cgs of signal output transistor.On the other hand by increasing signal output transistor
Drain width, so as to improve the gate leakage capacitance Cgd of signal output transistor, and then coupled voltages are reduced.Avoid
The grid of signal output transistor produces larger coupled voltages, improves the high temperature AD problems of signal output transistor.
Brief description of the drawings
The features and advantages of the present invention can be more clearly understood by reference to accompanying drawing, accompanying drawing is schematically without that should manage
Solve to carry out any restrictions to the present invention, in the accompanying drawings：
Fig. 1 shows that the comparison of signal output transistor according to an embodiment of the invention and other transistors is illustrated
Figure；
Fig. 2 shows the schematic diagram of pixel-driving circuit according to an embodiment of the invention；
Fig. 3 shows the schematic diagram of coupled voltages on signal output transistor according to an embodiment of the invention；
Fig. 4 shows the structural representation of signal output transistor according to an embodiment of the invention；
Fig. 5 is shown to be illustrated according to the comparison of the signal output transistor and other transistors of another embodiment of the invention
Figure.
Embodiment
It is below in conjunction with the accompanying drawings and specific real in order to be more clearly understood that the above objects, features and advantages of the present invention
Mode is applied the present invention is further described in detail.It should be noted that in the case where not conflicting, the implementation of the application
Feature in example and embodiment can be mutually combined.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still, the present invention may be used also
To be different from other modes described here using other to implement, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
As shown in figure 1, pixel-driving circuit according to an embodiment of the invention, including：
Signal output transistor M0 and other transistors, the width of signal output transistor M0 source electrodes 1 are less than other crystal
The width of pipe source electrode, the width of signal output transistor drain 2 are more than the width of other transistor drains.
As shown in Fig. 2 in a kind of GOA pixel-driving circuits, except comprising signal output transistor M0, also comprising other
Transistor.In the present embodiment, except signal output transistor M0, the width of other transistors (M1 to M11) drain electrode is equal, and
The width of source electrode is equal.
In Fig. 1 by taking transistor M1 source electrode and drain electrode as an example, carried out pair with signal output transistor M0 source electrode and drain electrode
Than explanation.The width Wd that the wherein width Ws of M0 source electrodes 1 is less than width Ws ', the M0 drain electrode 2 of M1 source electrodes is more than the width that M1 drains
Wd’.
As shown in figure 3, according to principle of charge conservation, the coupling of signal output transistor M0 grids in GOA pixel-driving circuits
Voltage VQ=(VH-VL) Cgs/ (Cgs+Cgd+Cs) is closed, wherein, VH and VL are the ceiling voltage of clock signal terminal respectively and minimum
Voltage, Cgs are the gate-source capacitances of signal output transistor, and Cgd is the gate leakage capacitance of signal output transistor, and Cs signal outputs are brilliant
Parasitic capacitance between body tube grid and drain electrode.
It can be seen from above formula, as long as parasitic capacitance Cs is sufficiently large, the influence of Cgs influence to coupled voltages with regard to very little, but
It is that Cs is become big, the time that the voltage of signal output transistor rises is elongated, influences output effect.
The present embodiment reduces the facing area of source electrode and grid by reducing the source width of signal output transistor, from
And reduce Cgs.On the other hand by increasing the drain width of signal output transistor, so as to improve Cgd, and then VQ drops make it that
It is low.The grid avoided in signal output transistor produces larger coupled voltages, improves the high temperature of signal output transistor
AD problems.
As shown in Figure 4, it is preferable that signal output transistor includes N number of sub- transistor, and the one of n-th of sub- transistor drain
End is connected with (n-1)th sub- transistor drain, and the other end is connected with (n+1)th sub- transistor drain, and 1<n<N.
In the present embodiment, the source electrode 1 of N number of sub- transistor can be connected to a data line 4, and in the He of source electrode 1
Grid 3 is additionally provided with drain electrode 2, certainly, gate insulation layer and active layer are additionally provided between grid 3 and source electrode 1, drain electrode 2
Etc. structure.
Each source electrode 1 of N number of sub- transistor in the present embodiment can serve as signal input part, and each drain electrode 2 can
So that as signal output part, even if individual small pin for the case transistor therein goes wrong and can not be normally-open, other sub- transistors are still
It can guarantee that the normal transmission of signal.
Preferably, the source width of at least one sub- transistor is wide less than the source electrode of other transistors in N number of sub- transistor
Degree, the width of drain electrode are more than the width of other transistor drains.
The present embodiment need to only change at least one sub- transistor source width and drain width, process in N number of sub- transistor
Relatively simple, the influence to GOA domains is smaller.
Preferably, the source width of every sub- transistor is less than the source width of other transistors, leakage in N number of sub- transistor
The width of pole is more than the width of other transistor drains.
The present embodiment can be adjusted to the source width of every individual sub- transistor and drain width in N number of sub- transistor,
So as to farthest reduce Cgs and improve Cgd, and then VQ is reduced as much as possible.
Preferably, the width of signal output transistor and the width of other transistors are equal, the length of signal output transistor
The equal length of degree and other transistors.It is in the case where signal output transistor includes more sub- transistors, then brilliant per height
The width of body pipe is equal with the width of other transistors, the length of every sub- transistor and the equal length of other transistors, with
Make the total length of signal output transistor in the present invention equal with the total length of signal output transistor in the prior art, the present invention
The overall width of middle signal output transistor is equal with the overall width of signal output transistor in the prior art.Wherein, signal output
The shape of transistor and other transistors can be U-shaped or L-shaped.
By taking U-shaped as an example, the drain electrode of signal output transistor and the drain electrode of other transistors are U-shaped, can be with setting signal
The distance between drain openings outer of output transistor and the distance between the drain openings outer of other transistors are equal, if
The drain openings portion of confidence output transistor to summit distance and other transistors drain openings portion to summit distance
It is equal.
As shown in figure 5, the present embodiment can be in the drain electrode 1 for changing signal output transistor M0 and the situation of the width of source electrode 2
Under, ensure drain electrode 1 entire length L1 and width L2 keep it is constant, namely signal output transistor M0 drain electrode 1 length L1 and its
His the length L1 ' of transistor (such as M1) drain electrode is equal, the width L2 ' phases that width L2 drains with other transistors (such as M1)
Deng.So that the adjustment to M source electrodes 1 and drain electrode 2 will not affect greatly to M0 charging effects, therefore filled without existing
Electric signal carries out the signal output transistor M0 that excessive adjustment is applicable to the present embodiment.
Preferably, the source width of signal output transistor is smaller than the source width of other transistors 0.3 to 0.5 micron.
The width of source electrode is reduced 0.3 to 0.5 micron, while effect can be stated in realization, avoids being blown during source conductive.
Preferably, the width of signal output transistor drain is bigger than the width of other transistor drains 0.3 to 0.5 micron.
The width of drain electrode is increased by 0.3 to 0.5 micron, while can stating effect in realization, ensures that source electrode will not contact with drain electrode,
Ensure the normal realization of transistor function.
As shown in Figure 2, it is preferable that foregoing circuit also includes：When the first signal input part, secondary signal input, first
Clock input, second clock input, input and output end are reset,
The first transistor M1, grid and source electrode are connected to the first signal input part STV, and drain electrode is connected to signal output crystal
Pipe M0 grid；
Second transistor M2, grid are connected to second clock input CLKB, and source electrode is connected to the first signal input part, leakage
Pole is connected to the grid of signal output transistor；
Third transistor M3, grid and source electrode are connected to second clock input CLKB, and drain electrode is connected to the 7th transistor
M7 source electrode；
4th transistor M4, grid are connected to third transistor M3 drain electrode, and source electrode is connected to second clock input
CLKB, drain electrode are connected to the 8th transistor M8 source electrode；
5th transistor M5, grid, which is connected to, resets input RESET, and source electrode is connected to the grid of signal output transistor
Pole, drain electrode are connected to secondary signal input；
6th transistor M6, grid are connected to the 8th transistor M8 source electrode, and source electrode is connected to signal output transistor M0
Grid, grid is connected to secondary signal input VSS；
7th transistor M7, grid are connected to signal output transistor M0 grid, and drain electrode is connected to secondary signal input
End 12；
8th transistor M8, grid are connected to signal output transistor M0 grid, and drain electrode is connected to secondary signal input
Hold VSS；
9th transistor M9, grid are connected to second clock input 22, and source electrode is connected to output end OUT, drain electrode connection
To secondary signal input VSS；
Tenth transistor M10, grid are connected to the 8th transistor M8 source electrode, and source electrode is connected to output end OUT, and drain electrode connects
It is connected to secondary signal input VSS；
11st transistor M11, grid are connected to reset signal end RESET, and source electrode is connected to output end OUT, and drain electrode connects
It is connected to secondary signal input VSS；
First input end of clock CLK is connected to signal output transistor M0 source electrode.
The present invention also proposes a kind of display base plate, includes the pixel-driving circuit of any of the above-described.
The invention also provides a kind of display device, including above-mentioned display base plate.
It should be noted that the display device in the present embodiment can be：Electronic Paper, mobile phone, tablet personal computer, television set,
Any product or part with display function such as notebook computer, DPF, navigator.
Technical scheme is described in detail above in association with accompanying drawing, it is contemplated that in the prior art, pixel-driving circuit
In signal output transistor gate can be influenceed by coupled voltages and high temperature AD occur.Technique according to the invention scheme,
By reducing the source width of signal output transistor, the facing area of source electrode and grid can be reduced, it is defeated so as to reduce signal
Go out the gate-source capacitance Cgs of transistor.On the other hand it is defeated so as to improve signal by increasing the drain width of signal output transistor
Go out the gate leakage capacitance Cgd of transistor, and then coupled voltages are reduced.Avoid signal output transistor grid produce compared with
Big coupled voltages, improve the high temperature AD problems of signal output transistor.
In the present invention, term " first " to " the 11st " is only used for describing purpose, and it is not intended that instruction or hint
Relative importance.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (10)
- A kind of 1. pixel-driving circuit, it is characterised in that including：Signal output transistor and other transistors, the width of the signal output transistor source are less than other described transistors The width of source electrode, the width of the signal output transistor drain are more than the width of other transistor drains.
- 2. circuit according to claim 1, it is characterised in that the signal output transistor includes N number of sub- transistor, the One end of n sub- transistor drains is connected with (n-1)th sub- transistor drain, the other end and (n+1)th sub- transistor drain phase Even, 1<n<N.
- 3. circuit according to claim 2, it is characterised in that at least one sub- transistor in N number of sub- transistor Source width is less than the source width of other transistors, and the width of drain electrode is more than the width of other transistor drains.
- 4. circuit according to claim 2, it is characterised in that the source electrode of every sub- transistor in N number of sub- transistor Width is less than the source width of other transistors, and the width of drain electrode is more than the width of other transistor drains.
- 5. circuit according to any one of claim 1 to 4, it is characterised in that the width of the signal output transistor It is equal with the width of other transistors, the length of the signal output transistor and the equal length of other transistors.
- 6. circuit according to any one of claim 1 to 4, it is characterised in that the source electrode of the signal output transistor Width is smaller than the source width of other transistors 0.3 to 0.5 micron.
- 7. circuit according to any one of claim 1 to 4, it is characterised in that the signal output transistor drain Width is bigger than the width of other transistor drains 0.3 to 0.5 micron.
- 8. circuit according to any one of claim 1 to 4, it is characterised in that also include：First signal input part, Binary signal input, the first input end of clock, second clock input, replacement input and output end,The first transistor, grid and source electrode are connected to the first signal input part, and drain electrode is connected to the signal output transistor Grid；Second transistor, grid are connected to second clock input, and source electrode is connected to the first signal input part, and drain electrode is connected to institute State the grid of signal output transistor；Third transistor, grid and source electrode are connected to second clock input, and drain electrode is connected to the source electrode of the 7th transistor；4th transistor, grid are connected to the drain electrode of third transistor, and source electrode is connected to second clock input, and drain electrode is connected to The source electrode of 8th transistor；5th transistor, grid are connected to replacement input, and source electrode is connected to the grid of the signal output transistor, and drain electrode connects It is connected to secondary signal input；6th transistor, grid are connected to the source electrode of the 8th transistor, and source electrode is connected to the grid of the signal output transistor, Grid is connected to secondary signal input；7th transistor, grid are connected to the grid of the signal output transistor, and drain electrode is connected to secondary signal input；8th transistor, grid are connected to the grid of the signal output transistor, and drain electrode is connected to secondary signal input；9th transistor, grid are connected to second clock input, and source electrode is connected to output end, and it is defeated that drain electrode is connected to secondary signal Enter end；Tenth transistor, grid are connected to the source electrode of the 8th transistor, and source electrode is connected to output end, and drain electrode is connected to secondary signal Input；11st transistor, grid are connected to reset signal end, and source electrode is connected to output end, and drain electrode is connected to secondary signal input End；First input end of clock is connected to the source electrode of the signal output transistor.
- 9. a kind of display base plate, it is characterised in that including the pixel-driving circuit any one of claim 1 to 8.
- 10. a kind of display device, it is characterised in that including the display base plate described in claim 9.
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| CN201610006936.4A CN105405388B (en) | 2016-01-05 | 2016-01-05 | Pixel-driving circuit, display base plate and display device |
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| CN110619856A (en) * | 2019-08-23 | 2019-12-27 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101022129A (en) * | 2007-03-26 | 2007-08-22 | 电子科技大学 | Metal-semiconductor field effect transistor with source-drain double-concave structure |
| CN102278935A (en) * | 2011-04-25 | 2011-12-14 | 北京大学 | Method for estimating relative position of radiation displacement damage area of COMS (Complementary Metal Oxide Semiconductor) device in channel |
| CN103117221A (en) * | 2011-11-16 | 2013-05-22 | 中国科学院微电子研究所 | HEMT device and manufacturing method thereof |
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| JP2002050767A (en) * | 2000-08-04 | 2002-02-15 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| US6972448B2 (en) * | 2000-12-31 | 2005-12-06 | Texas Instruments Incorporated | Sub-lithographics opening for back contact or back gate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101022129A (en) * | 2007-03-26 | 2007-08-22 | 电子科技大学 | Metal-semiconductor field effect transistor with source-drain double-concave structure |
| CN102278935A (en) * | 2011-04-25 | 2011-12-14 | 北京大学 | Method for estimating relative position of radiation displacement damage area of COMS (Complementary Metal Oxide Semiconductor) device in channel |
| CN103117221A (en) * | 2011-11-16 | 2013-05-22 | 中国科学院微电子研究所 | HEMT device and manufacturing method thereof |
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