CN202102694U

CN202102694U - Shift register for thin-film transistor, liquid-crystal panel and display equipment

Info

Publication number: CN202102694U
Application number: CN2011201707276U
Authority: CN
Inventors: 孙阳
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2011-05-25
Filing date: 2011-05-25
Publication date: 2012-01-04
Anticipated expiration: 2021-05-25

Abstract

The utility model discloses a low-power-consumption shift register for a thin-film transistor, wherein a control signal and the thin-film transistor (TFT) are added to the output part of a shift-registering function part of the shift register, a source electrode of the TFT is connected with the control signal, a grid electrode is connected with a highly-drawing point, and a drain electrode is connected with an output end. The utility model also discloses a liquid-crystal panel which integrates the shift register and display equipment which comprises the liquid-crystal panel. Through the devices, output power consumption and noise interference caused by a capacitance-coupling effect can be avoided, the low power consumption of the shift register can be realized, and the service life of the shift register is further longer.

Description

Thin film transistor shift register, liquid crystal panel and display device

Technical Field

The utility model relates to a LCD's shift register technique especially relates to a thin film transistor shift register, liquid crystal display panel and display device.

Background

The goa (Gate Drive on array) technology is a high-level design in the liquid crystal flat Panel display, and the basic concept is to integrate the Gate driver (Gate driver) of the liquid crystal Panel (LCD Panel) on the glass substrate to form the scan Drive for the liquid crystal Panel, wherein the Gate driver includes the shift register. Compared with the traditional Chip On Flex (COF) process and the process of directly binding the Chip On Glass (COG), the GOA technology not only saves the cost, but also enables the liquid crystal panel to achieve the aesthetic design with symmetrical two sides, saves the welding area (Bonding area) of a Gate drive integrated circuit (Gate IC) and the wiring space of a Fan-out (Fan-out), and further can realize the design of a narrow frame; meanwhile, the process of Bonding in the Gate direction can be omitted, so that the improvement of the productivity and the excellent rate of products is facilitated.

However, the design of GOAs also presents certain problems compared to COF and COG technologies, such as: and a problem of shortened circuit life due to threshold voltage shift (Vth shift) of amorphous silicon (a-Si) for long-term operation. In addition, since a-Si has low mobility, in order to satisfy the requirement of high Ion (Ion) of some Thin Film Transistors (TFTs) in a circuit, it can be satisfied only by increasing the channel width of the TFT, which may result in an increase in size in space and an increase in power consumption. In the design of the GOA of an actual product, how to use the minimum circuit components to realize the shift register function and ensure low power consumption and long-term stable operation is a key problem of the GOA design.

SUMMERY OF THE UTILITY MODEL

In view of this, the present invention provides a low power consumption thin film transistor shift register, a liquid crystal panel and a display device, which can solve the problems of high power consumption and short service life of the shift register.

In order to achieve the above purpose, the technical scheme of the utility model is realized like this:

the utility model provides a thin film transistor shift register, include: a shift register function part composed of four thin film transistors TFTM1, M2, M3, M4 and a capacitor C1, and an auxiliary part composed of eight TFTM5, M6, M8, M9, M10, M11, M12 and M13; wherein,

in the shift register functional part, the input end is connected with the source and the gate of M1, the drain of M1, the source of M2 and the gate of M3 are connected with a pull-up PU point, the gates of M2 and M4 are connected with a reset end, the drains of M2 and M4 are grounded, the clock end is connected with the source of M3, and the drain of M3 is connected with the PU point through C1 to form the output part of the shift register functional part;

in the auxiliary part, M5, M6, M8 and M9 for controlling the pull-down of a PD point are connected with the gates of M10 and M11 through the PD point, the drains of M10, M11 and M12 are grounded, the source of M10 is connected with a PU point, the sources of M11, M12 and M4 are connected with the output end in the output part, and the gate of M13 is connected with the PU point;

the output part of the shift register functional part is added with a VDD control signal and a TFT, the source electrode of the TFT is connected with the VDD control signal, the grid electrode is connected with a PU point, and the drain electrode is connected with the output end.

The VDD control signal is a direct current signal.

The utility model also provides a liquid crystal display panel, integrated the shift register as set forth in claim 1 or 2 on liquid crystal display panel's the glass substrate.

The utility model also provides a display device, including liquid crystal display panel, integrated the shift register as set forth in claim 1 or 2 on liquid crystal display panel's the glass substrate.

The utility model provides a low-power consumption thin film transistor shift register, liquid crystal display panel and display device shift register's output section increases a VDD control signal and a TFT, TFT's source electrode is connected the PU point is connected to VDD control signal, grid, the OUT is connected to the drain electrode. Therefore, output power consumption and noise interference caused by the capacitive coupling effect can be avoided, and therefore the shift register can achieve low power consumption and further has longer service life.

Drawings

Fig. 1 is a circuit configuration diagram of a shift register of 12T1C configuration;

fig. 2 is a circuit diagram of a low power consumption tft shift register according to the present invention.

Detailed Description

The basic idea of the utility model is that: and a VDD control signal and a TFT are added to an output part of the shift register, and the source electrode of the TFT is connected with the VDD control signal, the grid electrode of the TFT is connected with a PU point, and the drain electrode of the TFT is connected with OUT.

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

For better understanding of the present invention, the basic structure of a shift register composed of twelve TFTs and a capacitor (12T1C) unit will be described first. Fig. 1 is a circuit structure diagram of a shift register with a 12T1C structure, as shown in fig. 1, the shift register includes twelve TFTs and a capacitor, which includes: a shift register function portion constituted by four TFTs (M1, M2, M3, M4) and one capacitor (C1), and an auxiliary portion constituted by eight TFTs (M5, M6, M8, M9, M10, M11, M12, M13); wherein,

in the shift register functional part, the input end is connected with the source and the gate of M1, the drain of M1, the source of M2 and the gate of M3 are connected with a pull-up (PU) point, the gates of M2 and M4 are connected with a reset end, the drains of M2 and M4 are grounded, the clock end is connected with the source of M3, and the drain of M3 is connected with the PU point through C1 to form the output part of the shift register functional part;

in the auxiliary part, M5, M6, M8 and M9 for controlling a pull-down (PD) point are connected with gates of M10 and M11 through the PD point, drains of M10, M11 and M12 are grounded, a source of M10 is connected with a PU point, sources of M11, M12 and M4 are connected with an output end in the output part, and a gate of M13 is connected with the PU point;

specifically, M1, M2, M3, M4 and the capacitor C1 in the shift register function section realize the most basic shift register function: when the signal of the INPUT terminal (INPUT) is at a high potential, the thin film transistor M1 is turned on to charge the PU node, when the signal of the clock terminal (CLK) is at a high potential, the thin film transistor M3 turns on the output terminal (OUT) to output the pulse of CLK, and simultaneously the bootstrap (boosting) action of the capacitor C1 further pulls up the potential of the PU node; then, the signal at the RESET terminal (RESET) of the downstream output turns on the thin film transistors M2 and M4 to be connected to the ground terminal (VSS), discharging the PU node and OUT. However, in the most basic shift register (4T1C) implementation, the parasitic capacitance of M3 can cause large power consumption and noise.

Therefore, an auxiliary part is further added on the basis of 4T1C, wherein, four TFTs of M5, M6, M8 and M9 are used for controlling the voltage of a PD point, and then PU and OUT are discharged through the thin film transistors M10 and M11; the thin film transistor M12 is used to assist in suppressing OUT noise, and the thin film transistor M13 assists in charging and discharging the PU dot.

Although the improved 12T1C circuit can suppress noise, the charged tft M3 is large in size and directly connected to CLK, which results in large power consumption. In addition, since the tft M3 is large in size and has a large parasitic capacitance, it is difficult to completely eliminate circuit noise.

Fig. 2 is a circuit structure diagram of a low power consumption TFT shift register, as shown in fig. 2, a VDD control signal and a TFT (M7) are added to the output portion of the shift register function portion, the source of the TFT is connected to the VDD control signal, the gate is connected to the PU point, and the drain is connected to the OUT terminal.

The VDD control signal is a direct current signal; the output of the thin film transistor M3 is connected with the PU point through a capacitor C1, and the thin film transistor M4 is still connected with the output end; the output part of the shift register function part is the OUT position shown in fig. 1.

This design can avoid power consumption and noise interference of the CLK signal to the output due to the capacitive coupling effect of the capacitor C1. Therefore, the shift register can realize low power consumption and further has longer service life.

The embodiment of the utility model provides a still provide a liquid crystal display panel, the integration has the low-power consumption shift register that figure 2 shows on this liquid crystal display panel's the glass substrate.

Further, the embodiment of the utility model provides a display device is still provided, this display device includes liquid crystal display panel, integrated on liquid crystal display panel's the glass substrate has the low-power consumption shift register that figure 2 shows. Here, the display device may be a device having a display function, such as a mobile phone, a notebook computer, a tablet computer, a liquid crystal display, and a monitor.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A thin film transistor shift register, comprising: a shift register function part composed of four thin film transistors TFTM1, M2, M3, M4 and a capacitor C1, and an auxiliary part composed of eight TFTM5, M6, M8, M9, M10, M11, M12 and M13; wherein,

the shift register circuit is characterized in that a VDD control signal and a TFT are added to an output part of the shift register function part, and a source electrode of the TFT is connected with the VDD control signal, a grid electrode of the TFT is connected with a PU point, and a drain electrode of the TFT is connected with an output end.

2. The shift register of claim 1, wherein the VDD control signal is a dc signal.

3. A liquid crystal panel characterized in that the shift register according to claim 1 or 2 is integrated on a glass substrate of the liquid crystal panel.

4. A display device comprising a liquid crystal panel, characterized in that the shift register according to claim 1 or 2 is integrated on a glass substrate of the liquid crystal panel.