CN105405383B - Shifting deposit unit, shift register and its driving method, display device - Google Patents
Shifting deposit unit, shift register and its driving method, display device Download PDFInfo
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- CN105405383B CN105405383B CN201510993310.2A CN201510993310A CN105405383B CN 105405383 B CN105405383 B CN 105405383B CN 201510993310 A CN201510993310 A CN 201510993310A CN 105405383 B CN105405383 B CN 105405383B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
This application discloses shifting deposit unit, shift register and its driving method, display device.The shifting deposit unit includes the first transistor, second transistor, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the first electric capacity, the second electric capacity, the 3rd electric capacity, input signal end, the first clock signal terminal, second clock signal end, first voltage signal end, second voltage signal end and the first output end.Shifting deposit unit, shift register and its driving method of the embodiment of the present application offer, display device, the displacement for realizing signal by small number of transistor exports, reduce the power consumption of shift register, node potential competition and transistor threshold drift can be avoided to cause circuit malfunction simultaneously, enhance the stability of circuit operation.
Description
Technical field
The application is related to display technology field, and in particular to shifting deposit unit, shift register and its driving method, shows
Showing device.
Background technology
Can be provided with a kind of conventional design of display panel, on display panel pel array, a plurality of grid line, with it is more
The intersecting data wire of bar grid line insulation.In addition, gate driving circuit is also provided with display panel.Gate driving circuit will
After the individual pulse signal of input shifts step by step, each grid line is sequentially turned on, realizes that the row of pel array is swept on display panel
Retouch.
Fig. 1 shows a kind of structural representation of a driver element of existing gate driving circuit, described driving
Unit is used to drive a grid line.As shown in figure 1, driver element 100 includes shifting deposit unit 11 and phase inverter 12.Wherein move
Position deposit unit 11 exports after being used for the individual pulse signal displacement by input, and phase inverter 12 is used for shifting deposit unit 11 is defeated
Exported after the signal inversion gone out.Driver element 100 shown in Fig. 1 includes MA1 to MA12 totally 12 transistors.Rank is shifted in signal
Section, NA2 nodes are low potential, and MA4 is turned on, and the CKA2 low level signals inputted are transferred to the output of shifting deposit unit 11
Hold next.At this moment, output end next controls MA2 conductings, and high level signal VGH is transferred into NA1 nodes, so as to which MA5 be closed.
Because transistor MA5 is just closed after transistor MA4 the second pole output low level signal, transistor MA4 the second pole is to defeated
Go out to hold next to transmit between low level signal and transistor MA5 closings and there may be the time difference.The crystal within this time difference
Pipe MA4 and transistor MA5 are simultaneously turned on so that the problem of node potential competition in circuit are present, caused output end next to export
Jitter.
Fig. 2 shows the structural representation of a driver element of another existing gate driving circuit.Shown in Fig. 2
Circuit 200 in, using the initial signal of high level, when the level signal of CKB2 inputs is changed into low level by high level signal
During signal, due to electric capacity CB1 coupling so that NB1 node potentials reduce, transistor MB2 conductings, MB5 cut-offs, so it is high
Level signal VGH can not be transferred to NB1 nodes.NB1 nodes keep low potential so that transistor MB9 and MB10 the second pole it
Between occur node potential competition, the signal VGH of high level can not be normally transferred to output end E1, circuit can not normally input height
The shift signal of level.
The content of the invention
The problem of node potential competition in both the above existing design be present, and number of transistors is more, driving electricity
The power consumption on road is larger.In view of this, it is desired to be able to which a kind of shift register for reducing number of transistors is provided.Further, also
It is expected to provide a kind of shift register that can be avoided node potential competition, ensure circuit stability.In order to solve said one
Or multiple problems, this application provides shifting deposit unit, shift register and its driving method, display device.
In a first aspect, this application provides a kind of shifting deposit unit, including the first transistor, second transistor, the 3rd
Transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the first electric capacity, the second electric capacity, the 3rd electricity
Appearance, input signal end, the first clock signal terminal, second clock signal end, first voltage signal end, second voltage signal end and
First output end.Wherein, the signal that the first transistor is inputted by the input signal end controls, for electric by described first
The signal of pressure signal end input is transferred to first node；The signal that the second transistor is inputted by first clock signal terminal
Control, the signal for the input signal end to be inputted are transferred to section point；The third transistor is defeated by described first
Go out the signal control of end output, the signal for the second clock signal end to be inputted is transferred to the 3rd node；Described 4th
Transistor is controlled by the electric potential signal of the first node, for the signal that inputs first clock signal terminal or described the
The signal of two voltage signal ends input is transferred to fourth node；5th transistor by the section point electric potential signal control
System, the signal for the first voltage signal end to be inputted are transferred to the fourth node；6th transistor is by described
The electric potential signal control of fourth node, the signal for the first voltage signal end to be inputted are transferred to first output
End；7th transistor is controlled by the electric potential signal of the section point, for input the second voltage signal end
Signal is transferred to first output end；One end of first electric capacity is used for the letter for inputting the first clock signal terminal input
Number, the other end of first electric capacity is used for the electric potential signal for inputting the first node；One end of second electric capacity is used for
The electric potential signal of the 3rd node is inputted, the other end of second electric capacity is used for the current potential letter for inputting the section point
Number；One end of 3rd electric capacity is used for the signal for inputting the first voltage signal end, and the other end of the 3rd electric capacity is used
In the electric potential signal for inputting the fourth node.
Second aspect, this application provides a kind of shift register, including N number of cascade that the application first aspect is provided
Shifting deposit unit, wherein N is positive integer and N>1；Posted for the displacement at the input signal end of first order shifting deposit unit
The shift signal input of storage, the input letter of every one-level shifting deposit unit in the second level to N level shifting deposit units
Number end is connected with the first output end of upper level shifting deposit unit.
The third aspect, a kind of method of the shift register provided this application provides driving the application second aspect,
Including：First stage, the first level signal is provided to first clock signal terminal and the input signal end, to described second
Clock signal terminal provides second electrical level signal, and first output end exports second voltage signal；Second stage, to described first
Clock signal terminal provides the second electrical level signal, and described the is provided to the input signal end and the second clock signal end
One level signal, first output end export first voltage signal；Phase III, institute is provided to first clock signal terminal
The first level signal is stated, the second electrical level signal is provided to the input signal end and the second clock signal end, it is described
First output end exports the first voltage signal；Fourth stage, provided to first clock signal terminal and input signal end
The second electrical level signal, first level signal, the first output end output are provided to the second clock signal end
The second voltage signal；In 5th stage, first level signal is provided to first clock signal terminal, to the input
Signal end and the second clock signal end provide the second electrical level signal, and first output end exports the second voltage
Signal.
Fourth aspect, the side of the shift register provided this application provides another driving the application second aspect
Method, including：In the first stage, first level signal is provided to first clock signal terminal, believed to the second clock
Number, the input signal end second electrical level signal is provided, first output end exports the first voltage signal；
Two-stage, the second electrical level signal is provided to first clock signal terminal, the input signal end, to the second clock
Signal end provides first level signal, and first output end exports the second voltage signal；In the phase III, to institute
First clock signal terminal, input signal end offer first level signal are provided, provided to the second clock signal end
The second electrical level signal, first output end export the second voltage signal；In fourth stage, to first clock
Signal end provides the second electrical level signal, and first electricity is provided to the second clock signal end, the input signal end
Ordinary mail number, first output end export the first voltage signal；In the 5th stage, to first clock signal terminal, defeated
Enter signal end and first level signal is provided, the second electrical level signal is provided to the second clock signal end, described the
One output end exports the first voltage signal.
5th aspect, this application provides a kind of display device, the shift LD provided using the application first aspect
The driving method that the driving method or the application fourth aspect that unit and the application third aspect provide provide.
Shifting deposit unit, shift register and its driving method of the application offer, display device, pass through lesser amt
Transistor realize signal displacement output, reduce the power consumption of shift register, while can avoid in shifting deposit unit
Node potential competition, which occurs, during the current potential reversion of output end causes circuit malfunction, enhances the stability of circuit operation.
Brief description of the drawings
Non-limiting example is described in detail with reference to what the following drawings was made by reading, other features,
Objects and advantages will become more apparent upon：
Fig. 1 is a kind of structural representation of a driver element of existing gate driving circuit；
Fig. 2 is the structural representation of a driver element of another existing gate driving circuit；
Fig. 3 is the electrical block diagram of a specific embodiment of the shifting deposit unit that the application provides；
Fig. 4 is the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides；
Fig. 5 is the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides；
Fig. 6 is the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides；
Fig. 7 is the structural representation of the one embodiment for the shift register that the application provides；
Fig. 8 is a working timing figure of the circuit structure in embodiment illustrated in fig. 3；
Fig. 9 is a working timing figure of the circuit structure in embodiment illustrated in fig. 6；
Figure 10 is another working timing figure of the circuit structure in embodiment illustrated in fig. 3.
Embodiment
The application is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining related invention, rather than the restriction to the invention.It also should be noted that in order to
Be easy to describe, illustrate only in accompanying drawing to about the related part of invention.
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase
Mutually combination.Describe the application in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
Fig. 3 is refer to, the circuit knot of first specific embodiment of the shifting deposit unit provided it illustrates the application
Structure schematic diagram.As shown in figure 3, shifting deposit unit 300 include the first transistor M1, second transistor M2, third transistor M3,
4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the first electric capacity C1, the second electric capacity C2,
Three electric capacity C3, input signal end IN, the first clock signal terminal CK, second clock signal end XCK, first voltage signal end VGH,
Two voltage signal end VGL and the first output end EOUT.
In shifting deposit unit 300, the signal that the first transistor M1 is inputted by input signal end IN controls, for by the
The signal of one voltage signal end VGH inputs is transferred to first node N1；Second transistor M2 is by the first clock signal terminal CK
The signal control of input, the signal for the input signal end IN to be inputted are transferred to section point N2；Third transistor M3
Controlled by the signal of the first output end EOUT outputs, the signal for second clock signal end XCK to be inputted is transferred to Section three
Point N3；4th transistor M4 is controlled by first node N1 electric potential signal, for the signal for inputting the first clock signal terminal CK
It is transferred to fourth node N4；5th transistor M5 is controlled by section point N2 electric potential signal, for by first voltage signal end
The signal of VGH inputs is transferred to fourth node N4；6th transistor M6 is controlled by fourth node N4 electric potential signal, for by the
The signal VGH of one voltage signal end input is transferred to the first output end EOUT；The 7th transistor M7 is by described second
Node N2 electric potential signal control, the signal for the second voltage signal end VGL to be inputted are transferred to first output
Hold EOUT；First electric capacity C1 one end is used for the signal for inputting the first clock signal terminal CK inputs, the first electric capacity C1 other end
For inputting first node N1 electric potential signal；Second electric capacity C2 one end is used for the electric potential signal for inputting the 3rd node N3, the
The two electric capacity C2 other end is used for the electric potential signal for inputting section point N2；3rd electric capacity C3 one end is used to input first voltage
Signal end VGH signal, the 3rd electric capacity C3 other end are used for the electric potential signal for inputting fourth node N4.
Specifically, the first transistor M1 grid is connected with input signal end IN, the first transistor M1 the first pole and the
One voltage signal end VGH connections, the first transistor M1 the second pole are connected with first node N1.Second transistor M2 grid with
First clock signal terminal CK connections, second transistor M2 the first pole are connected with input signal end IN, and the of second transistor M2
Two poles are connected with section point N2.First output end EOUT connections of third transistor M3 grid and shifting deposit unit, the
Three transistor M3 the first pole is connected with second clock signal end XCK, and third transistor M3 the second pole and the 3rd node N3 connect
Connect.4th transistor M4 grid is connected with first node N1, the 4th transistor M4 the first pole and the first clock signal terminal CK
Connection, the 4th transistor M4 the second pole is connected with fourth node N4.5th transistor M5 grid is connected with section point N2,
5th transistor M5 the first pole is connected with first voltage signal end VGH, the 5th transistor M5 the second pole and fourth node N4
Connection；6th transistor M6 grid is connected with fourth node N4, the 6th transistor M6 the first pole and first voltage signal end
VGH connections, the 6th transistor M6 the second pole are connected with the first output end EOUT.7th transistor M7 grid and section point
N2 connections, the 7th transistor M7 the first pole are connected with second voltage signal end VGL, the 7th transistor M7 the second pole and first
Output end EOUT connections.First electric capacity C1 one end is connected with the first clock signal terminal CK, the first electric capacity C1 other end and
One node N1 connections.Second electric capacity C2 one end is connected with the 3rd node N3, the second electric capacity C2 other end and section point N2
Connection.3rd electric capacity C3 one end is connected with first voltage signal end VGH, and the 3rd electric capacity the C3 other end and fourth node N4 connect
Connect.
In the above-described embodiments, the current potential for controlling the 3rd node N3 by the first output end EOUT of shifting deposit unit is believed
Number, then the coupling by the second electric capacity C2, section point N2 current potential is further influenceed, can compensate for the 7th transistor M7 threshold
Value drift, ensure shift signal totally tansitive to the output end of shifting deposit unit.Also, in the output end of shifting deposit unit
At the time of the signal upset of EOUT outputs, the current potential of section point and fourth node is not exported by the output end of shifting deposit unit
Signal influence, therefore the problem of in the absence of node potential competition, enhance the stability of circuit.In addition, during using two
Clock signal and small number of transistor are the displacement that signal can be achieved, and can reduce driving power consumption, be advantageous to setting for narrow frame
Meter.
With further reference to Fig. 4, the electricity of another specific embodiment of the shifting deposit unit provided it illustrates the application
Line structure schematic diagram.From fig. 4, it can be seen that it is only that with the distinguishing feature of embodiment illustrated in fig. 3, shifting deposit unit
The 4th transistor M4 the first pole is connected with second voltage signal end VGL in 400.Because VGL signals are a kind of direct currents of stabilization
Signal, and the first clock signal terminal CK is a kind of pulse signal, its stability is not so good as direct current signal, during continuous upset
Fourth node N4 stability can be influenceed.Therefore, the of the 4th transistor M4 in the shifting deposit unit 400 that the present embodiment provides
One pole is connected the stability that can ensure fourth node N4 with second voltage signal end VGL not by the 4th transistor M4 the first pole
The influence of input signal.When the first output end EOUT exports high level signal, the present embodiment can ensure the 4th transistor M4
Transmitted for low level signal, so as to which fourth node N4 current potential is maintained at into low potential so that the 6th transistor M6 is kept
Conducting state, the first output end EOUT output high level signals, the signal for avoiding the first clock signal terminal CK from inputting are overturn
When fourth node N4 current potential is impacted, enhance the stability of circuit.
With further reference to Fig. 5, the electricity of another specific embodiment of the shifting deposit unit provided it illustrates the application
Line structure schematic diagram.As shown in figure 5, the shifting deposit unit 500 that the present embodiment is provided is in the shifting deposit unit shown in Fig. 3
The 8th transistor M8 can also be included on the basis of 300.8th transistor M8 is controlled by fourth node N4 electric potential signal, by the
The signal of one voltage signal inputs VGH inputs is transferred to the 3rd node N3.Specifically, the 8th transistor M8 grid and the 4th
Node N4 connections, the 8th transistor M8 the first pole are connected with first voltage signal end VGH, the 8th transistor M8 the second pole with
3rd node N3 connections.
From figure 5 it can be seen that compared with embodiment illustrated in fig. 3, increased 8th transistor M8 can be in fourth node
Under the control of N4 electric potential signal, the first voltage signal end VGH high level signals inputted are transferred to the 3rd node N3.
When two node N2 current potential is high potential, the 3rd node N3 current potential is maintained into high potential, avoids the 3rd node N3 from being in outstanding
Floating state, and then guarantee section point N2 current potential is low potential, the first output end EOUT normally exports low level signal, enhancing
The stability of circuit.
Fig. 6 is refer to, the circuit knot of another specific embodiment of the shifting deposit unit provided it illustrates the application
Structure schematic diagram.As shown in fig. 6, the shifting deposit unit 600 that the present embodiment is provided is in the shifting deposit unit 400 shown in Fig. 3
On the basis of can also include the 9th transistor M9, the tenth transistor M10, the 11st transistor M11, the 4th electric capacity C4 and the
Two output end SOUT.Wherein, the second output end SOUT is used to export gate drive signal.9th transistor M9 is by section point N2
Electric potential signal control, the signal for first voltage signal end VGH to be inputted is transferred to the second output end SOUT.Tenth crystal
Pipe M10 is controlled by fourth node N4 electric potential signal, and it is defeated that the signal for second clock signal end XCK to be inputted is transferred to second
Go out to hold SOUT.The signal that 11st transistor M11 is exported by the second output end SOUT controls, for by first voltage signal end
The signal of VGH inputs is transferred to section point N2.4th electric capacity C4 one end is used for the electric potential signal for inputting fourth node N4, the
The four electric capacity C4 other end is used for the signal for inputting the second output end SOUT outputs.
In the embodiment shown in fig. 6, the letter that the first output end EOUT inputs input signal end IN in shifting deposit unit
Number displacement after shift signal is exported.The signal of first output end EOUT outputs can be as the defeated of next stage shifting deposit unit
Enter signal.The scan line that second output end SOUT of shifting deposit unit is used to drive to shifting deposit unit exports raster data model
Signal.
Specifically, in the embodiment shown in fig. 6, the 9th transistor M9 grid is connected with section point N2, the 9th crystal
Pipe M9 the first pole is connected with first voltage signal end VGH, the 9th transistor M9 the second pole and the second output end SOUT
Connection.Tenth transistor M10 grid is connected with fourth node N4, the tenth transistor M10 the first pole and second clock signal
XCK connections are held, the tenth transistor M10 the second pole is connected with the second output end SOUT.The grid and second of 11st transistor
Output end SOUT connections, the 11st transistor M11 the first pole are connected with first voltage signal end VGH, the 11st transistor M11
The second pole be connected with section point N2.4th electric capacity C4 one end is connected with fourth node N4, the 4th electric capacity C4 other end
It is connected with the second output end SOUT.
Unlike embodiment illustrated in fig. 3, the shifting deposit unit 600 shown in Fig. 6 can realize shift signal and grid
Pole drive signal exports simultaneously, also, because when the second output end SOUT exports low level signal, the 11st transistor M11 is led
It is logical, the first voltage signal end VGH high level signals inputted are transferred to section point N2, exported in the second output end SOUT low
Section point N2 current potential is maintained into high potential during level signal, avoids node potential competition, enhances the stabilization of circuit
Property.
It should be noted that the transistor in the shifting deposit unit that each embodiment of the application is provided can be that p-type is brilliant
Body pipe or N-type transistor.Although Fig. 3 schematically illustrates the structure of shifting deposit unit into Fig. 6 with P-type transistor,
The restriction to transistor types in the application is not formed.
The embodiment of the present application additionally provides a kind of shift register for including above-mentioned shifting deposit unit.Fig. 7 is refer to, its
Show the structural representation of the one embodiment for the shift register that the application provides.As shown in fig. 7, shift register 700
Include the shifting deposit unit of N number of cascade, wherein, 71,72,73,74 ..., 7 (N-1), 7N represent first order shift LD respectively
Unit, second level shifting deposit unit, third level shifting deposit unit, fourth stage shifting deposit unit ..., (N-1) level move
Position deposit unit and N level shifting deposit units.Wherein, N is positive integer and N>1.Can be per one-level shifting deposit unit with
For upper combination Fig. 3 to any one shifting deposit unit described in Fig. 6, the input signal end of first order shifting deposit unit is shifting
The shift signal input IN of bit register, for inputting shift signal.For n-th grade of shift register, its input signal is
(n-1)th grade of the first output end of shift register EOUT output signal：N is the positive integer more than 1, and no more than N.Moved per one-level
Position deposit unit is connected with the first clock signal terminal CK and second clock signal end XCK.Can be with per one-level shifting deposit unit
Including the second output end SOUT.Such as first order shifting deposit unit 71, second level shifting deposit unit 72, the third level in Fig. 7
Shifting deposit unit 73, fourth stage shifting deposit unit 74, (N-1) level shifting deposit unit 7 (N-1) and the displacement of N levels are posted
Memory cell 7N the first output end is respectively EOUT1, EOUT2, EOUT3, EOUT4, EOUT (N-1), EOUT (N), and second exports
End is respectively SOUT1, SOUT2, SOUT3, SOUT4, SOUT (N-1), SOUT (N).
In further embodiments, each shifting deposit unit of shift register can also cascade as follows：N
Shift signal input of the input signal end of level shifting deposit unit as shift register, n-th grade of shift register, its is defeated
Enter output signal of the signal for (n+1)th grade of the first output end of shift register EOUT：N is the positive integer more than 1, and less than N.
The embodiment of the present application additionally provides a kind of driving method applied to above-mentioned shift register.With further reference to Fig. 8,
It illustrates the working timing figure of the shifting deposit unit in embodiment illustrated in fig. 3.
Below so that the transistor in each embodiment is P-type transistor as an example, illustrate the shift register that the application provides
Driving method operation principle.Wherein, the first level is high level, and second electrical level is low level, and first voltage is high voltage,
Second voltage is low-voltage.In actual applications, each transistor can also be N-type transistor in shifting deposit unit, at this moment
First level is low level, and second electrical level is high level, and first voltage is low-voltage, and second voltage is high voltage.
As shown in figure 8, a moment before T1, the first clock signal terminal CK input second electrical levels are believed in the first stage
Number, control second transistor M2 conducting, the IN second electrical level signals inputted in input signal end are transferred to section point N2, by the
Two node N2 current potential is set to low potential.5th transistor M5 is turned under section point N2 low potential control, by the first electricity
The first voltage signal of pressure signal end VGH inputs is transferred to fourth node N4.The second electrical level signal of input signal end IN inputs
The first transistor M1 conductings are controlled, so as to which the first voltage signal of first voltage signal end VGH inputs is transferred into first node
N1。
T1 in the first stage, the first level signal is provided to the first clock signal terminal CK and input signal end IN, to second
Clock signal terminal XCK provides second electrical level signal.At this moment, section point N2 maintains the low potential of last moment, the crystalline substance of control the 7th
Body pipe M7 is turned on, the first output end EOUT output second voltage signals VGL of shifting deposit unit.Meanwhile first output end
EOUT control third transistor M3 conductings, the 3rd node is transferred to by the second clock signal end XCK second electrical level signals inputted
N3, the 3rd node N3 is set to low potential, and by the second electric capacity C2 coupling, section point N2 current potential is further
Reduce, so as to can also turn on the 7th transistor M7 when threshold drift occurs for the 7th transistor M7, by second voltage signal VGL
Totally tansitive is to the first output end EOUT.Now first node N1 and fourth node N4 keeps the high potential of last moment.
In second stage T2, second electrical level signal is provided to the first clock signal terminal CK, to input signal end IN and second
Clock signal terminal XCK provides the first level signal.At this moment, by the first electric capacity C1 coupling by the first clock signal terminal CK
The second electrical level signal of input is transferred to first node N1, first node N1 current potential is kept low potential.First node N1's
Low-potential signal controls the 4th transistor M4 conductings, and the first clock signal terminal CK second electrical level signals inputted are transferred into the 4th
Node N4, fourth node N4 is set to keep low potential, it is so as to control the 6th transistor M6 to turn on, first voltage signal end VGH is defeated
The first voltage signal entered is transferred to the first output end EOUT, the first output end EOUT output first voltage of shifting deposit unit
Signal.The second electrical level signal control second transistor M2 conductings of first clock signal terminal CK inputs, input signal end IN is defeated
The first level signal entered is transferred to section point N2 so that and section point N2 keeps high potential state in second stage T2, from
And the 7th transistor M7 is ended.At this stage, the 3rd node N3 keeps high potential shape under the second electric capacity C2 coupling
State.
In phase III T3, the first level signal is provided to the first clock signal terminal CK, to input signal end IN and second
Clock signal terminal XCK provides second electrical level signal.At this moment, the low level signal that the first transistor M1 inputs in input signal end IN
Control under turn on, the first voltage signal that first voltage signal end inputs is transferred to first node N1, makes first node N1
Keep high potential state.The high level signal control third transistor that first output end EOUT is exported at the end of second stage T2
M3 ends, and the 3rd node N3 current potential is not influenceed by second clock signal end XCK level signal change, maintains high potential shape
State, section point N2 current potential also maintain high potential state on last stage in the presence of the second electric capacity C2.Now, the 5th is brilliant
Body pipe M5 ends under section point N2 high potential control, and fourth node N4 maintains single order in the presence of the 3rd electric capacity C3
The low-potential state of section, control the 6th transistor M6 conductings, the first voltage signal that first voltage signal end inputs is transferred to
First voltage signal described in first output end EOUT, the first output end EOUT output of shifting deposit unit.
In fourth stage T4, second electrical level signal is provided to the first clock signal terminal CK and input signal end IN, to second
Clock signal terminal XCK provides the first level signal.The second electrical level letter that second transistor M2 inputs in the first clock signal terminal CK
Number control under turn on, by input signal end IN input second electrical level signal be transferred to section point N2 so that section point
N2 is changed into low-potential state.The first transistor M1 is turned under the control of the input signal end IN second electrical level signals inputted,
The first voltage signal that first voltage signal end inputs is transferred to first node N1, first node N1 is maintained high potential shape
State.5th transistor M5 is turned under the control of section point N2 low potential, by the first of first voltage signal end VGH inputs
Voltage signal is transferred to fourth node N4, so as to control the 6th transistor M6 to end.7th transistor M7 is section point N2's
Turned under the control of low potential, the second voltage signal that second voltage signal end inputs is transferred to the first of shifting deposit unit
Output end EOUT, the first output end EOUT output second voltage signal, control third transistor M3 conductings, by second clock signal
First level signal of end XCK inputs is transferred to the 3rd node N3 so that the 3rd node N3 keeps high potential state.
In the 5th stage T5, the first level signal is provided to the first clock signal terminal CK, to input signal end IN and second
Clock signal terminal XCK provides second electrical level signal.At this moment, section point N2 maintains low potential on last stage, the crystalline substance of control the 7th
Body pipe M7 is turned on, the first output end EOUT output second voltage signals.Meanwhile the first output end EOUT controls third transistor M3
Conducting, the second clock signal end XCK second electrical level signals inputted are transferred to the 3rd node N3, the 3rd node N3 are set to low
Current potential, and by the second electric capacity C2 coupling, section point N2 current potential is further reduced, so as in the 7th transistor
M7 occurs also turn on the 7th transistor M7 during threshold drift, by second voltage signal VGL totally tansitives to the first output end
EOUT.Now first node N1 and fourth node N4 keeps high potential state on last stage.
In above-mentioned working timing figure, because the signal of output is fed back to the 3rd node N3 by shifting deposit unit,
One stage and the 5th stage are stable in low-potential state by section point N2 so that the signal of shifting deposit unit output will not be sent out
Raw distortion.Also, at the time of upset due to the signal of the first output end EOUT inputs in shifting deposit unit, section point N2
It is unaffected with fourth node M4 current potential, therefore cause the abnormal problem of output signal in the absence of node potential competition, increase
The strong stability of circuit.
Further, if the structure of shifting deposit unit is circuit structure as shown in Figure 5.Its driving method and above-mentioned knot
The driving method for closing Fig. 8 descriptions is consistent.Compared with the driving method of the shifting deposit unit shown in Fig. 3, the displacement shown in Fig. 5 is posted
In the driving method of memory cell, in second stage T2 and phase III T3, low potential controls of the 8th transistor M8 in fourth node
System is lower to be turned on, and the first voltage signal end VGH first voltage signals inputted are transferred into the 3rd node N3, avoid the 3rd node N3
Section point N2 current potential is maintained into high potential state in suspended state, while by the second electric capacity C2 coupling.
So that the first output end EOUT both ends compete in the absence of node potential, ensure circuit stability output.
With further reference to Fig. 9, it illustrates the circuit structure in embodiment illustrated in fig. 6 a working timing figure.Fig. 6 institutes
Show in embodiment, shifting deposit unit adds the second output end SOUT, the 9th transistor M9, the tenth transistor M10, the 11st
Transistor M11 and the 4th electric capacity C4.Unlike Fig. 8, timing diagram shown in Fig. 9 adds the second output end SOUT sequential letter
Number schematic diagram.
T1 in the first stage, the 9th transistor M9 are turned under section point N2 low potential control, and first voltage is believed
Number end VGH input first voltage signal be transferred to the second output end SOUT.Height electricity of the tenth transistor M10 in fourth node N4
Position control is lower to be ended, and the second output end SOUT output high level signals, the 11st transistor M11 exports in the second output end SOUT
High level signal control lower end.
End in second stage T2, the 9th transistor M9 under section point N2 high potential control, the tenth transistor M10
Turned under fourth node N4 low potential control, the second clock signal end XCK high level signals inputted are transferred to second
Output end SOUT, the second output end SOUT output high level signal, the 11st transistor M11 export in the second output end SOUT
High level signal control is lower to be ended.
End in phase III T3, the 9th transistor M9 under section point N2 high potential control, the tenth transistor M10
Turned under fourth node N4 low potential control, the second clock signal end XCK low level signals inputted are transferred to second
Output end SOUT, the second output end SOUT output low level signal.11st transistor M11 exports in the second output end SOUT
Low level signal control is lower to be turned on, and the first voltage signal end VGH first voltage signals inputted are transferred into section point N2, protected
Demonstrate,prove section point interior maintenance high potential state at this stage.
Turned under section point N2 low potential control in fourth stage T4, the 9th transistor M9, first voltage is believed
Number end VGH input first voltage signal be transferred to the second output end SOUT.Height electricity of the tenth transistor M10 in fourth node N4
Position control is lower to be ended, and the second output end SOUT output high level signals, the 11st transistor M11 exports in the second output end SOUT
High level signal control lower end.
Turned under section point N2 low potential control in the 5th stage T5, the 9th transistor M9, first voltage is believed
Number end VGH input first voltage signal be transferred to the second output end SOUT.Height electricity of the tenth transistor M10 in fourth node N4
Position control is lower to be ended, and the second output end SOUT output high level signals, the 11st transistor M11 exports in the second output end SOUT
High level signal control lower end.
From fig. 9, it can be seen that the letter that the second output end SOUT of shifting deposit unit can input input signal end IN
Number displacement and it is anti-phase after export.First output end EOUT can be connected with the input signal end of next stage shifting deposit unit, be made
For the input signal of next stage shifting deposit unit.Second output end SOUT can be connected with the scan line on display panel, the
Two output end SOUT output signal can turn on a line grid line as scanning signal corresponding to thin film transistor (TFT), pass through data wire
Charged to the row sub-pixel.
The embodiment of the present application additionally provides another driving method for being applied to above-mentioned shift register.It refer to Figure 10,
It illustrates another working timing figure of the circuit structure in embodiment illustrated in fig. 3.Unlike embodiment illustrated in fig. 8,
The letter that input signal end IN is inputted in signal timing diagram shown in Fig. 8 that input signal end IN is inputted in timing diagram shown in Figure 10
Number inversion signal.
As shown in Figure 10, a moment before T1, the first clock signal terminal CK input second electrical levels are believed in the first stage
Number, control second transistor M2 conducting, IN the first level signals inputted in input signal end are transferred to section point N2, by the
Two node N2 current potential is set to high potential.Couplings of the first node N1 in the first electric capacity C1 is maintaining low-potential state,
Control the 4th transistor M4 to turn on, the first clock signal terminal CK the second electric potential signals inputted are transferred to fourth node N4, made
Fourth node N4 keeps low-potential state.
T1 in the first stage, first level signal is provided to the first clock signal terminal CK, to second clock signal
XCK, input signal end IN provide the second electrical level signal.The second electrical level that the first transistor M1 inputs in input signal end IN
Turned under the control of signal, the first voltage signal end VGH first voltage signals inputted are transferred to first node N1, make first
Node N1 keeps high potential state.Second transistor M2 is under the control of the first clock signal terminal CK the first level signals inputted
Cut-off, section point N2 keep the high potential state of last moment, control the 7th transistor M7 cut-offs；In fourth node N4 holdings
The low-potential state at one moment, control the 6th transistor M6 conductings, the first voltage signal end VGH signals inputted are transferred to the
One output end EOUT.At this moment, the first output end EOUT exports first voltage signal.
In second stage T2, second electrical level signal is provided to the first clock signal terminal CK, input signal end IN, during to second
Clock signal end XCK provides the first level signal.Controls of the first transistor M1 in the input signal end IN second electrical level signals inputted
System is lower to be turned on, and the first voltage signal end VGH first voltage signals inputted are transferred into first node N1, make first node N1's
Current potential keeps high potential state.Second transistor M2 is led under the control of the first clock signal terminal CK second electrical level signals inputted
It is logical, IN the second electric potential signals inputted in input signal end are transferred to section point N2, section point N2 is converted to low potential
State, and then the 7th transistor M7 is turned on, the second voltage signal end VGL second voltage signals inputted are transferred to the first output
Hold EOUT.First output end EOUT exports second voltage signal, control third transistor M3 conductings, by second clock signal end
First level signal of XCK inputs is transferred to the 3rd node N3, the 3rd node N3 is kept high potential state, at this moment due to second
Transistor M2 is remained under the control of the first clock signal terminal CK second electrical level signal, input signal end IN inputs
Second electrical level signal, so section point N2 maintains low-potential state, the potential difference between section point N2 and the 3rd node N3
Kept by the second electric capacity C2.5th transistor M5 is turned under the low potential control of section point, by first voltage signal end VGH
The first voltage signal of input is transferred to fourth node N4, fourth node N4 is kept high potential state.
In phase III T3, the first level signal is provided to the first clock signal terminal CK, input signal end IN, during to second
Clock signal end XCK provides second electrical level signal.First electric capacity C1 one end inputs the first level signal, and first node N1 is first
High potential state is maintained under electric capacity C1 coupling.Section point N2 keeps low-potential state on last stage, conducting the 7th
Transistor M7, the second voltage signal end VGL second voltage signals inputted are transferred to the first output end EOUT.First output end
EOUT exports second voltage signal, the M3 conductings of control third transistor, the second electrical level of second clock signal end XCK inputs is believed
Number the 3rd node N3 is transferred to, the 3rd node N3 is kept low-potential state.Under the second electric capacity C2 coupling, the second section
Point N2 low potential is further dragged down, and the 5th transistor M5 is turned under section point N2 low potential control, by first voltage
The first voltage signal of signal end VGH inputs is transferred to fourth node N4, fourth node N4 is kept high potential state, so as to control
Make the 6th transistor M6 cut-offs.
In fourth stage T4, second electrical level signal is provided to the first clock signal terminal CK, to second clock signal end XCK,
Input signal end IN provides the first level signal.The second electrical level signal that second transistor M2 inputs in the first clock signal terminal CK
Control is lower to be turned on, and IN the first level signals inputted in input signal end are transferred into section point N2, keep section point N2
High potential state.The first transistor M1 ends under the control of input signal end IN the first level signals inputted, first node
N1 is converted to low-potential state under the first electric capacity C1 coupling, and so as to turn on the 4th transistor M4, the first clock is believed
Number end CK input second electrical level signal be transferred to fourth node N4, fourth node N4 is kept low-potential state at this stage,
So as to turn on the 6th transistor M6, the first voltage signal end VGH first voltage signals inputted are transferred to the first output end
EOUT, the first output end EOUT export first voltage signal, and the M3 cut-offs of control third transistor, the 3rd node N3 is in the second electric capacity
High potential state is converted under C2 coupling.
In the 5th stage, the first level signal is provided to the first clock signal terminal CK, input signal end IN, to second clock
Signal end XCK provides the second electrical level signal.The first transistor M1 is in input signal end IN the first level signals inputted
Control is lower to be ended, and second transistor M2 ends under the control of the first clock signal terminal CK the first level signals inputted, and second
Node N2 keeps the high potential state of last moment, control the 7th transistor M7 cut-offs；First node N1 is the first electric capacity C1's
It is changed into high potential state under coupling, therefore, fourth node N4 maintains low-potential state on last stage, the crystalline substance of control the 6th
Body pipe M6 is turned on, and the first voltage signal end VGH signals inputted are transferred into the first output end EOUT.At this moment, the first output end
EOUT exports first voltage signal.
The driving method for the shift register that the embodiment of the present application is provided, no matter the signal of input signal end input is height
Level signal or low level signal, it can realize the displacement of signal.Due to the first output end by shifting deposit unit
EOUT controls the 3rd node N3 electric potential signal, further drags down section point N2 current potential, can compensate for due to transistor
Threshold drift, the output end of guarantee shift signal totally tansitive to shifting deposit unit, so as to increase the process window of circuit,
Improve the stability of circuit.
On the basis of above-described embodiment, the embodiment of the present application additionally provides a kind of display device, using above example
Described shifting deposit unit and the driving method of shifting deposit unit.It is appreciated that display device can also include other
Known structure, such as pel array, multi-strip scanning line, a plurality of data lines intersected with multi-strip scanning line insulation.
Above description is only the preferred embodiment of the application and the explanation to institute's application technology principle.People in the art
Member should be appreciated that invention scope involved in the application, however it is not limited to the technology that the particular combination of above-mentioned technical characteristic forms
Scheme, while should also cover in the case where not departing from the inventive concept, carried out by above-mentioned technical characteristic or its equivalent feature
The other technical schemes for being combined and being formed.Such as features described above has similar work(with (but not limited to) disclosed herein
The technical scheme that the technical characteristic of energy is replaced mutually and formed.
Claims (10)
1. a kind of shifting deposit unit, including the first transistor, second transistor, third transistor, the 4th transistor, the 5th crystalline substance
Body pipe, the 6th transistor, the 7th transistor, the first electric capacity, the second electric capacity, the 3rd electric capacity, input signal end, the first clock signal
End, second clock signal end, first voltage signal end, second voltage signal end and the first output end, wherein,
The signal that the first transistor is inputted by the input signal end controls, for the first voltage signal end to be inputted
Signal be transferred to first node；
The signal that the second transistor is inputted by first clock signal terminal controls, for the input signal end to be inputted
Signal be transferred to section point；
The signal that the third transistor is exported by first output end controls, for the second clock signal end to be inputted
Signal be transferred to the 3rd node；
4th transistor is controlled by the electric potential signal of the first node, for input first clock signal terminal
Signal or the signal of second voltage signal end input are transferred to fourth node；
5th transistor is controlled by the electric potential signal of the section point, for input the first voltage signal end
Signal is transferred to the fourth node；
6th transistor is controlled by the electric potential signal of the fourth node, for input the first voltage signal end
Signal is transferred to first output end；
7th transistor is controlled by the electric potential signal of the section point, for input the second voltage signal end
Signal is transferred to first output end；
One end of first electric capacity is used for the signal for inputting first clock signal terminal input, first electric capacity it is another
Hold the electric potential signal for inputting the first node；
One end of second electric capacity is used for the electric potential signal for inputting the 3rd node, and the other end of second electric capacity is used for
Input the electric potential signal of the section point；
One end of 3rd electric capacity is used for the signal for inputting the first voltage signal end, and the other end of the 3rd electric capacity is used
In the electric potential signal for inputting the fourth node.
2. shifting deposit unit according to claim 1, it is characterised in that the grid of the first transistor with it is described defeated
Enter signal end connection, the first pole of the first transistor is connected with the first voltage signal end, the first transistor
Second pole is connected with the first node；
The grid of the second transistor is connected with first clock signal terminal, the first pole of the second transistor with it is described
Input signal end is connected, and the second pole of the second transistor is connected with the section point；
The grid of the third transistor is connected with the first output end of the shifting deposit unit, and the of the third transistor
One pole is connected with the second clock signal end, and the second pole of the third transistor is connected with the 3rd node；
The grid of 4th transistor is connected with the first node, when the first pole of the 4th transistor is with described first
Clock signal end or second voltage signal end connection, the second pole of the 4th transistor is connected with the fourth node；
The grid of 5th transistor is connected with the section point, the first pole of the 5th transistor and the described first electricity
Signal end connection is pressed, the second pole of the 5th transistor is connected with the fourth node；
The grid of 6th transistor is connected with the fourth node, the first pole of the 6th transistor and the described first electricity
Signal end connection is pressed, the second pole of the 6th transistor is connected with first output end；
The grid of 7th transistor is connected with the section point, the first pole of the 7th transistor and the described second electricity
Signal end connection is pressed, the second pole of the 7th transistor is connected with first output end；
One end of first electric capacity is connected with first clock signal terminal, the other end of first electric capacity and described first
Node connects；
One end of second electric capacity is connected with the 3rd node, and the other end and the section point of second electric capacity connect
Connect；
One end of 3rd electric capacity is connected with the first voltage signal end, the other end and the described 4th of the 3rd electric capacity
Node connects.
3. shifting deposit unit according to claim 1, it is characterised in that it is brilliant that the shifting deposit unit also includes the 8th
Body pipe, the 8th transistor are controlled by the electric potential signal of the fourth node, the letter that the first voltage signal end is inputted
Number it is transferred to the 3rd node.
4. shifting deposit unit according to claim 3, the grid of the 8th transistor is connected with the fourth node,
First pole of the 8th transistor is connected with the first voltage signal end, the second pole of the 8th transistor and described the
Three nodes connect.
5. shifting deposit unit according to claim 1, it is characterised in that the shifting deposit unit also includes：
Second output end；
9th transistor, controlled by the electric potential signal of the section point, for the letter for inputting the first voltage signal end
Number it is transferred to second output end；
Tenth transistor, controlled by the electric potential signal of the fourth node, for the letter for inputting the second clock signal end
Number it is transferred to second output end；
11st transistor, controlled by the signal of second output end output, for the first voltage signal end to be inputted
Signal be transferred to the section point；
4th electric capacity, one end of the 4th electric capacity are used for the electric potential signal for inputting the fourth node, the 4th electric capacity
The other end is used for the signal for inputting the second output end output.
6. shifting deposit unit according to claim 5, it is characterised in that the grid of the 9th transistor and described the
Two nodes connect, and the first pole of the 9th transistor is connected with the first voltage signal end, and the of the 9th transistor
Two poles are connected with second output end；
The grid of tenth transistor is connected with the fourth node, when the first pole of the tenth transistor is with described second
Clock signal end is connected, and the second pole of the tenth transistor is connected with second output end；
The grid of 11st transistor is connected with second output end, the first pole of the 11st transistor with it is described
First voltage signal end is connected, and the second pole of the 11st transistor is connected with the section point；
One end of 4th electric capacity is connected with the fourth node, the other end and second output end of the 4th electric capacity
Connection.
7. a kind of shift register, include the shifting deposit unit as described in claim any one of 1-6 of N number of cascade.
8. a kind of method for driving the shifting deposit unit as described in claim any one of 1-6, including：
First stage, the first level signal is provided to first clock signal terminal and the input signal end, to described second
Clock signal terminal provides second electrical level signal, and first output end exports second voltage signal；
Second stage, the second electrical level signal is provided to first clock signal terminal, to the input signal end and described
Second clock signal end provides first level signal, and first output end exports first voltage signal；
Phase III, first level signal is provided to first clock signal terminal, to the input signal end and described
Second clock signal end provides the second electrical level signal, and first output end exports the first voltage signal；
Fourth stage, the second electrical level signal is provided to first clock signal terminal and input signal end, to described second
Clock signal terminal provides first level signal, and first output end exports the second voltage signal；
In 5th stage, first level signal is provided to first clock signal terminal, to the input signal end and described
Second clock signal end provides the second electrical level signal, and first output end exports the second voltage signal.
9. a kind of method for driving the shifting deposit unit as described in claim any one of 1-6, including：
In the first stage, provide first level signal to first clock signal terminal, to the second clock signal end,
The input signal end provides the second electrical level signal, and first output end exports the first voltage signal；
In second stage, the second electrical level signal is provided to first clock signal terminal, the input signal end, to described
Second clock signal end provides first level signal, and first output end exports the second voltage signal；
In the phase III, first level signal is provided to first clock signal terminal, the input signal end, to described
Second clock signal end provides the second electrical level signal, and first output end exports the second voltage signal；
In fourth stage, the second electrical level signal is provided to first clock signal terminal, to the second clock signal end,
The input signal end provides first level signal, and first output end exports the first voltage signal；
In the 5th stage, first level signal is provided to first clock signal terminal, input signal end, to described second
Clock signal terminal provides the second electrical level signal, and first output end exports the first voltage signal.
A kind of 10. display device, using the shifting deposit unit as described in claim any one of 1-6 and the institute of claim 8 or 9
The driving method stated.
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| CN201510993310.2A CN105405383B (en) | 2015-12-25 | 2015-12-25 | Shifting deposit unit, shift register and its driving method, display device |
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| KR102476721B1 (en) * | 2016-06-30 | 2022-12-15 | 삼성디스플레이 주식회사 | Stage and Organic Light Emitting Display Device Using The Same |
| CN106067325A (en) * | 2016-07-11 | 2016-11-02 | 信利（惠州）智能显示有限公司 | A kind of shift register and gate driver circuit |
| CN106328055B (en) * | 2016-10-25 | 2018-08-14 | 广东聚华印刷显示技术有限公司 | A kind of phase inverter, display driver circuit and display panel |
| CN106486065B (en) * | 2016-12-29 | 2019-03-12 | 上海天马有机发光显示技术有限公司 | Shifting deposit unit, register, organic light emitting display panel and driving method |
| CN106782406B (en) * | 2017-02-08 | 2019-04-09 | 京东方科技集团股份有限公司 | Shift-register circuit and its driving method, gate driving circuit, display panel |
| CN107945732B (en) * | 2017-03-21 | 2020-04-03 | 北京大学深圳研究生院 | Gate drive circuit |
| CN106847159B (en) * | 2017-03-30 | 2019-11-19 | 上海天马有机发光显示技术有限公司 | A kind of shift register, gate driving circuit and display panel |
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| CN109147635B (en) * | 2017-06-27 | 2021-04-16 | 上海天马有机发光显示技术有限公司 | Shift register, driving method thereof and display device |
| CN107316599B (en) | 2017-07-07 | 2020-09-22 | 上海天马有机发光显示技术有限公司 | Shift register unit, driving method thereof and display panel |
| KR102523066B1 (en) * | 2017-11-21 | 2023-04-17 | 엘지디스플레이 주식회사 | Gate driver and electroluminescence display device including the same |
| CN109949758B (en) * | 2017-12-21 | 2022-01-04 | 咸阳彩虹光电科技有限公司 | Scanning signal compensation method and device based on grid drive circuit |
| CN108831385B (en) * | 2018-06-25 | 2020-04-28 | 上海天马有机发光显示技术有限公司 | Scanning driving circuit, display device and driving method |
| CN109147646B (en) * | 2018-10-31 | 2021-05-11 | 武汉天马微电子有限公司 | Shift register and control method thereof, display panel and display device |
| CN110322824A (en) * | 2019-05-21 | 2019-10-11 | 合肥维信诺科技有限公司 | A kind of scan drive circuit and display panel |
| CN110689844B (en) * | 2019-09-26 | 2021-03-12 | 昆山工研院新型平板显示技术中心有限公司 | Shift register and display panel |
| CN112802424A (en) * | 2021-02-26 | 2021-05-14 | 合肥维信诺科技有限公司 | Shift register, display panel and display device |
| CN112951163B (en) * | 2021-03-25 | 2023-04-28 | 厦门天马微电子有限公司 | Shift register and driving method, grid line driving circuit, display panel and device |
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