CN105404346A - Voltage regulating circuit, high-voltage generation circuit, and storage circuit - Google Patents
Voltage regulating circuit, high-voltage generation circuit, and storage circuit Download PDFInfo
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- CN105404346A CN105404346A CN201510971817.8A CN201510971817A CN105404346A CN 105404346 A CN105404346 A CN 105404346A CN 201510971817 A CN201510971817 A CN 201510971817A CN 105404346 A CN105404346 A CN 105404346A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
Provided are a voltage regulating circuit, a high-voltage generation circuit, and a storage circuit. The voltage regulating circuit comprises a first ZMOS tube, a voltage division circuit, a first NMOS tube, and a comparator. The grid electrode of the first ZMOS tube is connected with the drain electrode of the first ZMOS tube. The source electrode of the first ZMOS tube is connected with the input end of the voltage division circuit. The drain electrode of the first NMOS tube is connected with the first output end of the voltage division circuit. The source electrode of the first NMOS tube is connected with ground. The first input end of the comparator is connected with the second output end of the voltage division circuit. The second input end of the comparator is suitable to receive reference voltage.
Description
Technical field
The present invention relates to electronic applications, particularly relate to a kind of Voltage Cortrol, high pressure produces and memory circuitry.
Background technology
As shown in Figure 1, existing circuit for producing high voltage comprises: voltage-regulating circuit 10, first charge pump 20, second charge pump 30, transmission ZMOS pipe Z0 and voltage stabilizer 40.Described circuit for producing high voltage is suitable for providing high pressure program voltage to storer 50.Threshold voltage-0.1V ~ the 0.5V of described transmission ZMOS pipe Z0.
The power end of the first charge pump 20 receives the first voltage Vdd provided by low pressure difference linear voltage regulator, and the power end of the second charge pump 30 receives the second voltage Vddq that external power source provides.
Described voltage-regulating circuit 10 comprises bleeder circuit 110, comparer 120 and NMOS tube MN10.Comparer 120 outputs enable signal to the Enable Pin Pump_en of the first charge pump 20 according to the voltage Vrdet of the second output terminal of bleeder circuit 110 and the size comparative result of reference voltage Vref, thus regulate the output end voltage Vr of the first charge pump 20, make the first input end voltage Vrdet of comparer 120 equal with reference voltage Vref.Whether the grid of NMOS tube MN10 connects the Enable Pin EN of described voltage-regulating circuit 10, thus receive described voltage-regulating circuit 10 enable signal and carry out control voltage Circuit tuning 10 and work.
When the first input end voltage Vrdet of comparer 120 is equal with reference voltage Vref, the source voltage Vep=K*Vref+Vgsz0 of transmission ZMOS pipe Z0.K is the dividing potential drop coefficient of bleeder circuit 110, and Vref is the magnitude of voltage of reference voltage, and Vgsz0 is the grid of transmission ZMOS pipe and the voltage difference of source electrode.
The grid of transmission ZMOS pipe Z0 and the voltage difference of source electrode each process conditions and temperature lower deviation larger, cause the high pressure program voltage bias voltage under each process conditions and temperature being supplied to storer 50 also larger, this is unfavorable to the Performance And Reliability of storer 50.
Summary of the invention
The problem that the present invention solves is that voltage bias voltage under each process conditions and temperature that existing circuit for producing high voltage provides is larger.
For solving the problem, the invention provides a kind of voltage-regulating circuit, comprising: a ZMOS pipe, bleeder circuit, the first NMOS tube and comparer; The grid of a described ZMOS pipe connects the drain electrode of a described ZMOS pipe, and the source electrode of a described ZMOS pipe connects the input end of described bleeder circuit; The drain electrode of described first NMOS tube connects the first output terminal of described bleeder circuit, the source ground of described first NMOS tube; The first input end of described comparer connects the second output terminal of described bleeder circuit, and the second input end of described comparer is suitable for receiving reference voltage.
Optionally, described reference voltage is 0.7V ~ 1V.
Optionally, described bleeder circuit comprises: M the first PMOS, M >=2; The source electrode of the 1st the first PMOS connects the input end of described bleeder circuit; The source electrode of m the first PMOS connects the grid of m-1 the first PMOS and the drain electrode of m-1 the first PMOS, M >=m >=2; The drain electrode of M the first PMOS connects the first output terminal of described bleeder circuit; The source electrode of first PMOS in described M the first PMOS connects the second output terminal of described bleeder circuit.
Optionally, described voltage-regulating circuit also comprises: at least one compensating unit; First link of described compensating unit connects the drain electrode of a described ZMOS pipe, and the second link of described compensating unit connects the source electrode of a described ZMOS pipe; Described compensating unit comprises: the 2nd ZMOS pipe and the second PMOS; The drain electrode of described 2nd ZMOS pipe connects the described grid of the 2nd ZMOS pipe and the first link of described compensating unit, and the source electrode of described 2nd ZMOS pipe connects the source electrode of described second PMOS; The drain electrode of described second PMOS connects the second link of described compensating unit.
The present invention also provides a kind of circuit for producing high voltage, comprising: the first charge pump, the second charge pump, the 3rd ZMOS pipe and above-mentioned voltage-regulating circuit; The input end of described first charge pump connects the drain electrode of described second electric charge delivery side of pump and described 3rd ZMOS pipe, described first electric charge delivery side of pump connects the drain electrode of a ZMOS pipe in the grid of described 3rd ZMOS pipe and described voltage-regulating circuit, and the Enable Pin of described first charge pump connects the output terminal of comparer in described voltage-regulating circuit.
Optionally, a described ZMOS pipe and the 3rd ZMOS pipe are N-type, and a described ZMOS pipe is identical with the channel length of the 3rd ZMOS pipe, and a described ZMOS pipe is identical with the channel width of the 3rd ZMOS pipe.
Optionally, circuit for producing high voltage also comprises: at least one compensating unit; First link of described compensating unit connects the drain electrode of a described ZMOS pipe, and the second link of described compensating unit connects the source electrode of a described ZMOS pipe; Described compensating unit comprises: the 2nd ZMOS pipe and the second PMOS; The drain electrode of described 2nd ZMOS pipe connects the described grid of the 2nd ZMOS pipe and the first link of described compensating unit, and the source electrode of described 2nd ZMOS pipe connects the source electrode of described second PMOS; The drain electrode of described second PMOS connects the second link of described compensating unit.
Optionally, a described ZMOS pipe and the 2nd ZMOS pipe are N-type, and a described ZMOS pipe is identical with the channel length of the 2nd ZMOS pipe, and a described ZMOS pipe is identical with the channel width of the 2nd ZMOS pipe.
Optionally, described circuit for producing high voltage also comprises: control circuit; The source electrode of described 3rd ZMOS pipe is suitable for connected storage; Described control circuit is suitable for the second PMOS controlled in N number of compensating unit and is in off state, and described N equals the figure place needing in described storer to programme, N >=1.
The present invention also provides a kind of memory circuitry, it is characterized in that, comprises above-mentioned circuit for producing high voltage and storer, the source electrode connected storage of described 3rd ZMOS pipe.
Compared with prior art, the voltage-regulating circuit of technical scheme of the present invention adds a ZMOS pipe, concerning the source voltage of the 3rd ZMOS pipe, process conditions and the impact of temperature on the grid of the 3rd ZMOS pipe and the voltage difference of source electrode can be weakened by a ZMOS pipe.This makes the circuit for producing high voltage be made up of voltage-regulating circuit of the present invention can be provided in the less high pressure program voltage of bias voltage at each process conditions and temperature, thus improves the Performance And Reliability of storer.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing circuit for producing high voltage;
Fig. 2 is memory circuitry one structural representation of the embodiment of the present invention;
Fig. 3 is another structural representation of memory circuitry of the embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
As shown in Figure 2, the embodiment of the present invention provides a kind of voltage-regulating circuit 1, comprising: a ZMOS pipe Z1, bleeder circuit 11, first NMOS tube MN1 and comparer 12.
The grid of a described ZMOS pipe Z1 connects the drain electrode of a described ZMOS pipe Z1, and the source electrode of a described ZMOS pipe Z1 connects the input end of described bleeder circuit 11.The drain electrode of described first NMOS tube MN1 connects the first output terminal of described bleeder circuit 11, the source ground of described first NMOS tube MN1.The first input end of described comparer 12 connects the second output terminal of described bleeder circuit 11, and the second input end of described comparer 12 is suitable for receiving reference voltage Vref.
The grid of described first NMOS tube MN1 can connect the Enable Pin EN of described voltage-regulating circuit 1, for receiving the enable signal whether control voltage Circuit tuning 1 works.
The circuit for producing high voltage adopting Circuit tuning 1 to be formed comprises: voltage-regulating circuit 1, first charge pump 2, second charge pump 3, the 3rd ZMOS pipe Z3.
The input end of described first charge pump 2 connects the output terminal of described second charge pump 3 and the drain electrode of described 3rd ZMOS pipe Z3, the output terminal of described first charge pump 2 connects the drain electrode of a ZMOS pipe Z1 in the grid of described 3rd ZMOS pipe Z3 and described voltage-regulating circuit 1, and the Enable Pin Pump_en of described first charge pump 2 connects the output terminal of comparer 12 in described voltage-regulating circuit 1.
Comparer 12 outputs enable signal to the Enable Pin Pump_en of the first charge pump 2 according to the voltage Vrdet of the second output terminal of bleeder circuit 11 and the size comparative result of reference voltage Vref, thus regulate the output end voltage Vr of the first charge pump 2, make the first input end voltage Vrdet of comparer 12 equal with reference voltage Vref.Described reference voltage Vref is 0.7V ~ 1V.
When the first input end voltage Vrdet of comparer 12 is equal with reference voltage Vref, namely the second output end voltage of bleeder circuit 11 is equal with reference voltage Vref, then
Source voltage Vep=K*Vref+ (Vgsz1-Vgsz3) formula 1 of the 3rd ZMOS pipe
In equation 1, K is the dividing potential drop coefficient of bleeder circuit 11, and Vref is the magnitude of voltage of reference voltage, and Vgsz1 is the grid of a ZMOS pipe and the voltage difference of source electrode, and Vgsz3 is the grid of the 3rd ZMOS pipe and the voltage difference of source electrode.
As can be seen from formula 1, concerning the source voltage Vep of the 3rd ZMOS pipe Z3, process conditions and the impact of temperature on the grid of the 3rd ZMOS pipe Z3 and the voltage difference of source electrode can be weakened by a ZMOS pipe.
When a described ZMOS pipe Z1 is identical with the 3rd ZMOS pipe Z3 type and critical size is identical, the grid of a ZMOS pipe Z1 and the 3rd ZMOS pipe Z3 and the voltage difference approximately equal of source electrode, (Vgsz1-Vgsz3) namely in formula 1 is approximately 0.This makes process conditions and the impact of temperature on the grid of the 3rd ZMOS pipe Z3 pipe and the voltage difference of source electrode substantially can be offset by a ZMOS pipe Z1.
Concrete, the threshold voltage of a described ZMOS pipe Z1 and the 3rd ZMOS pipe Z3 is very low, is-0.1V ~ 0.5V.A described ZMOS pipe Z1 and the 3rd ZMOS pipe Z3 can be N-type, the critical size of a described ZMOS pipe Z1 and the 3rd ZMOS pipe Z3 comprises channel length and channel width, a described ZMOS pipe Z1 is identical with the channel length of the 3rd ZMOS pipe Z3, and a described ZMOS pipe Z1 is identical with the channel width of the 3rd ZMOS pipe Z3.A described ZMOS pipe Z1 and the 3rd ZMOS pipe Z3 can manufacture under same process condition and temperature.
Continue with reference to figure 2, described bleeder circuit comprises: M the first PMOS, M >=2.
The source electrode of the 1st the first PMOS MP11 connects the input end of described bleeder circuit 11.The source electrode of m the first PMOS connects the grid of m-1 the first PMOS and the drain electrode of m-1 the first PMOS, M >=m >=2.The drain electrode of M the first PMOS MP1M connects the first output terminal of described bleeder circuit 11.The source electrode of first PMOS in described M the first PMOS connects the second output terminal of described bleeder circuit.
Optionally, the source electrode of described M the first PMOS connects the second output terminal of described bleeder circuit, in this situation, and the source voltage Vep=M*Vref+ (Vgsz1-Vgsz3) of the 3rd ZMOS pipe.
Described circuit for producing high voltage can also comprise: the voltage stabilizer 4 connecting described second charge pump 3.The power end of described first charge pump 2 is suitable for reception first voltage Vdd, and described first voltage Vdd can be provided by low pressure difference linear voltage regulator, and described first voltage Vdd can be 1.5V.The power end of described second charge pump 3 is suitable for reception second voltage Vddq, and described second voltage Vddq can be provided by external power source, and described second voltage Vddq can be 1.8V ~ 5.5V.Described first charge pump 2, second charge pump 3 and voltage stabilizer 4 structure can adopt prior art to realize, and repeat no more herein.
As shown in Figure 3, described voltage-regulating circuit 1 can also comprise: at least one compensating unit 13.
First link of described compensating unit 13 connects the drain electrode of a described ZMOS pipe Z1, and the second link of described compensating unit 13 connects the source electrode of a described ZMOS pipe Z1.
Described compensating unit 13 comprises: the 2nd ZMOS pipe Z2 and the second PMOS MP2.The drain electrode of described 2nd ZMOS pipe Z2 connects the described grid of the 2nd ZMOS pipe Z2 and the first link of described compensating unit 13, and the source electrode of described 2nd ZMOS pipe Z2 connects the source electrode of described second PMOS MP2.The drain electrode of described second PMOS MP2 connects the second link of described compensating unit 13.
The threshold voltage of described 2nd ZMOS pipe Z2 is-0.1V ~ 0.5V.Described 2nd ZMOS pipe Z2 can be N-type, identical with the channel length of the 3rd ZMOS pipe Z3 with a described ZMOS pipe Z1, also identical with the channel width of the 3rd ZMOS pipe Z3 with a described ZMOS pipe Z1.A described ZMOS pipe Z1, the 2nd ZMOS pipe Z2 can manufacture with the 3rd ZMOS pipe Z3 under identical process conditions and temperature.
Described circuit for producing high voltage may be used for the high pressure program voltage providing storer 5, and namely the source voltage Vep of the 3rd ZMOS pipe Z3 is as the high pressure program voltage of storer 5.When the figure place of programming required in storer 5 increases, programmed load increases, and high pressure program voltage also needs to increase, and the compensating unit 13 of the present embodiment can meet these needs.
Concrete, when in compensating unit 13, the second PMOS MP2 turns off, compensating unit 13 can increase the grid of a ZMOS pipe and the voltage difference Vgsz1 of source electrode, from formula 1, the source voltage Vep of the 3rd ZMOS pipe can raise, thus the demand that the figure place that can meet required programming in storer 5 increases.
Described circuit for producing high voltage can also comprise: control circuit.
The source electrode of described 3rd ZMOS pipe is suitable for connected storage, and described control circuit is suitable for the second PMOS controlled in N number of compensating unit and is in off state.Described N equals the figure place needing in described storer to programme, N >=1.Such as, storer needs the figure place of programming to be 8, then the second PMOS that control circuit controls in 8 compensating units is in off state.
When the figure place that control circuit selects the second PMOS quantity of shutoff and storer to need to programme is identical, the high pressure program voltage that circuit for producing high voltage provides can remain unchanged substantially, thus improves the accuracy of memory program.
Described control circuit can comprise: selector switch and level translator, and the output terminal of described selector switch connects described level translator, and the output terminal of described level translator connects the grid of described second PMOS.
Be understandable that, the output terminal quantity of level translator is greater than or equals the quantity of described second PMOS, thus realizes connecting one to one.
The embodiment of the present invention also provides a kind of memory circuitry, comprises circuit for producing high voltage and the storer of above-described embodiment.The source electrode connected storage of the 3rd ZMOS pipe in described circuit for producing high voltage, provides the program voltage of the high pressure needed for storer.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a voltage-regulating circuit, is characterized in that, comprising: a ZMOS pipe, bleeder circuit, the first NMOS tube and comparer;
The grid of a described ZMOS pipe connects the drain electrode of a described ZMOS pipe, and the source electrode of a described ZMOS pipe connects the input end of described bleeder circuit;
The drain electrode of described first NMOS tube connects the first output terminal of described bleeder circuit, the source ground of described first NMOS tube;
The first input end of described comparer connects the second output terminal of described bleeder circuit, and the second input end of described comparer is suitable for receiving reference voltage.
2. voltage-regulating circuit as claimed in claim 1, it is characterized in that, described reference voltage is 0.7V ~ 1V.
3. voltage-regulating circuit as claimed in claim 1, it is characterized in that, described bleeder circuit comprises: M the first PMOS, M >=2;
The source electrode of the 1st the first PMOS connects the input end of described bleeder circuit;
The source electrode of m the first PMOS connects the grid of m-1 the first PMOS and the drain electrode of m-1 the first PMOS, M >=m >=2;
The drain electrode of M the first PMOS connects the first output terminal of described bleeder circuit;
The source electrode of first PMOS in described M the first PMOS connects the second output terminal of described bleeder circuit.
4. voltage-regulating circuit as claimed in claim 1, is characterized in that, also comprise: at least one compensating unit;
First link of described compensating unit connects the drain electrode of a described ZMOS pipe, and the second link of described compensating unit connects the source electrode of a described ZMOS pipe;
Described compensating unit comprises: the 2nd ZMOS pipe and the second PMOS;
The drain electrode of described 2nd ZMOS pipe connects the described grid of the 2nd ZMOS pipe and the first link of described compensating unit, and the source electrode of described 2nd ZMOS pipe connects the source electrode of described second PMOS;
The drain electrode of described second PMOS connects the second link of described compensating unit.
5. a circuit for producing high voltage, is characterized in that, comprising: the first charge pump, the second charge pump, the 3rd ZMOS pipe and the voltage-regulating circuit described in the arbitrary claim of claims 1 to 3;
The input end of described first charge pump connects the drain electrode of described second electric charge delivery side of pump and described 3rd ZMOS pipe, described first electric charge delivery side of pump connects the drain electrode of a ZMOS pipe in the grid of described 3rd ZMOS pipe and described voltage-regulating circuit, and the Enable Pin of described first charge pump connects the output terminal of comparer in described voltage-regulating circuit.
6. circuit for producing high voltage as claimed in claim 5, it is characterized in that, a described ZMOS pipe and the 3rd ZMOS pipe are N-type, and a described ZMOS pipe is identical with the channel length of the 3rd ZMOS pipe, and a described ZMOS pipe is identical with the channel width of the 3rd ZMOS pipe.
7. circuit for producing high voltage as claimed in claim 5, is characterized in that, comprising: at least one compensating unit;
First link of described compensating unit connects the drain electrode of a described ZMOS pipe, and the second link of described compensating unit connects the source electrode of a described ZMOS pipe;
Described compensating unit comprises: the 2nd ZMOS pipe and the second PMOS;
The drain electrode of described 2nd ZMOS pipe connects the described grid of the 2nd ZMOS pipe and the first link of described compensating unit, and the source electrode of described 2nd ZMOS pipe connects the source electrode of described second PMOS;
The drain electrode of described second PMOS connects the second link of described compensating unit.
8. circuit for producing high voltage as claimed in claim 7, it is characterized in that, a described ZMOS pipe and the 2nd ZMOS pipe are N-type, and a described ZMOS pipe is identical with the channel length of the 2nd ZMOS pipe, and a described ZMOS pipe is identical with the channel width of the 2nd ZMOS pipe.
9. circuit for producing high voltage as claimed in claim 7, is characterized in that, also comprise: control circuit;
The source electrode of described 3rd ZMOS pipe is suitable for connected storage;
Described control circuit is suitable for the second PMOS controlled in N number of compensating unit and is in off state, and described N equals the figure place needing in described storer to programme, N >=1.
10. a memory circuitry, is characterized in that, comprises the circuit for producing high voltage described in the arbitrary claim of claim 5 to 9 and storer, the source electrode connected storage of described 3rd ZMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510971817.8A CN105404346B (en) | 2015-12-22 | 2015-12-22 | Voltage adjustment, high pressure are produced and memory circuitry |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510971817.8A CN105404346B (en) | 2015-12-22 | 2015-12-22 | Voltage adjustment, high pressure are produced and memory circuitry |
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| CN105404346A true CN105404346A (en) | 2016-03-16 |
| CN105404346B CN105404346B (en) | 2017-08-08 |
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| CN201510971817.8A Active CN105404346B (en) | 2015-12-22 | 2015-12-22 | Voltage adjustment, high pressure are produced and memory circuitry |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5029282A (en) * | 1989-02-16 | 1991-07-02 | Kabushiki Kaisha Toshiba | Voltage regulator circuit |
| CN1226334A (en) * | 1996-06-07 | 1999-08-18 | 内部技术公司 | Electrically erasable and programmable no-volatile memory protected against power failure |
| US20070076476A1 (en) * | 2004-11-26 | 2007-04-05 | Massimiliano Frulio | Method and system for regulating a program voltage value during multilevel memory device programming |
| CN101620449A (en) * | 2008-06-30 | 2010-01-06 | 力晶半导体股份有限公司 | Voltage stabilizing device and flash memory |
| CN104714584A (en) * | 2013-12-13 | 2015-06-17 | 芯视达系统公司 | Voltage regulator with multiple output ranges and control method thereof |
-
2015
- 2015-12-22 CN CN201510971817.8A patent/CN105404346B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5029282A (en) * | 1989-02-16 | 1991-07-02 | Kabushiki Kaisha Toshiba | Voltage regulator circuit |
| CN1226334A (en) * | 1996-06-07 | 1999-08-18 | 内部技术公司 | Electrically erasable and programmable no-volatile memory protected against power failure |
| US20070076476A1 (en) * | 2004-11-26 | 2007-04-05 | Massimiliano Frulio | Method and system for regulating a program voltage value during multilevel memory device programming |
| CN101620449A (en) * | 2008-06-30 | 2010-01-06 | 力晶半导体股份有限公司 | Voltage stabilizing device and flash memory |
| CN104714584A (en) * | 2013-12-13 | 2015-06-17 | 芯视达系统公司 | Voltage regulator with multiple output ranges and control method thereof |
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| Publication number | Publication date |
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| CN105404346B (en) | 2017-08-08 |
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