CN105391487B - Satellite link time delay simulator based on FPGA - Google Patents
Satellite link time delay simulator based on FPGA Download PDFInfo
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- CN105391487B CN105391487B CN201510671527.1A CN201510671527A CN105391487B CN 105391487 B CN105391487 B CN 105391487B CN 201510671527 A CN201510671527 A CN 201510671527A CN 105391487 B CN105391487 B CN 105391487B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1851—Systems using a satellite or space-based relay
Abstract
The invention discloses a kind of satellite link time delay simulator based on FPGA, it includes: IP packet discrimination module, receives the message of input for passing through into control unit, exports IP packet；Delays time to control module is sent out after delay process for receiving the IP packet that IP packet discrimination module is sent；Poller module is exported, for cooperating delays time to control module and going out the output of control module completion message.The present invention has many advantages, such as precision height, flexible operation, low in cost.
Description
Technical field
Present invention relates generally to satellite communication fields, refer in particular to a kind of satellite link time delay simulator based on FPGA.
Background technique
Satellite link is the basis of space-air-ground integration network communication, and influences the pass of space-air-ground integration network performance
Key factor.There is an urgent need to establish genuine and believable simulated experiment for the work such as test, verifying and assessment of space-air-ground integration network
Environment, link simulations technology are one of the key technologies that the such environment of building must solve.Therefore, carry out satellite link simulator
Development have great importance.
Satellite link has the distinct characteristic such as long delay, high bit error, asymmetric, and time delay simulation is satellite link simulator
One of critical function.In space environment, the transmission range between satellite link interior joint is longer, such as low-orbit satellite LEO
The distance of (Low Earth Orbit) away from ground communication station is usually 2000 kilometers, medium earth orbit satellite MEO (Medium Earth
Orbit) distance away from ground communication station has been more than 10000 kilometers, high orbit satellite GEO (Geostationary Earth
Orbit) apart from 35860 kilometers of the earth, therefore the transmission delay of link is larger.
Current several typical satellite link simulation tools are as follows:
(1) Spirent network simulator；
Spirent company mainly produces wireless communication test product, and product can provide currently for many wireless communication systems
Industry most accurately with advanced testing scheme,
SR5500/SR5500-M is most popular channel simulator.In the process of test wireless receiver,
SR5500 channel simulator can interfere RF reappears with decline effect, and SR5500 channel simulator can be to wireless channel
The characteristics such as shade decline, rapid fading and the channel loss of middle load bandwidth carry out accurately analog simulation.Since SR5500-M believes
Road emulator is capable of providing flexible, modular test configurations, therefore SR5500-M channel simulator not only can be right simultaneously
Multiple projects carry out concurrent testing, and can carry out joint test to large-scale project.
(2) Dummynet and NIST Net；
The purposes of Dummynet is divided to two aspects, is on the one hand the control for network bandwidth；It on the other hand is to carry out network
Test.Although it is operated on FreeBSD, also there is good transplantability for other protocol stacks.Its working principle
It is the data interception packet by way of protocol stack, to link propagation delay, bandwidth, packet loss etc. using IPFW packet filtering
The simulation of characteristic is completed by one or more pipelines.
NIST Net is a Open-Source Tools for capableing of dynamic real-time simulator IP network environment based on linux system, it can
Effective simulation and emulation in real time are carried out to the numerous characteristics in network, for example, NIST Net can link delay to network into
The effective simulation of row；The data-signal jittering characteristic of network link can really be reflected；It can also be existing to the packet loss in network
As accurately being simulated.Accurately and effectively research method is provided for the research of IP network environment.NIST Net is to do
For one of linux kernel can the module of dynamically load realize.Its architecture mainly includes two parts: one group is that can add
The kernel module of load；Another group uses interface for user.
The problems of above-mentioned conventional solution is summarized as follows:
(1) although the hardware time delay simulator precision height based on dedicated ASIC design, function are strong, price is prohibitively expensive,
And lack programmable extended capability.
(2) it although the time delay simulator based on software realization has great advantages in terms of flexibility, can not provide
In high precision, high performance time delay analog capability.
Summary of the invention
The technical problem to be solved in the present invention is that, for technical problem of the existing technology, the present invention provides one
Kind precision height, flexible operation, the low-cost satellite link time delay simulator based on FPGA.
In order to solve the above technical problems, the invention adopts the following technical scheme:
A kind of satellite link time delay simulator based on FPGA, it includes:
IP packet discrimination module, for passing through the message into the reception input of control unit, exporting IP packet；
Delays time to control module is sent out after delay process for receiving the IP packet that IP packet discrimination module is sent；
Poller module is exported, for cooperating delays time to control module and going out the output of control module completion message.
As a further improvement of the present invention: the non-IP packet through IP packet discrimination module is sent directly into output poller module
Complete message output.
As a further improvement of the present invention: the simulated operation object of the delays time to control module is continuous multiple Ethernets
The link transmission of IP datagram text is delayed；The delays time to control module is used to carry out accurately mould to satellite link constant time lag
It is quasi-, and effective simulation is carried out to Variable delay in link.
As a further improvement of the present invention: the delays time to control inside modules analog parameter will be total by configuring by user
Line is configured.
As a further improvement of the present invention: the delays time to control module includes two-port RAM, the effective number of delay parameter
Register, each delay parameter effective time register and delay process unit, the two-port RAM, delay parameter are effectively a
Number register, each delay parameter effective time register are connected with read-write configuration bus, and the configuration for carrying out delay parameter is made
Industry；After IP packet input, delay process is carried out by the delay process mechanism in the delay process unit, until completing message
The output of data.
As a further improvement of the present invention: the delay process mechanism in the delay process unit is that adoption status machine follows
The mode that Huantiao turns to wait realizes link packet delay function.
Compared with the prior art, the advantages of the present invention are as follows: the satellite link time delay of the invention based on FPGA simulates dress
It sets, it is precision height, flexible operation, low in cost, high-precision, high speed, the advantage of flexible programmable can be provided simultaneously with.The present invention is not only
Accurate simulation can be carried out to satellite link constant time lag, and can carry out effective simulation to Variable delay in link.
Detailed description of the invention
Fig. 1 is topological structure schematic diagram of the invention.
Fig. 2 is the topological structure schematic diagram of present invention delays time to control module in specific application example.
Fig. 3 is operation principle schematic diagram of the present invention in specific application example.
Specific embodiment
The present invention is described in further details below with reference to Figure of description and specific embodiment.
As shown in Figure 1, the satellite link time delay simulator of the invention based on FPGA, comprising:
IP packet discrimination module, for passing through the message into the reception input of control unit, exporting IP packet；
Delays time to control module is sent out after delay process for receiving the IP packet that IP packet discrimination module is sent；Prolong
When control module simulated operation object be continuous multiple ethernet ip data messages link transmission delay.This module can not only
Accurate simulation is carried out to satellite link constant time lag, and effective simulation can be carried out to Variable delay in link.In module
Portion's analog parameter will be configured by user by configuring bus.
Poller module is exported, for cooperating delays time to control module and going out the output of control module completion message.
Non- IP packet through IP packet discrimination module is sent directly into output poller module and completes message output.
In the present embodiment, delays time to control module includes that two-port RAM, the effective number of delay parameter are posted combined with Figure 1 and Figure 2,
Storage, each delay parameter effective time register and delay process unit, the effective number deposit of two-port RAM, delay parameter
Device, each delay parameter effective time register are connected with read-write configuration bus, carry out the configuration operation of delay parameter；IP report
After text input, delay process is carried out by the delay process mechanism in delay process unit, until completing the output of message data.
From the foregoing, it will be observed that being by the way of two-port RAM and register in the present invention come the storage for carrying out analog parameter, while with this
Analog parameter is managed for configuration in read-write bus in ground, and the delay process mechanism in delay process unit is that adoption status machine follows
The mode that Huantiao turns to wait realizes link packet delay function.
Satellite link time delay simulator based on FPGA of the invention, can complete following simulation job:
(1) for low-orbit satellite LEO, (Low Earth Orbit arrives the list of earth station highly for 500Km~900Km)
Journey link delay can be accomplished accurately to simulate, and simulation context is 1ms~10ms.
(2) for medium earth orbit satellite MEO, (Medium Earth Orbit highly arrives ground for 5000Km~12000Km)
Between one way link delay can accomplish accurately to simulate, simulation context be 10ms~100ms.
(3) for high orbit satellite GEO, (Geostationary Earth Orbit highly arrives earth station for 35768Km)
One way link delay can accomplish accurately to simulate, simulation delay size be 120ms.
In a specific application example, in conjunction with Fig. 3, wherein address_b is the read address of two-port RAM, rden_b
For the reading enable signal of two-port RAM, q_b is the read output data of two-port RAM；M and w is reg type register.This hair
Bright working principle is as follows:
(unit of T0 is ms, number n to analog parameter T0 needed for user passes through the configuration of local parameter control bus first
≤ 1021) with T1 (unit s).
Module parameter configuration enters normal operating conditions after completing, and there are three types of working conditions: idle state, transmit
State and discard state.Firstly, reading first from two-port RAM and each delay parameter effective time register respectively
The value of a analog parameter T0 and T1 calculates the value that cycling jump waits number m and the effective time state transition number w that is delayed.
Guaranteeing that this module identification fifo empty signal empty is that 0 and next module data FIFO can in idle state simulation device simultaneously
Whether the value that m is judged under the premise of holding next maximum length message is 0, if 0, then proves that delay time has arrived, state machine
It will jump to transmit forwarding state, start to send first message；Otherwise, simulator will do circulation in idle state and jump
Turn, while the value of m does the operation that subtracts 1, until the value of m reduces to 0.
Module will judge state according to [138:136] information of 139 bit format messages after jumping to transmit state
The forwarding of machine jumped with message is then header, state machine will jump to transmit state if 101；If 100,
Then among message, state machine will jump to transmit state；It is then message tail, state machine will jump to if 110
Idle state starts waiting to send next message, while calculating the value of m；If other values (except 101,100 and 110), then
It is considered as error message, state machine will jump to discard packet loss state, after error message is abandoned, jump back to idle state etc.
Transmission to next message.
In each clock cycle of state machine work, module will also monitor the value of w simultaneously, if w is 0, prove at this time
The effective time of clock cycle T 0 has arrived, and module can provide the reading enable signal of a RAM (if the value of read address is equal to link simultaneously
The number n-1 of average delay, then the value of read address is set to 0, and otherwise the value of read address is done plus 1 operates), read next T0's
Value, and calculate the value of new m.Meanwhile being recalculated as the value of w；Otherwise the value of (w > 0), this clock cycle T 0 is still effective,
W subtracts 1, until w reduces to 0.
The above is only the preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-described embodiment,
All technical solutions belonged under thinking of the present invention all belong to the scope of protection of the present invention.It should be pointed out that for the art
For those of ordinary skill, several improvements and modifications without departing from the principles of the present invention should be regarded as protection of the invention
Range.
Claims (4)
1. a kind of satellite link time delay simulator based on FPGA characterized by comprising
IP packet discrimination module, for passing through the message into the reception input of control unit, exporting IP packet；
Delays time to control module is sent out after delay process for receiving the IP packet that IP packet discrimination module is sent；It is described to prolong
When control module include two-port RAM, the effective number register of delay parameter, each delay parameter effective time register and prolong
When processing unit, the effective number register of the two-port RAM, delay parameter, each delay parameter effective time register are equal
It is connected with read-write configuration bus, carries out the configuration operation of delay parameter；After IP packet input, by the delay process unit
Delay process mechanism carries out delay process, until completing the output of message data；
Poller module is exported, for cooperating delays time to control module and going out the output of control module completion message, differentiates mould through IP packet
The non-IP packet of block is sent directly into output poller module and completes message output；
Pass through analog parameter T0 and T1 needed for the configuration of local parameter control bus；
Module parameter configuration enters normal operating conditions after completing, and there are three types of working conditions: idle state, transmit state
With discard state；Firstly, first mould is read from two-port RAM and each delay parameter effective time register respectively
The value of quasi- parameter T0 and T1 calculate the value that cycling jump waits number m and the effective time state transition number w that is delayed；Simultaneously
Guaranteeing that this module identification fifo empty signal empty is that 0 and next module data FIFO can be held in idle state simulation device
Whether the value that m is judged under the premise of one maximum length message is 0, if 0, then proves that delay time has arrived, and state machine will jump
Transmit forwarding state is gone to, starts to send first message；Otherwise, simulator will do cycling jump in idle state, together
When m value do the operation that subtracts 1, until the value of m reduces to 0；
Module will judge jumping for state machine and turning for message after jumping to transmit state according to the information of format message
Hair, when being determined as header, state machine will jump to transmit state；It is determined as among message, state machine will jump to
Transmit state；It is determined as message tail, state machine will jump to idle state, start waiting to send next message, together
When calculate m value；If other values, then it is considered as error message, state machine will jump to discard packet loss state, by false alarm
After text abandons, the transmission that idle state waits next message is jumped back to.
2. the satellite link time delay simulator according to claim 1 based on FPGA, which is characterized in that the delay control
The simulated operation object of molding block is the link transmission delay of continuous multiple ethernet ip data messages；The delays time to control module
For carrying out accurate simulation to satellite link constant time lag, and effective simulation is carried out to Variable delay in link.
3. the satellite link time delay simulator according to claim 1 based on FPGA, which is characterized in that the delay control
Molding block internal simulation parameter will be configured by user by configuring bus.
4. the satellite link time delay simulator according to claim 1 based on FPGA, which is characterized in that at the delay
Delay process mechanism in reason unit is that the mode that adoption status machine cycling jump waits realizes link packet delay function.
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Citations (4)
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| US5467345A (en) * | 1994-05-31 | 1995-11-14 | Motorola, Inc. | Packet routing system and method therefor |
| JP2000332669A (en) * | 1999-05-20 | 2000-11-30 | Hitachi Ltd | Satellite communication network simulation system |
| CN102571781A (en) * | 2011-12-28 | 2012-07-11 | 南京邮电大学 | Transmission control protocol connection disconnecting method suitable for integrated satellite communication system |
| CN102664867A (en) * | 2012-03-15 | 2012-09-12 | 南京邮电大学 | Method for enhancing transmission protocols in satellite communication system |
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2015
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5467345A (en) * | 1994-05-31 | 1995-11-14 | Motorola, Inc. | Packet routing system and method therefor |
| JP2000332669A (en) * | 1999-05-20 | 2000-11-30 | Hitachi Ltd | Satellite communication network simulation system |
| CN102571781A (en) * | 2011-12-28 | 2012-07-11 | 南京邮电大学 | Transmission control protocol connection disconnecting method suitable for integrated satellite communication system |
| CN102664867A (en) * | 2012-03-15 | 2012-09-12 | 南京邮电大学 | Method for enhancing transmission protocols in satellite communication system |
Non-Patent Citations (1)
| Title |
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| "星地链路特性分析及其仿真器设计与实现";尹艳平;《CNKI工学硕士学位论文》;20121201;第26-47页 |
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