CN105391426A - A high-speed latch capable of receiving millivolt signals - Google Patents
A high-speed latch capable of receiving millivolt signals Download PDFInfo
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- CN105391426A CN105391426A CN201510935215.7A CN201510935215A CN105391426A CN 105391426 A CN105391426 A CN 105391426A CN 201510935215 A CN201510935215 A CN 201510935215A CN 105391426 A CN105391426 A CN 105391426A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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Abstract
The invention discloses a high-speed latch capable of receiving millivolt signals. The latch comprises a reference current source used for providing a reference current for the latch; a sampling amplification circuit for carrying out sampling amplification on input signals; a latch circuit for carrying out latch on sampling point data of the sampling amplification circuit; and a current amplification circuit for carrying out amplification on charging and discharging current of the sampling circuit when the latch is switched from a latch state to a sampling state. The sampling amplification circuit is connected with the current amplification circuit; and the current amplification circuit is connected with the latch circuit. The current amplification circuit comprises an emitter follower, wherein current gain of the emitter follower is beta; and when the latch is switched from the latch state to the sampling state, the charging and discharging current of the sampling circuit has enough current to charge/discharge an output node after being amplified for beta times by the current amplification circuit. The high-speed latch solves the problem of reception of the millivolt high-speed signals of the latch, reduces a comparator structure of a conventional EOM circuit, reduces power consumption and simplifies circuit structure.
Description
Technical field
The present invention relates to a kind of high-speed latches that can receive millivolt signal.
Background technology
The requirement of modern communications to data transfer rate and transmission range is more and more higher, but the signal quality that the impact of the non-ideal factor such as crosstalk, reflection makes receiver receive is very poor.Therefore in high-speed signal transmission circuit, more and more being integrated with EOM(eye pattern to detect) circuit detects the signal quality received, by judging that the stretching degree of eye pattern adjusts equalizer coefficients, thus recover correct data, sampler is part and parcel in EOM circuit.
In current EOM circuit, more common way is first through a high-speed comparator, small-signal is converted to CML (current-mode) level (general 200mV ~ 800mV), then gives trigger sampling, as shown in Figure 1.This scheme opposed configuration is complicated, therefore can consume more area and power consumption.
The defect that convention latches exists: traditional latch structure as shown in Figure 2.Region I is sample circuit, and Q11, Q12 and R11, R12 form difference cascode level amplifying circuit, when sample states, amplify input voltage signal, but when amplifying high speed signal, gain generally only have about 1 ~ 2.Region II is latch cicuit, and Q13, Q14 and R11, R12 are regenerative circuit, latch the signal sampled.Q15, Q16 are bias current diverter switch, control the switching of sampling and latch mode.
When input signal is CML level, when latch clock is high (for high, CLK-is low to CLK+), bias current flows through Q5, and passing through sample circuit, latch is in sample states, input signal amplifies by Q11, Q12 and R11, R12, and output node exports sampled signal.When latch clock is low (CLK+ is low, and CLK-is high), bias current flows through latch cicuit by Q6, and latch is in latch mode, and Q13, Q14 and R11, R12 regenerative circuit are by the voltage latch of sample states, and the level of this process as shown in Figure 3.Because output current is relevant to applied signal voltage, as shown in Figure 4, input signal amplitude is greater than 3V
t(V
t=26mV), so sampled output current is enough large, make level can in the time internal conversion needed to required voltage.
When input signal is the voltage signal of mV level, the output node voltage of latch mode is CML level, when being transformed into sample states, the output current of sample circuit (Q11, Q12 and R11, R12) is very little, very weak to output node (OUT+, OUT-) charging ability, can not at short notice (half clock cycle) make output node reach target voltage, cause latch to make mistakes, as shown in Figure 5.Therefore traditional latch structure can not process the input signal of low amplitude value.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of high-speed latches that can receive millivolt level signal is provided, solves latch to the Receiver Problem of the high speed signal of millivolt level, remove the comparator configuration of traditional E OM circuit, reduce power consumption, simplify circuit structure.
The object of the invention is to be achieved through the following technical solutions: the high-speed latches that can receive millivolt level signal, it comprises reference current source, for latch provides reference current; Amplifier circuit, carries out amplifier to input signal; Latch cicuit, latches amplifier circuit sampling point data; Current amplification circuit, amplifies the charging and discharging currents of sample circuit when latch is switched to sample states by latch mode; Amplifier circuit is connected with current amplification circuit, and current amplification circuit is connected with latch cicuit; Current amplification circuit comprises penetrates a grade follower, the current gain of penetrating grade follower is β, when latch is switched to sample states by latch mode, the charging and discharging currents of sample circuit, after current amplification circuit amplifies β times, has enough electric currents to output node discharge and recharge.
Described amplifier circuit comprises the first triode Q1, second triode Q2, first resistance R1, second resistance R2 and the second metal-oxide-semiconductor M2, the positive port of input signal is connected with the base stage of the first triode Q1, the negative terminal mouth of input signal is connected with the base stage of the second triode Q2, the collector electrode of the first triode Q1 is connected with the first resistance R1, the collector electrode of the second triode Q2 is connected with the second resistance R2, first resistance R1 is connected with supply voltage with the other end of the second resistance R2, first triode Q1 is connected with the drain electrode of the second metal-oxide-semiconductor M2 with the emitter of the second triode Q2, the source ground of the second metal-oxide-semiconductor M2, grid is connected with reference current source.
Described current amplification circuit comprises the 3rd triode Q3, 4th triode Q4, 5th triode Q5, 6th triode Q6, 7th triode Q7, 8th triode Q8, 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4, 3rd triode Q3 is connected with supply voltage with the collector electrode of the 4th triode Q4, the base stage of the 3rd triode Q3 is connected with the collector electrode of the first triode Q1, the base stage of the 4th triode Q4 is connected with the collector electrode of the second triode Q2, the emitter of the 3rd triode Q3 is connected with the collector electrode of the 7th triode Q7, the emitter of the 4th triode Q4 is connected with the collector electrode of the 8th triode Q8, 7th triode Q7 is connected with negative clock signal jointly with the base stage of the 8th triode Q8, the emitter of the 7th triode Q7 is connected with the drain electrode of the 3rd metal-oxide-semiconductor M3, the emitter of the 8th triode Q8 is connected with the drain electrode of the 4th metal-oxide-semiconductor, the collector electrode of the 5th triode Q5 is connected with the collector electrode of the first triode Q1, the collector electrode of the 6th triode Q6 is connected with the collector electrode of the second triode Q2, 5th triode Q5 is connected with positive clock signals jointly with the base stage of the 6th triode Q6, the emitter of the 5th triode Q5 is connected with the drain electrode of the 3rd metal-oxide-semiconductor M3, the emitter of the 6th triode Q6 is connected with the drain electrode of the 4th metal-oxide-semiconductor, 3rd metal-oxide-semiconductor M3 is connected with reference current source with the grid of the 4th metal-oxide-semiconductor M4, source ground.
Described latch cicuit comprises the 3rd resistance R3, 4th resistance R4, 9th triode Q9, tenth triode Q10 and the 5th metal-oxide-semiconductor M5, 3rd resistance R3, one end of 4th resistance R4 is connected with supply voltage, the other end of the 3rd resistance R3 is connected with the collector electrode of the 9th triode Q9, the other end of the 4th resistance R4 is connected with the collector electrode of the tenth triode Q10, the collector electrode of the 9th triode Q9 is connected with the collector electrode of the 7th triode Q7, the collector electrode of the tenth triode Q10 is connected with the collector electrode of the 8th triode Q8, the base stage of the 9th triode Q9 is connected with the collector electrode of the tenth triode Q10, the base stage of the tenth triode Q10 is connected with the collector electrode of the 9th triode Q9, 9th triode Q9 is connected with the drain electrode of the 5th metal-oxide-semiconductor M5 with the emitter of the tenth triode Q10, the collector electrode of the 9th triode Q9 is also connected with positive output port, the collector electrode of the tenth triode Q10 is also connected with negative output port, the grid of the 5th metal-oxide-semiconductor M5 is connected with reference current source, source ground.
Described reference current source comprises reference current source and the first metal-oxide-semiconductor M1, and the drain electrode of the first metal-oxide-semiconductor M1 is connected with reference current source with base stage, source ground.
The invention has the beneficial effects as follows: the invention provides a kind of high-speed latches that can receive millivolt level signal, solve the Receiver Problem of latch to the high speed signal of millivolt level, eliminate the comparator configuration of traditional E OM circuit, reduce power consumption, simplify circuit structure.
Accompanying drawing explanation
Fig. 1 is the sampling structure in traditional E OM (eye pattern detection) circuit;
Fig. 2 is convention latches structure;
Fig. 3 is convention latches CML level input sample output map;
Fig. 4 is the relation of output current and input voltage;
Fig. 5 is convention latches millivolt level signal input sample output map;
Fig. 6 is novel latch structure of the present invention;
Fig. 7 is millivolt level signal sampling output map of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.
As shown in Figure 6, can receive the high-speed latches of millivolt level signal, it comprises reference current source, for latch provides reference current; Amplifier circuit, carries out amplifier to input signal; Latch cicuit, latches amplifier circuit sampling point data; Current amplification circuit, amplifies the charging and discharging currents of sample circuit when latch is switched to sample states by latch mode; Amplifier circuit is connected with current amplification circuit, and current amplification circuit is connected with latch cicuit; Current amplification circuit comprises penetrates a grade follower, the current gain of penetrating grade follower is β, when latch is switched to sample states by latch mode, the charging and discharging currents of sample circuit, after current amplification circuit amplifies β times, has enough electric currents to output node discharge and recharge.
Described amplifier circuit comprises the first triode Q1, second triode Q2, first resistance R1, second resistance R2 and the second metal-oxide-semiconductor M2, the positive port of input signal is connected with the base stage of the first triode Q1, the negative terminal mouth of input signal is connected with the base stage of the second triode Q2, the collector electrode of the first triode Q1 is connected with the first resistance R1, the collector electrode of the second triode Q2 is connected with the second resistance R2, first resistance R1 is connected with supply voltage with the other end of the second resistance R2, first triode Q1 is connected with the drain electrode of the second metal-oxide-semiconductor M2 with the emitter of the second triode Q2, the source ground of the second metal-oxide-semiconductor M2, grid is connected with reference current source.
Described current amplification circuit comprises the 3rd triode Q3, 4th triode Q4, 5th triode Q5, 6th triode Q6, 7th triode Q7, 8th triode Q8, 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4, 3rd triode Q3 is connected with supply voltage with the collector electrode of the 4th triode Q4, the base stage of the 3rd triode Q3 is connected with the collector electrode of the first triode Q1, the base stage of the 4th triode Q4 is connected with the collector electrode of the second triode Q2, the emitter of the 3rd triode Q3 is connected with the collector electrode of the 7th triode Q7, the emitter of the 4th triode Q4 is connected with the collector electrode of the 8th triode Q8, 7th triode Q7 is connected with negative clock signal jointly with the base stage of the 8th triode Q8, the emitter of the 7th triode Q7 is connected with the drain electrode of the 3rd metal-oxide-semiconductor M3, the emitter of the 8th triode Q8 is connected with the drain electrode of the 4th metal-oxide-semiconductor, the collector electrode of the 5th triode Q5 is connected with the collector electrode of the first triode Q1, the collector electrode of the 6th triode Q6 is connected with the collector electrode of the second triode Q2, 5th triode Q5 is connected with positive clock signals jointly with the base stage of the 6th triode Q6, the emitter of the 5th triode Q5 is connected with the drain electrode of the 3rd metal-oxide-semiconductor M3, the emitter of the 6th triode Q6 is connected with the drain electrode of the 4th metal-oxide-semiconductor, 3rd metal-oxide-semiconductor M3 is connected with reference current source with the grid of the 4th metal-oxide-semiconductor M4, source ground.
Described latch cicuit comprises the 3rd resistance R3, 4th resistance R4, 9th triode Q9, tenth triode Q10 and the 5th metal-oxide-semiconductor M5, 3rd resistance R3, one end of 4th resistance R4 is connected with supply voltage, the other end of the 3rd resistance R3 is connected with the collector electrode of the 9th triode Q9, the other end of the 4th resistance R4 is connected with the collector electrode of the tenth triode Q10, the collector electrode of the 9th triode Q9 is connected with the collector electrode of the 7th triode Q7, the collector electrode of the tenth triode Q10 is connected with the collector electrode of the 8th triode Q8, the base stage of the 9th triode Q9 is connected with the collector electrode of the tenth triode Q10, the base stage of the tenth triode Q10 is connected with the collector electrode of the 9th triode Q9, 9th triode Q9 is connected with the drain electrode of the 5th metal-oxide-semiconductor M5 with the emitter of the tenth triode Q10, the collector electrode of the 9th triode Q9 is also connected with positive output port, the collector electrode of the tenth triode Q10 is also connected with negative output port, the grid of the 5th metal-oxide-semiconductor M5 is connected with reference current source, source ground.
Described reference current source comprises reference current source and the first metal-oxide-semiconductor M1, and the drain electrode of the first metal-oxide-semiconductor M1 is connected with reference current source with base stage, source ground.
The present invention is by separating sampling and latch cicuit, and two parts circuit is free of attachment to same output node, increases simultaneously and penetrates grade follower as connection, as shown in Figure 6 between two parts circuit.I partial circuit (Q1, Q2, R1 and R2) is amplifier circuit, and II partial circuit (Q9, Q10, R3 and R4) is latch cicuit, and III partial circuit (Q3, Q4, Q5, Q6, Q7 and Q8) is current amplification circuit.
Invention increases III part Current amplifier structure, current amplification circuit is formed by penetrating a grade follower, and the voltage gain penetrating grade follower approximates 1, and current gain is β (more than 100 times).Like this when latch mode is switched to sampling shape, although the charging and discharging currents of sample circuit is very little, but after current amplification circuit is exaggerated β times, just there are enough electric currents to output node discharge and recharge, change in voltage is faster, voltage gain approximates 1 simultaneously, also can not affect the transmission of information of voltage between sample circuit and latch cicuit.Such as input voltage is 1mV, under the Current amplifier effect of penetrating grade follower, also can reach the discharge and recharge effect of input voltage for the input voltage of mV more than 100, so just can reach discharge and recharge time requirement at a high speed.
Specific works flow process: the state being controlled latch by the bias current controlling to penetrate grade follower is switched, (the CLK+ low level when CLK is low, CLK-high level), bias current is by penetrating a grade follower, penetrate voltage signal that input sampling circuit adopts by grade follower to amplify and deliver to latch cicuit, the change in voltage of output node (OUT+ and OUT-) is very large, owing to penetrating the Current amplifier effect of grade follower, also can be very fast carry out change in voltage, there is no the problem of the charging and discharging currents deficiency of convention latches, now export the result for sample circuit, for sample states.
(the CLK+ high level when CLK is high, CLK-low level), electric current is by Q5 and Q6, dragged down by the common-mode voltage of input sampling circuit output node, and the common mode of latch cicuit output node is constant, the input and output voltage difference of penetrating grade follower is less than the forward conduction voltage of diode, penetrate a grade follower not conducting, having completely cut off sampling and latch cicuit, exported the result after into latches, is latch mode.The present invention is receiving the signal waveform of millivolt level as shown in Figure 7.
Claims (5)
1. can receive the high-speed latches of millivolt level signal, it is characterized in that: it comprises reference current source, for latch provides reference current; Amplifier circuit, carries out amplifier to input signal; Latch cicuit, latches amplifier circuit sampling point data; Current amplification circuit, amplifies the charging and discharging currents of sample circuit when latch is switched to sample states by latch mode; Amplifier circuit is connected with current amplification circuit, and current amplification circuit is connected with latch cicuit; Current amplification circuit comprises penetrates a grade follower, the current gain of penetrating grade follower is β, when latch is switched to sample states by latch mode, the charging and discharging currents of sample circuit, after current amplification circuit amplifies β times, has enough electric currents to output node discharge and recharge.
2. the high-speed latches that can receive millivolt level signal according to claim 1, it is characterized in that: described amplifier circuit comprises the first triode Q1, second triode Q2, first resistance R1, second resistance R2 and the second metal-oxide-semiconductor M2, the positive port of input signal is connected with the base stage of the first triode Q1, the negative terminal mouth of input signal is connected with the base stage of the second triode Q2, the collector electrode of the first triode Q1 is connected with the first resistance R1, the collector electrode of the second triode Q2 is connected with the second resistance R2, first resistance R1 is connected with supply voltage with the other end of the second resistance R2, first triode Q1 is connected with the drain electrode of the second metal-oxide-semiconductor M2 with the emitter of the second triode Q2, the source ground of the second metal-oxide-semiconductor M2, grid is connected with reference current source.
3. the high-speed latches that can receive millivolt level signal according to claim 1, it is characterized in that: described current amplification circuit comprises the 3rd triode Q3, 4th triode Q4, 5th triode Q5, 6th triode Q6, 7th triode Q7, 8th triode Q8, 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4, 3rd triode Q3 is connected with supply voltage with the collector electrode of the 4th triode Q4, the base stage of the 3rd triode Q3 is connected with the collector electrode of the first triode Q1, the base stage of the 4th triode Q4 is connected with the collector electrode of the second triode Q2, the emitter of the 3rd triode Q3 is connected with the collector electrode of the 7th triode Q7, the emitter of the 4th triode Q4 is connected with the collector electrode of the 8th triode Q8, 7th triode Q7 is connected with negative clock signal jointly with the base stage of the 8th triode Q8, the emitter of the 7th triode Q7 is connected with the drain electrode of the 3rd metal-oxide-semiconductor M3, the emitter of the 8th triode Q8 is connected with the drain electrode of the 4th metal-oxide-semiconductor, the collector electrode of the 5th triode Q5 is connected with the collector electrode of the first triode Q1, the collector electrode of the 6th triode Q6 is connected with the collector electrode of the second triode Q2, 5th triode Q5 is connected with positive clock signals jointly with the base stage of the 6th triode Q6, the emitter of the 5th triode Q5 is connected with the drain electrode of the 3rd metal-oxide-semiconductor M3, the emitter of the 6th triode Q6 is connected with the drain electrode of the 4th metal-oxide-semiconductor, 3rd metal-oxide-semiconductor M3 is connected with reference current source with the grid of the 4th metal-oxide-semiconductor M4, source ground.
4. the high-speed latches that can receive millivolt level signal according to claim 1, it is characterized in that: described latch cicuit comprises the 3rd resistance R3, 4th resistance R4, 9th triode Q9, tenth triode Q10 and the 5th metal-oxide-semiconductor M5, 3rd resistance R3, one end of 4th resistance R4 is connected with supply voltage, the other end of the 3rd resistance R3 is connected with the collector electrode of the 9th triode Q9, the other end of the 4th resistance R4 is connected with the collector electrode of the tenth triode Q10, the collector electrode of the 9th triode Q9 is connected with the collector electrode of the 7th triode Q7, the collector electrode of the tenth triode Q10 is connected with the collector electrode of the 8th triode Q8, the base stage of the 9th triode Q9 is connected with the collector electrode of the tenth triode Q10, the base stage of the tenth triode Q10 is connected with the collector electrode of the 9th triode Q9, 9th triode Q9 is connected with the drain electrode of the 5th metal-oxide-semiconductor M5 with the emitter of the tenth triode Q10, the collector electrode of the 9th triode Q9 is also connected with positive output port, the collector electrode of the tenth triode Q10 is also connected with negative output port, the grid of the 5th metal-oxide-semiconductor M5 is connected with reference current source, source ground.
5. the high-speed latches that can receive millivolt level signal according to claim 1, is characterized in that: described reference current source comprises reference current source and the first metal-oxide-semiconductor M1, and the drain electrode of the first metal-oxide-semiconductor M1 is connected with reference current source with base stage, source ground.
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|---|---|---|---|
| CN201510935215.7A CN105391426B (en) | 2015-12-15 | 2015-12-15 | The high-speed latches of millivolt level signal can be received |
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| CN201510935215.7A CN105391426B (en) | 2015-12-15 | 2015-12-15 | The high-speed latches of millivolt level signal can be received |
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| CN105391426B CN105391426B (en) | 2018-05-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107332562A (en) * | 2017-05-27 | 2017-11-07 | 烽火通信科技股份有限公司 | Signal sample circuit |
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| CN101431327A (en) * | 2007-11-06 | 2009-05-13 | 瑞昱半导体股份有限公司 | Bolt lock device |
| US20100013535A1 (en) * | 2008-07-17 | 2010-01-21 | Taek-Sang Song | Latch circuit |
| US20130127507A1 (en) * | 2011-11-18 | 2013-05-23 | Jingcheng Zhuang | Low-hysteresis high-speed differential sampler |
| US20130335129A1 (en) * | 2012-06-13 | 2013-12-19 | Fujitsu Limited | Current Mode Logic Latch |
| CN205160488U (en) * | 2015-12-15 | 2016-04-13 | 成都振芯科技股份有限公司 | Can receive high -speed latch of millivolt level signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877642A (en) * | 1995-11-17 | 1999-03-02 | Nec Corporation | Latch circuit for receiving small amplitude signals |
| CN101431327A (en) * | 2007-11-06 | 2009-05-13 | 瑞昱半导体股份有限公司 | Bolt lock device |
| US20100013535A1 (en) * | 2008-07-17 | 2010-01-21 | Taek-Sang Song | Latch circuit |
| US20130127507A1 (en) * | 2011-11-18 | 2013-05-23 | Jingcheng Zhuang | Low-hysteresis high-speed differential sampler |
| US20130335129A1 (en) * | 2012-06-13 | 2013-12-19 | Fujitsu Limited | Current Mode Logic Latch |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107332562A (en) * | 2017-05-27 | 2017-11-07 | 烽火通信科技股份有限公司 | Signal sample circuit |
| CN107332562B (en) * | 2017-05-27 | 2020-12-15 | 烽火通信科技股份有限公司 | Signal sampling circuit |
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| CN105391426B (en) | 2018-05-11 |
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