CN105375887B - Buffer amplifying circuit - Google Patents
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- CN105375887B CN105375887B CN201510882013.0A CN201510882013A CN105375887B CN 105375887 B CN105375887 B CN 105375887B CN 201510882013 A CN201510882013 A CN 201510882013A CN 105375887 B CN105375887 B CN 105375887B
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Abstract
The application discloses buffering amplifier circuit, amplifier circuit includes: the device comprises a bias amplification unit, a first compensation unit and a second compensation unit; the bias amplifying unit comprises a bias resistor, a first transistor and a second transistor; an input signal is transmitted to the grids of the first transistor and the second transistor through a signal input end of the amplifying circuit, and is amplified by the first transistor and the second transistor to be output as a first signal through a signal output end of the bias amplifying unit; the first compensation unit and the second compensation unit are used for providing negative feedback to the bias amplification unit, so that the signal bandwidth of the bias amplification unit is improved, the rising edge and the falling edge of the output signal of the amplification circuit are steep, the modulation of the output signal of the amplification circuit by the 1/f noise of the transistor is reduced, and the improved phase noise performance of the output signal is obtained.
Description
Technical field
The present invention relates to semiconductor applications, systems a kind of buffer amplifier circuit.
Background technology
Buffer amplifier is widely used in on-chip integration system and communication system.Fig. 1 is generally use in the prior art
The circuit diagram of buffer amplifier, as shown in Figure 1, the buffer amplifier includes biasing resistor R0, the first transistor M1 and second
Transistor M2, wherein one end of the biasing resistor R0 is connect with the grid of the first transistor M1, second transistor M2,
As the signal input part Vin of the buffer amplifier, the drain electrode of the other end and the first transistor M1, second transistor M2
Connection, as signal output end G；The first transistor M1 is N-channel enhancement mode FET, and substrate and source electrode are grounded,
The second transistor M2 is that P-channel enhancement type FET, substrate and source electrode are connect with DC power supply VDD；The biasing
Resistance R0 is used to the first transistor M1, second transistor M2 being biased in saturation amplification region, so that passing through the letter
The input signal of number input terminal Vin can be exported after the first transistor M1, second transistor M2 amplifications.
Because flicker noise (i.e. 1/f noise) is generated since defects from semiconductor materials causes electric current random fluctuation,
And the defect of semi-conducting material is inevitable at present, for the buffer amplifier, in amplification input letter
Number while, the 1/f noise of transistor will be modulated in the output signal of amplification, show as the phase noise of output signal,
Excessive phase noise makes the buffer amplifier be difficult to meet the requirement of high performance communication system and on-chip integration system.
Therefore, there is an urgent need for a kind of smaller buffer amplifiers of the phase noise of output signal.
Invention content
An embodiment of the present invention provides a kind of buffer amplifier circuit, the amplifying circuit has preferable phase noise
Energy.
A kind of buffer amplifier circuit, including：Bias amplifying unit, the first compensating unit and the second compensating unit；Wherein,
The biasing amplifying unit includes biasing resistor, the first transistor, second transistor；The first transistor,
The grid of two-transistor is connect with one end of the biasing resistor, as the signal input part of the amplifying circuit, described first
The drain electrode of transistor, second transistor is connect with the other end of the biasing resistor, the signal as the biasing amplifying unit
Output end, the source electrode of the first transistor are connect with first compensating unit, the source electrode of the second transistor with it is described
Second compensating unit connects, and input signal is transmitted to the first transistor and the by the signal input part of the amplifying circuit
The grid of two-transistor is put by being used as the first signal after the first transistor and second transistor amplification via the biasing
The signal output end of big unit exports；
First compensating unit one end is connect with the source electrode of the first transistor, and other end ground connection is used for described
It biases amplifying unit and negative-feedback is provided, improve the signal bandwidth of the biasing amplifying unit；
Second compensating unit one end is connect with the source electrode of the second transistor, and the other end is connect with power supply, is used for
Negative-feedback is provided to the biasing amplifying unit, improves the signal bandwidth of the biasing amplifying unit.
Preferably, first compensating unit includes first resistor and the first capacitance, the first resistor and the first capacitance
Parallel connection, one end are connect with the source electrode of the first transistor, other end ground connection.
Preferably, second compensating unit includes second resistance and the second capacitance, the second resistance and the second capacitance
Parallel connection, one end are connect with the source electrode of the second transistor, and the other end is connect with power supply.
Preferably, the biasing amplifying unit further includes compensation amplifying unit, and the compensation amplifying unit includes：Third is brilliant
Body pipe and the 4th transistor；Wherein,
The third transistor, the 4th transistor grid be connected to the signal input part of the amplifying circuit, the third
The drain electrode of transistor, the 4th transistor is connected to the signal output end of the biasing amplifying unit, and the third transistor is N-channel
Enhanced field-effect tube, source electrode and Substrate ground, the 4th transistor be P-channel enhancement type FET, source electrode and
Substrate is connect with power supply；
Input signal is transmitted to the third transistor and the 4th transistor by the signal input part of the amplifying circuit
Grid, by be used as second signal after the third transistor and the amplification of the 4th transistor, the second signal and described the
One Signal averaging forms the second composite signal and is exported by the signal output end of the biasing amplifying unit, to improve the amplification electricity
The signal gain on road.
Preferably, the amplifying circuit further includes the first reverse phase amplifying unit, the signal of the first reverse phase amplifying unit
Input is terminated at the signal output end of the biasing amplifying unit, is carried out for the output signal to the biasing amplifying unit anti-
Mutually amplify, and third signal is exported by the signal output end of the first reverse phase amplifying unit.
Preferably, the first reverse phase amplifying unit includes the 5th transistor and the 6th transistor；Wherein,
5th transistor, the 6th transistor grid be connected to it is described biasing amplifying unit signal output end, as
The signal input part of the first reverse phase amplifying unit, the drain electrode connection of the 5th transistor, the 6th transistor, as described
The signal output end of first reverse phase amplifying unit, the 5th transistor are N-channel enhancement mode FET, source electrode and substrate
Ground connection, the 6th transistor are P-channel enhancement type FET, and source electrode and substrate are connected to DC power supply, and the biasing is put
The output signal of big unit is transmitted to the 5th transistor and by the signal input part of the first reverse phase amplifying unit
The grid of six transistors amplifies list after the amplification of the reverse phase of the 5th transistor and the 6th transistor by first reverse phase
The signal output end of member exports third signal.
Preferably, the amplifying circuit further includes the second reverse phase amplifying unit, the signal of the second reverse phase amplifying unit
Input is terminated at the signal output end of the first reverse phase amplifying unit, for carrying out reverse phase amplification to the third signal and leading to
Cross the signal output end output fourth signal of the second reverse phase amplifying unit.
Preferably, the second reverse phase amplifying unit includes：7th transistor and the 8th transistor；Wherein,
7th transistor, the 8th transistor grid be connected to the signal output end of the first reverse phase amplifying unit,
As the signal input part of the second reverse phase amplifying unit, the drain electrode connection of the 7th transistor, the 8th transistor, as
The signal output end of the second reverse phase amplifying unit, the 7th transistor be N-channel enhancement mode FET, source electrode and
Substrate ground, the 8th transistor are P-channel enhancement type FET, and source electrode and substrate are connected to DC power supply, described the
Three signals are transmitted to the 7th transistor and the 8th transistor by the signal input part of the second reverse phase amplifying unit
Grid, it is defeated by the signal of the second reverse phase amplifying unit after the amplification of the reverse phase of the 7th transistor and the 8th transistor
Outlet exports fourth signal.
Preferably, the amplifying circuit further includes：Capacitance；
Signal input part of the one end of the capacitance as the amplifying circuit, it is another to be terminated at the first crystal
It manages, the connecting node of the grid and the biasing resistor of second transistor, the DC level for blocked input signal is to described
The influence of amplifying circuit.
Preferably, the first transistor is N-channel enhancement mode FET, and the second transistor enhances for P-channel
Type field-effect tube.
Compared with prior art, above-mentioned technical proposal has the following advantages：
An embodiment of the present invention provides a kind of buffer amplifier circuits, including：Bias amplifying unit, the first compensating unit and the
Two compensating units；Wherein, first compensating unit and the second compensating unit are negative anti-by being provided for the biasing amplifying unit
Feedback has widened the signal bandwidth of the biasing amplifying unit so that the rising edge of the output signal of the amplifying circuit and decline
Along steepening, modulation of the transistor 1/f noise to the output signal of the amplifying circuit is reduced, to obtain improved output
Signal phase noiseproof feature.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the circuit diagram of the buffer amplifier used in the prior art；
Fig. 2 is a kind of circuit diagram for buffer amplifier circuit that one embodiment of the present of invention provides；
Fig. 3 is the amplifying circuit negative-feedback gain bandwidth change schematic diagram that one embodiment of the present of invention provides；
Fig. 4 is a kind of first compensating unit that the specific embodiment of the present invention provides and the second compensating unit
Concrete structure；
Fig. 5 is a kind of circuit diagram for buffer amplifier circuit that another specific embodiment of the present invention provides；
Fig. 6 is a kind of circuit for load-carrying buffer amplifier circuit that the particular preferred embodiment of the present invention provides
Figure；
Fig. 7-9 is the amplifying circuit and the buffer amplifier output signal that an alternative embodiment of the invention provides
Phase noise vs figure；
Figure 10 is the amplifying circuit and the buffer amplifier same period that another embodiment of the present invention provides
Interior the comparison diagram by electric current.
Specific implementation mode
As described in background, the prior art use buffer amplifier due to the phase noise of output signal it is excessive,
It is difficult to meet the requirement of high performance communication system and on-chip integration system.
In view of this, an embodiment of the present invention provides a kind of buffer amplifier circuits, including：Bias amplifying unit, the first benefit
Repay unit and the second compensating unit；Wherein,
The biasing amplifying unit includes biasing resistor, the first transistor, second transistor；The first transistor,
The grid of two-transistor is connect with one end of the biasing resistor, as the signal input part of the amplifying circuit, described first
The drain electrode of transistor, second transistor is connect with the other end of the biasing resistor, the signal as the biasing amplifying unit
Output end, the source electrode of the first transistor are connect with first compensating unit, the source electrode of the second transistor with it is described
Second compensating unit connects, and input signal is transmitted to the first transistor and the by the signal input part of the amplifying circuit
The grid of two-transistor is put by being used as the first signal after the first transistor and second transistor amplification via the biasing
The signal output end of big unit exports；
First compensating unit one end is connect with the source electrode of the first transistor, and other end ground connection is used for described
It biases amplifying unit and negative-feedback is provided, improve the signal bandwidth of the biasing amplifying unit；
Second compensating unit one end is connect with the source electrode of the second transistor, and the other end is connect with power supply, is used for
Negative-feedback is provided to the biasing amplifying unit, improves the signal bandwidth of the biasing amplifying unit.
An embodiment of the present invention provides a kind of buffer amplifier circuits, including：Bias amplifying unit, the first compensating unit and the
Two compensating units；Wherein, first compensating unit and the second compensating unit are negative anti-by being provided for the biasing amplifying unit
Feedback has widened the signal bandwidth of the biasing amplifying unit so that the rising edge of the output signal of the amplifying circuit and decline
Along steepening, modulation of the transistor 1/f noise to the output signal of the amplifying circuit is reduced, to obtain improved output
Signal phase noiseproof feature.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a kind of buffer amplifier circuits, as shown in Fig. 2, including：Bias amplifying unit 100, the
One compensating unit 200 and the second compensating unit 300；Wherein,
The biasing amplifying unit 100 includes biasing resistor R3, the first transistor A1, second transistor A2；Described first
Transistor A1, second transistor A2 grid connect with one end of the biasing resistor R3, the signal as the amplifying circuit
The drain electrode of input terminal Vin1, the first transistor A1, second transistor A2 are connect with the other end of the biasing resistor R3, are made
For the signal output end O of the biasing amplifying unit 100, the source electrode of the first transistor A1 and first compensating unit
200 connections, the source electrode of the second transistor A2 are connect with second compensating unit 300, and input signal passes through the signal
Input terminal is transmitted to the grid of the first transistor A1 and second transistor A2, brilliant by the first transistor A1 and second
As the first signal via the signal output end O outputs of the biasing amplifying unit 100 after the A2 amplifications of body pipe；
Described first compensating unit, 200 one end is connect with the source electrode of the first transistor A1, the other end ground connection, for
The biasing amplifying unit 100 provides negative-feedback, improves the signal bandwidth of the biasing amplifying unit 100；
Described second compensating unit, 300 one end is connect with the source electrode of the second transistor A2, and the other end is connect with power supply,
For providing negative-feedback to the biasing amplifying unit 100, the signal bandwidth of the biasing amplifying unit 100 is improved.
It should be noted that the Substrate ground of the first transistor, the substrate of the second transistor is connect with power supply,
In order to indicate convenient, the substrate of the first transistor and second transistor is not shown in the drawing.
In the present embodiment, while purpose that first compensating unit, 200 and second compensating unit 300 is arranged is to protect
The signal amplitude for demonstrate,proving the biasing positive and negative semiaxis of 100 output signal of amplifying unit is consistent.
It should be noted first compensating unit, 200 and second compensating unit 300 to the biasing amplifying unit
100 provide negative-feedback, reduce the signal gain of the biasing amplifying unit 100；This is because under normal circumstances, an amplification
The gain bandwidth product of circuit is certain, the signal bandwidth of amplifying circuit can be improved by negative-feedback, but gain is then dropped therewith
It is low.It is illustrated in figure 3 amplifying circuit negative-feedback gain bandwidth change schematic diagram, horizontal axis is frequency axis ω, and the longitudinal axis is gain AV.From
Fig. 3 is it is found that the initial gain of an amplifying circuit is A0, signal bandwidth ω0, gain bandwidth product GBW；Introducing negative-feedback
When, feedback factor β, then the gain reduction of amplifying circuit is A0/(1+βA0), signal bandwidth is (1+ β A0)ω0, but gain
Bandwidth product remains as GBW.In the present invention, first compensating unit, 200 and second compensating unit 300 is opened up by providing negative-feedback
The wide signal bandwidth of the amplifying circuit so that the rising edge and failing edge steepening of the output signal of the amplifying circuit, drop
Low modulation of the transistor 1/f noise to the output signal of the amplifying circuit, to obtain improved phase of output signal
Noiseproof feature.
On the basis of the above embodiments, a preferred embodiment of the present invention provides a kind of first compensating unit
200 and second compensating unit 300 specific implementation form, as shown in figure 4, first compensating unit 200 include first resistor
R1 and the first capacitance C1, the first resistor R1 is in parallel with the first capacitance C1, the source electrode of one end and the first transistor A1
Connection, other end ground connection；Second compensating unit 300 includes second resistance R2 and the second capacitance C2, the second resistance R2
In parallel with the second capacitance C2, one end is connect with the source electrode of the second transistor A2, and the other end is connect with power supply.
It should be noted that the present invention whether may be used to the way of realization and resistance of the first resistor R1 and second resistance R2
Control variation does not limit, as long as the function of resistance can be realized, specifically depending on actual conditions.The present invention is to described
Whether controllable variations do not limit the way of realization and capacitance of one capacitance C1 and the second capacitance C2, as long as capacitance can be realized
Function, specifically depending on actual conditions.
It should also be noted that, in other embodiments of the invention, first compensating unit 200 can only include the
One resistance R1, second compensating unit 300 can only include second resistance R2, and the present invention is to first compensating unit 200
It is not limited with the specific implementation form of the second compensating unit 300, as long as can be described under the premise of meeting certain gain
Bias amplifying unit 100 and negative-feedback be provided, improve the signal bandwidth of the biasing amplifying unit, specifically regarding actual conditions and
It is fixed.
On the basis of the above embodiments, in one embodiment of the invention, the first transistor A1 increases for N-channel
Strong type field-effect tube, the second transistor A2 are P-channel enhancement type FET.The present invention to the first transistor A1 and
The concrete type of second transistor A2 does not limit, specifically depending on actual conditions.
On the basis of the above embodiments, in one particular embodiment of the present invention, the biasing amplifying unit 100 is gone back
Including compensating amplifying unit, as shown in figure 5, the compensation amplifying unit 400 includes：Third transistor A11 and the 4th transistor
A22, wherein
The third transistor A11, the 4th transistor A22 grid be connected to the signal input part of the amplifying circuit
The drain electrode of Vin1, the third transistor A11, the 4th transistor A22 are connected to the signal output end of the biasing amplifying unit 100
O, the third transistor A11 are N-channel enhancement mode FET, source electrode and Substrate ground, and the 4th transistor A22 is
P-channel enhancement type FET, source electrode and substrate are connect with power supply；
Input signal is transmitted to the grid of the third transistor A11 and the 4th transistor A22 by the signal input part
Pole, by being used as second signal after the third transistor A11 and the 4th transistor A22 amplifications, the second signal with it is described
First Signal averaging forms signal output end O output of second composite signal by the biasing amplifying unit 100, described in raising
The signal gain of amplifying circuit.
It should be noted that the biasing resistor R3 is biased in and puts by the first transistor A1 and second transistor A2
While big state, the third transistor A11 and the 4th transistor A22 are also biased in magnifying state.
It should also be noted that, since the first compensating unit 200 and the second compensating unit 300 are to the biasing amplifying unit
100 provide negative-feedback, reduce the signal gain of the biasing amplifying unit 100, in order to prevent the biasing amplifying unit 100
The amplitude of first signal of output is too small, therefore introduces compensation amplifying circuit 400, is ensureing the biasing amplifying unit
The amplitude of output signal is improved on the basis of first signal of 100 outputs.
On the basis of the above embodiments, in another specific embodiment of the present invention, the amplifying circuit further includes
First reverse phase amplifying unit, the signal input part of the first reverse phase amplifying unit are connected to the letter of the biasing amplifying unit 100
Number output end O carries out reverse phase amplification for the output signal to the biasing amplifying unit 100, and passes through first reverse phase
The signal output end of amplifying unit exports third signal.
It should be noted that when the output signal of the biasing amplifying unit 100 does not include the second signal, it is described
First reverse phase amplifying unit is used to carry out reverse phase amplification to first signal, and passes through the letter of the first reverse phase amplifying unit
Number output end exports third signal；When the output signal of the biasing amplifying unit 100 includes the second signal, described the
One reverse phase amplifying unit is used to carry out reverse phase amplification to second composite signal, and passes through the first reverse phase amplifying unit
Signal output end exports third signal.
On the basis of the above embodiments, in another specific embodiment of the present invention, the amplifying circuit further includes
Second reverse phase amplifying unit, the signal input part of the second reverse phase amplifying unit are connected to the letter of the first reverse phase amplifying unit
Number output end, for carrying out reverse phase amplification to the third signal and passing through the signal output end of the second reverse phase amplifying unit
Export fourth signal.
On the basis of the above embodiments, another specific embodiment of the invention provides one kind first reverse phase and puts
The specific implementation form of big unit and the second reverse phase amplifying unit, as shown in fig. 6, the first reverse phase amplifying unit 500 includes
5th transistor A3 and the 6th transistor A4；Wherein,
The 5th transistor A3, the 6th transistor A4 grid be connected to it is described biasing amplifying unit 100 signal output
O is held, as the signal input part of the first reverse phase amplifying unit 500, the leakage of the 5th the transistor A3, the 6th transistor A4
Pole connects, and as the signal output end of the first reverse phase amplifying unit 500, the 5th transistor A3 is that N-channel is enhanced
Field-effect tube, source electrode and Substrate ground, the 6th transistor A4 are P-channel enhancement type FET, source electrode and substrate
It is connected to DC power supply, the output signal of the biasing amplifying unit 100 is defeated by the signal of the first reverse phase amplifying unit 500
Enter the grid that end is transmitted to the 5th the transistor A3 and the 6th transistor A4, by the 5th transistor A3 and the 6th crystal
Third signal is exported by the signal output end of the first reverse phase amplifying unit 500 after the reverse phase amplification of pipe A4.
Likewise, the output signal of the biasing amplifying unit 100 is the first signal or the second composite signal.
The second reverse phase amplifying unit 600 includes：7th transistor A5 and the 8th transistor A6；Wherein,
The 7th transistor A5, the 8th transistor A6 grid be connected to the signal of the first reverse phase amplifying unit 500
Output end, as the signal input part of the second reverse phase amplifying unit 600, the 7th transistor A5, the 8th transistor A6
Drain electrode connection, be N ditches as the signal output end Vout of the second reverse phase amplifying unit 600, the 7th transistor A5
The enhanced field-effect tube in road, source electrode and Substrate ground, the 8th transistor A6 are P-channel enhancement type FET, source
Pole and substrate are connected to DC power supply, and the third signal is transmitted by the signal input part of the second reverse phase amplifying unit 600
To the grid of the 7th the transistor A5 and the 8th transistor A6, by the anti-of the 7th transistor A5 and the 8th transistor A6
After mutually amplifying, fourth signal is exported by the signal output end Vout of the second reverse phase amplifying unit 600.
Wherein Cd represents capacitance, the CL for amplifying circuit institute band load.
It should be noted that when the output signal of the biasing amplifying unit 100 is low level, the 6th transistor
A4 is connected, and the first reverse phase amplifying unit 500 exports high level to the second reverse phase amplifying unit 600, at this point, described the
Seven transistor A5 conductings, the second reverse phase amplifying unit 600 export low level.When the output of the biasing amplifying unit 100
When signal is high level, the 5th transistor A3 conductings, the first reverse phase amplifying unit 500 amplifies to second reverse phase
Unit 600 exports low level, and the 8th transistor A6 conductings, the second reverse phase amplifying unit 600 export high level at this time,
Realize the reverse phase of signal.
It should also be noted that, the first reverse phase amplifying unit 500 and the second reverse phase amplifying unit 600 are in the present embodiment
In main function be to promote the carrying load ability of the amplifying circuit.When the first reverse phase amplifying unit 500 or second is anti-
Phase amplifying unit 600 P-channel enhancement type FET conducting when, power supply by open P-channel enhancement type FET to
Successive load charges, it is clear that and the size of P-channel enhancement type FET is bigger, and the speed to charge to successive load is faster,
Carrying load ability is stronger.Similarly, the size of N-channel enhancement mode FET determines the speed that the charge in load is put into ground
Degree, size is bigger, and the speed that the charge in load is put into ground is faster.In general, it is single to constitute the first reverse phase amplification
The size of the transistor of member 500 or the second reverse phase amplifying unit 600 is bigger, and the carrying load ability of the amplifying circuit is stronger,
But the size for constituting the transistor of the first reverse phase amplifying unit 500 or the second reverse phase amplifying unit 600 is bigger, prime electricity
The load on road is bigger, it is therefore desirable to using multistage reverse phase amplifying unit, expand the carrying load ability of the amplifying circuit step by step,
Two-stage reverse phase amplifying unit, the carrying load ability for expanding the amplifying circuit, but the present invention are used in the present embodiment
The series of the reverse phase amplifying unit is not limited, specifically depending on actual conditions, likewise, the present invention is to the reverse phase
The concrete composition structure of amplifying unit does not limit, specifically depending on actual conditions.
Based on any of the above embodiments, in the particular preferred embodiment of the present invention, the amplifying circuit
Further include：Capacitance；
Signal input part Vin1 of the one end of the capacitance as the amplifying circuit, it is another to be terminated at described first
The connecting node of the grid and the biasing resistor R3 of transistor A1, second transistor A2 is used for the direct current of blocked input signal
Influence of the level to the amplifying circuit.
The embodiment of the present invention uses slow by taking the buffer amplifier circuit that the embodiment of the present invention is provided as an example with the prior art
The noiseproof feature for rushing amplifier is compared.
Contrast experiment 1：Pass through the input terminal Vin and the embodiment of the present invention of the buffer amplifier in background technology respectively
In the amplifying circuit input terminal Vin1 input frequency be 40MHz, the sinusoidal signal that amplitude is 100mV, the buffering puts
Big device is identical with DC power supply used by the amplifying circuit, the parameter of the first transistor M1 of the buffer amplifier and institute
The parameter for stating the first transistor A1 of amplifying circuit is identical, and the parameter of the second transistor M2 of the buffer amplifier is put with described
The parameter of the second transistor A2 of big circuit is identical, the parameter phase of the load capacitance of the buffer amplifier and the amplifying circuit
Together.It is as shown in Figure 7 by the comparison for testing the phase noise performance of the buffer amplifier and the amplifying circuit that obtain.Figure
Curve 11 in 7 is the phase noise curve of the buffer amplifier output signal, and curve 12 is amplifying circuit output letter
Number phase noise curve, can be obtained from Fig. 7, the phase noise performance of the amplifying circuit is substantially better than the buffer amplifier
Noiseproof feature：At frequency deviation Δ f (=1Hz), the output of the noise buffer amplifier of the amplifying circuit output is made an uproar
The low about 0.97dB of sound；At frequency deviation Δ f (=100Hz), the phase noise buffer amplifier of the amplifying circuit output
Output the low about 1.50dB of phase noise；At frequency deviation Δ f (=10MHz), the phase noise of amplifying circuit output compared with
The low about 2.80dB of phase noise of the output of the buffer amplifier.And as can be known from Fig. 7, at frequency deviation Δ f (=100Hz)
The phase noise value of place, the buffer amplifier and the amplifying circuit is below -145dBc/Hz, makes an uproar in phase low in this way
In the case of sound, the phase noise of the amplifying circuit optimizes 1.50dB again；At frequency deviation Δ f (=10MHz), the buffering is put
The phase noise value of big device and the amplifying circuit is below -150dBc/Hz, described under phase-noise case low in this way
The phase noise of amplifying circuit optimizes 2.80dB again.
Contrast experiment 2：Pass through the input terminal Vin and the embodiment of the present invention of the buffer amplifier in background technology respectively
In the amplifying circuit input terminal Vin1 input frequency be 40MHz, the sinusoidal signal that amplitude is 300mV, the buffering puts
Big device is identical with DC power supply used by the amplifying circuit, the parameter of the first transistor M1 of the buffer amplifier and institute
The parameter for stating the first transistor A1 of amplifying circuit is identical, and the parameter of the second transistor M2 of the buffer amplifier is put with described
The parameter of the second transistor A2 of big circuit is identical, the parameter phase of the load capacitance of the buffer amplifier and the amplifying circuit
Together.It is as shown in Figure 8 by the comparison for testing the phase noise performance of the buffer amplifier and the amplifying circuit that obtain.Figure
Curve 13 in 8 is the phase noise curve of the buffer amplifier output signal, and curve 14 is amplifying circuit output letter
Number phase noise curve, can be obtained from Fig. 8, the phase noise performance of the amplifying circuit is substantially better than the buffer amplifier
Noiseproof feature.At frequency deviation Δ f (=1Hz), the output of the phase noise buffer amplifier of the amplifying circuit output
The low about 1.95dB of phase noise；At frequency deviation Δ f (=100Hz), the phase noise of the amplifying circuit output is more described slow
Rush the low about 2.03dB of phase noise of the output of amplifier；At frequency deviation Δ f (=10MHz), the phase of the amplifying circuit output
The low about 3.40dB of phase noise of the output of the position noise buffer amplifier.And as can be known from Fig. 8, frequency deviation Δ f (=
The phase noise value of 100Hz) place, the buffer amplifier and the amplifying circuit is below -145dBc/Hz, low in this way
Under phase-noise case, the phase noise of the amplifying circuit optimizes 2.03dB again；It is described at frequency deviation Δ f (=10MHz)
The phase noise value of buffer amplifier and the amplifying circuit is below -155dBc/Hz, in phase-noise case low in this way
Under, the phase noise of the amplifying circuit optimizes 3.40dB again.
Contrast experiment 3：Pass through the input terminal Vin and the embodiment of the present invention of the buffer amplifier in background technology respectively
In the amplifying circuit input terminal Vin1 input frequency be 40MHz, the sinusoidal signal that amplitude is 500mV, the buffering puts
Big device is identical with DC power supply used by the amplifying circuit, the parameter of the first transistor M1 of the buffer amplifier and institute
The parameter for stating the first transistor A1 of amplifying circuit is identical, and the parameter of the second transistor M2 of the buffer amplifier is put with described
The parameter of the second transistor A2 of big circuit is identical, the parameter phase of the load capacitance of the buffer amplifier and the amplifying circuit
Together.It is as shown in Figure 9 by the comparison for testing the phase noise performance of the buffer amplifier and the amplifying circuit that obtain.Figure
Curve 15 in 9 is the phase noise curve of the buffer amplifier output signal, and curve 16 is amplifying circuit output letter
Number phase noise curve, can be obtained from Fig. 9, the phase noise performance of the amplifying circuit is substantially better than the buffer amplifier
Noiseproof feature.At frequency deviation Δ f (=1Hz), the output of the phase noise buffer amplifier of the amplifying circuit output
The low about 1.82dB of phase noise；At frequency deviation Δ f (=100Hz), the phase noise of the amplifying circuit output is more described slow
Rush the low about 1.87dB of phase noise of the output of amplifier；At frequency deviation Δ f (=10MHz), the phase of the amplifying circuit output
The low about 3.62dB of phase noise of the output of the position noise buffer amplifier.And as can be known from Fig. 9, frequency deviation Δ f (=
The phase noise value of 100Hz) place, the buffer amplifier and the amplifying circuit is below -145dBc/Hz, low in this way
Under phase-noise case, the phase noise of the amplifying circuit optimizes again compared to the phase noise of the buffer amplifier
1.87dB；At frequency deviation Δ f (=10MHz), the phase noise value of the buffer amplifier and the amplifying circuit below-
160dBc/Hz, under phase-noise case low in this way, the phase noise of the amplifying circuit is compared to the buffer amplifier
Phase noise optimize 3.62dB again.
Can be seen that the amplifying circuit that the embodiment of the present invention is provided by above three contrast experiment has more preferably
Phase noise performance.
The embodiment of the present invention also compares the power consumption parameter of the amplifying circuit and the buffer amplifier：
Respectively by putting described in the input terminal Vin and the embodiment of the present invention of the buffer amplifier in background technology
The input terminal Vin1 input frequencies of big circuit are 40MHz, the sinusoidal signal that amplitude is 500mV, the buffer amplifier and described
DC power supply used by amplifying circuit is identical, parameter and the amplifying circuit of the first transistor M1 of the buffer amplifier
The first transistor A1 parameter it is identical, the of the parameter of the second transistor M2 of the buffer amplifier and the amplifying circuit
The parameter of two-transistor A2 is identical, and the buffer amplifier is identical with the parameter of the load capacitance of the amplifying circuit.Pass through reality
It tests the buffer amplifier of acquisition and current curve that the amplifying circuit consumes within the same period is as shown in Figure 10.Figure
Curve 17 in 10 is the current curve that the buffer amplifier consumes within the period, and curve 18 is that the amplifying circuit exists
The current curve consumed in the period, as can be seen from Figure 10, the electric current that the amplifying circuit is consumed are significantly lower than the buffering
The electric current that amplifier is consumed.By the average value of calculating current it is found that the average current that the buffer amplifier is consumed is
4.908mA, and the average current that the amplifying circuit is consumed is 4.116mA, the amplification that the embodiment of the present invention is provided
The lower power consumption of the power consumption buffer amplifier of circuit is more than 16%, can be obtained by this experiment, the embodiment of the present invention
The amplifying circuit provided not only has good phase noise performance, but also power consumption is relatively low.
In conclusion an embodiment of the present invention provides a kind of buffer amplifier circuits, including：Bias amplifying unit 100, first
Compensating unit 200 and the second compensating unit 300；Wherein, first compensating unit, 200 and second compensating unit 300 by for
The biasing amplifying unit 100 provides negative-feedback, has widened the signal bandwidth of the biasing amplifying unit 100 so that described to put
The rising edge and failing edge steepening of the output signal of big circuit, reduce output of the transistor 1/f noise to the amplifying circuit
The modulation of signal, to obtain improved phase of output signal noiseproof feature.At the same time, it is found by Experimental comparison, this
The power consumption for the amplifying circuit that inventive embodiments are provided is relatively low.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (8)
1. a kind of buffer amplifier circuit, which is characterized in that including：It is single to bias amplifying unit, the first compensating unit and the second compensation
Member；Wherein,
The biasing amplifying unit includes biasing resistor, the first transistor, second transistor；The first transistor, the second crystalline substance
The grid of body pipe is connect with one end of the biasing resistor, as the signal input part of the amplifying circuit, the first crystal
The drain electrode of pipe, second transistor is connect with the other end of the biasing resistor, the signal output as the biasing amplifying unit
End, the source electrode of the first transistor are connect with first compensating unit, the source electrode of the second transistor and described second
Compensating unit connects, and input signal is transmitted to the first transistor and the second crystalline substance by the signal input part of the amplifying circuit
The grid of body pipe amplifies list by being used as the first signal after the first transistor and second transistor amplification via the biasing
The signal output end output of member；
First compensating unit one end is connect with the source electrode of the first transistor, and other end ground connection is used for the biasing
Amplifying unit provides negative-feedback, improves the signal bandwidth of the biasing amplifying unit；
Second compensating unit one end is connect with the source electrode of the second transistor, and the other end is connect with power supply, is used for institute
It states biasing amplifying unit and negative-feedback is provided, improve the signal bandwidth of the biasing amplifying unit；
First compensating unit includes first resistor and the first capacitance, and the first resistor is in parallel with the first capacitance, one end
It is connect with the source electrode of the first transistor, other end ground connection；
Second compensating unit includes second resistance and the second capacitance, and the second resistance is in parallel with the second capacitance, one end
It is connect with the source electrode of the second transistor, the other end is connect with power supply.
2. amplifying circuit according to claim 1, which is characterized in that the biasing amplifying unit further includes that compensation amplification is single
Member, the compensation amplifying unit include：Third transistor and the 4th transistor；Wherein,
The third transistor, the 4th transistor grid be connected to the signal input part of the amplifying circuit, the third crystal
The drain electrode of pipe, the 4th transistor is connected to the signal output end of the biasing amplifying unit, and the third transistor enhances for N-channel
Type field-effect tube, source electrode and Substrate ground, the 4th transistor are P-channel enhancement type FET, source electrode and substrate
It is connect with power supply；
Input signal is transmitted to the grid of the third transistor and the 4th transistor by the signal input part of the amplifying circuit
Pole, by being used as second signal after the third transistor and the amplification of the 4th transistor, the second signal is believed with described first
Number superposition composition the second composite signal by it is described biasing amplifying unit signal output end export, to improve the amplifying circuit
Signal gain.
3. according to claim 1-2 any one of them amplifying circuits, which is characterized in that the amplifying circuit further includes first anti-
Phase amplifying unit, the signal input part of the first reverse phase amplifying unit are connected to the signal output end of the biasing amplifying unit,
Reverse phase amplification is carried out for the output signal to the biasing amplifying unit, and passes through the signal of the first reverse phase amplifying unit
Output end exports third signal.
4. amplifying circuit according to claim 3, which is characterized in that the first reverse phase amplifying unit includes the 5th crystal
Pipe and the 6th transistor；Wherein,
5th transistor, the 6th transistor grid be connected to it is described biasing amplifying unit signal output end, as described
The signal input part of first reverse phase amplifying unit, the drain electrode connection of the 5th transistor, the 6th transistor, as described first
The signal output end of reverse phase amplifying unit, the 5th transistor are N-channel enhancement mode FET, and source electrode and substrate connect
Ground, the 6th transistor are P-channel enhancement type FET, and source electrode and substrate are connected to DC power supply, the biasing amplification
The output signal of unit is transmitted to the 5th transistor and the 6th by the signal input part of the first reverse phase amplifying unit
The grid of transistor, by the first reverse phase amplifying unit after the amplification of the reverse phase of the 5th transistor and the 6th transistor
Signal output end export third signal.
5. amplifying circuit according to claim 3, which is characterized in that the amplifying circuit further includes that the amplification of the second reverse phase is single
Member, the signal input part of the second reverse phase amplifying unit are connected to the signal output end of the first reverse phase amplifying unit, are used for
Reverse phase amplification is carried out to the third signal and fourth signal is exported by the signal output end of the second reverse phase amplifying unit.
6. amplifying circuit according to claim 5, which is characterized in that the second reverse phase amplifying unit includes：7th is brilliant
Body pipe and the 8th transistor；Wherein,
7th transistor, the 8th transistor grid be connected to the signal output end of the first reverse phase amplifying unit, as
The signal input part of the second reverse phase amplifying unit, the drain electrode connection of the 7th transistor, the 8th transistor, as described
The signal output end of second reverse phase amplifying unit, the 7th transistor are N-channel enhancement mode FET, source electrode and substrate
Ground connection, the 8th transistor are P-channel enhancement type FET, and source electrode and substrate are connected to DC power supply, the third letter
The grid of the 7th transistor and the 8th transistor number is transmitted to by the signal input part of the second reverse phase amplifying unit,
By the signal output end of the second reverse phase amplifying unit after the amplification of the reverse phase of the 7th transistor and the 8th transistor
Export fourth signal.
7. according to claim 1-2 or 4-6 any one of them amplifying circuit, which is characterized in that the amplifying circuit further includes：
Capacitance；
Signal input part of the one end of the capacitance as the amplifying circuit, it is another be terminated at the first transistor,
The connecting node of the grid of second transistor and the biasing resistor, the DC level for blocked input signal is to the amplification
The influence of circuit.
8. amplifying circuit according to claim 1, which is characterized in that the first transistor is the enhanced field effect of N-channel
Ying Guan, the second transistor are P-channel enhancement type FET.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093956A (en) * | 2007-07-20 | 2007-12-26 | 开源集成电路(苏州)有限公司 | Under voltage locking circuit with temperature compensation |
| CN101252341A (en) * | 2008-03-11 | 2008-08-27 | 东南大学 | Wideband low noise amplifier |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093956A (en) * | 2007-07-20 | 2007-12-26 | 开源集成电路(苏州)有限公司 | Under voltage locking circuit with temperature compensation |
| CN101252341A (en) * | 2008-03-11 | 2008-08-27 | 东南大学 | Wideband low noise amplifier |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
Non-Patent Citations (1)
| Title |
|---|
| 全CMOS温度补偿的参考电压电流源;赵喆 等;《微处理机》;20131130(第5期);第1-9页 * |
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