CN105374864A - Insulated gate bipolar transistor and method of manufacturing the same - Google Patents
Insulated gate bipolar transistor and method of manufacturing the same Download PDFInfo
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- CN105374864A CN105374864A CN201410527310.9A CN201410527310A CN105374864A CN 105374864 A CN105374864 A CN 105374864A CN 201410527310 A CN201410527310 A CN 201410527310A CN 105374864 A CN105374864 A CN 105374864A
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Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
An embodiment of the present invention provides an insulated gate bipolar transistor and a method for manufacturing the same, the insulated gate bipolar transistor including: a collector electrode; a collector layer; a first conductivity type drift layer provided on the collector layer; a first emitter layer; a trench extending from a surface of the first emitter layer into the drift layer of the first conductivity type, wherein the trench has a first side and a second side opposite to each other; the grid electrode is filled in the groove and extends to the surface of the first emitter layer, wherein the extending distances of the grid electrodes on the first side and the second side on the surface of the first emitter layer are different; a gate dielectric layer; a second emitter region; an interlayer dielectric layer; and an emitter electrode.
Description
Technical field
The embodiment of the present invention relates to semiconductor technology, and relates to Insulated Gate Bipolar transistor and manufacture method thereof especially.
Background technology
Power component is widely used in for driving and controlling high-power electrical article and vehicular applications etc.This power component comprises the power transistor of the large output carrying out switching manipulation.This kind of power transistor, except power metal oxide semiconductor field-effect transistor (MOSFET), Power bipolar transistor, also comprise Insulated Gate Bipolar transistor (insulatedgatebipolartransistor, IGBT).Insulated Gate Bipolar transistor has the high input impedance of mos field effect transistor and the low on-resistance of bipolar transistor concurrently.
Summary of the invention
The embodiment of the present invention provides a kind of Insulated Gate Bipolar transistor, can reduce the current density of Insulated Gate Bipolar transistor and closedown loss.
The Insulated Gate Bipolar transistor that one embodiment of the invention provides, comprising: collector electrode; Collector layer, electrical connection collector electrode, and there is the second conductivity type; First conductivity type drift layer, be located on collector layer, wherein the first conductivity type is different from the second conductivity type; First emitter layer, is located in the first conductivity type drift layer, and has the second conductivity type; Groove (trench), extends into from the surface of the first emitter layer in the first conductivity type drift layer, and wherein groove has the first relative side and the second side; Gate electrode, to insert in groove and to extend on the surface of the first emitter layer, wherein different at the extended distance of gate electrode on the surface of the first emitter layer of the first side and the second side; Gate dielectric, is located between gate electrode and groove and between gate electrode and the first emitter layer; Second emitter region, be located in the first emitter layer of gate electrode both sides, wherein the second emitter region has the first conductivity type; Interlayer dielectric layer, is located on the first emitter layer; And emitter-base bandgap grading electrode, be electrically connected with the first emitter layer and the second emitter region, wherein interlayer dielectric layer is located between gate electrode and emitter-base bandgap grading electrode.
One embodiment of the invention provides a kind of manufacture method of Insulated Gate Bipolar transistor, comprising: provide substrate, has the first conductivity type, and has upper surface and lower surface; Form the first emitter region, there is the second conductivity type, and extend in substrate from the upper surface of substrate, and the second conductivity type is different from the first conductivity type; Form groove (trench), extend from the upper surface of substrate and pass through the first emitter region in substrate, wherein groove has the first relative side and the second side; Form grid structure, comprise gate dielectric and gate electrode, wherein gate electrode to be inserted in groove and is extended on the upper surface of substrate, the extended distance of gate electrode wherein in the first side and the second side on the upper surface of substrate is different, and gate dielectric is located between gate electrode and groove and between gate electrode and the first emitter region; Form the second emitter region in the first emitter region of gate electrode both sides, wherein the second emitter region has the first conductivity type; Form interlayer dielectric layer on gate electrode; Form emitter-base bandgap grading electrode, emitter-base bandgap grading electrode is electrically connected with the first emitter region, the second emitter region, and interlayer dielectric layer is located between gate electrode and emitter-base bandgap grading electrode; Form collector region, have the second conductivity type, and extend in substrate from the lower surface of substrate, wherein substrate is not formed with the first emitter region, the part of the second emitter region and collector region is as the first conductivity type drift region; And form collector electrode, collector electrode electrical connection collector region.
The embodiment of the present invention provides again a kind of manufacture method of Insulated Gate Bipolar transistor, comprising: provide substrate, has the second conductivity type, and wherein substrate is as collector region; Form epitaxial loayer on substrate, epitaxial loayer has the first conductivity type, and the first conductivity type is different from the second conductivity type; Form the first emitter region, extend in epitaxial loayer from the surface of epitaxial loayer, and there is the second conductivity type; Form groove (trench), extend from the surface of the first emitter region and pass through the first emitter region in epitaxial loayer, wherein groove has the first relative side and the second side; Form grid structure, comprise gate dielectric and gate electrode, wherein gate electrode to be inserted in groove and is extended to the surface of the first emitter region, the extended distance of gate electrode wherein in the first side and the second side on the surface of the first emitter region is different, and gate dielectric is located between gate electrode and groove and between gate electrode and the first emitter region; Form the second emitter region in the first emitter region of gate electrode both sides, wherein the second emitter region has the first conductivity type, and the part that its epitaxial layers is not formed with the first emitter region and the second emitter region is as the first conductivity type drift region; Form interlayer dielectric layer on gate electrode; Form emitter-base bandgap grading electrode, emitter-base bandgap grading electrode is electrically connected with the first emitter region, the second emitter region, and interlayer dielectric layer is located between gate electrode and emitter-base bandgap grading electrode; And form collector electrode, collector electrode electrical connection collector region.
For feature of the present invention and advantage can be become apparent, cited below particularly go out preferred embodiment, and coordinate appended diagram, be described in detail below.
Accompanying drawing explanation
Fig. 1-8 is the profiles in Insulated Gate Bipolar transistor each stage in its manufacture method of the embodiment of the present invention;
Fig. 9 is the profile of the Insulated Gate Bipolar transistor of another embodiment of the present invention;
Figure 10 is current density and the voltage analysis figure of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example;
Figure 11 is the partial enlarged drawing of Figure 10;
Figure 12 is ESD protection area and the conducting voltage analysis chart of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example;
Figure 13 is the switch performance analysis chart of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example;
Figure 14 is the partial enlarged drawing of Figure 13;
Figure 15 is the analysis of electric field figure of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example; And
Figure 16 is the puncture voltage analysis chart of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example.
Symbol description:
100 substrates; 100A upper surface;
100B lower surface; 110 first emitter-base bandgap grading zones/layers;
120 grooves; S1 first side;
S2 second side; 130 grid structures;
The horizontal grid part of 130P; 130V vertical gate part;
140 dielectric materials layers; 150 conductive layers;
160 gate dielectrics; 170 gate electrodes;
180 second emitter regions; 190 interlayer dielectric layers;
200 contact openings; 210 the 3rd emitter regions;
220 emitter-base bandgap grading electrodes; 230 collector fates;
240 predetermined drift regions; 250 heavy doping resilient coatings;
260 collector zones/layers;
255/270 first conductivity type drift zones/layers;
280 collector electrodes;
300 Insulated Gate Bipolar transistors;
T1 thickness; T2 thickness;
T3 thickness; W1 width;
W2 width; W3 width;
W4 width; W5 width.
Embodiment
Insulated Gate Bipolar transistor below for the embodiment of the present invention elaborates.Describing it is to be understood that provides many different embodiments or example, in order to implement different pattern of the present invention.The specific element of the following stated and arrangement mode are only and simply describe the present invention.Certainly, these are only in order to illustrate but not restriction of the present invention.In addition, label or the sign of repetition may be used in different embodiments.These repeat only clearly to describe the present invention in order to simple, do not represent between discussed different embodiment and/or structure and have any relevance.Moreover, when address one first material layer to be positioned on one second material layer or on time, comprise the situation that the first material layer directly contacts with the second material layer.Or, be also separated with the situation of other material layer one or more between possibility, in this case, may not directly contact between the first material layer with the second material layer.
Must it is to be understood that to describe or illustrated element can exist by the various forms known by these those skilled in the art for special.In addition, when certain layer other layer or substrate " on " time, likely refer to that " directly " is on other layer or substrate, or refer to that certain layer is on other layer or substrate, or refer to other layer of sandwiched between other layer or substrate.
In addition, in embodiment, relative term may be used, such as " lower " or " bottom " and " higher " or " top ", to describe the relativeness of an illustrated element for another element.Accessible, if make it turn upside down the upset of illustrated device, then be described in " lower " side element will become element in " higher " side.
At this, the term of " about ", " approximately " in certain embodiments ordinary representation, within 20% or other numerical value of a set-point or scope, is preferably within 10%, and better be within 5%.Be about quantity in this given quantity, meaning, namely when not having certain illustrated, still can imply the implication of " about ", " approximately ".
The embodiment of the present invention can utilize an asymmetric gate structure to reduce the current density (currentdensity) of this Insulated Gate Bipolar transistor and close loss (turn-offloss) and maintain its conducting voltage (turnonvoltage) simultaneously.
See Fig. 1, first provide a substrate 100.This substrate 100 can comprise: the silicon of mono-crystalline structures, polycrystalline structure or non crystalline structure or the elemental semiconductor of germanium; The compound semiconductors such as gallium nitride (GaN), carborundum (siliconcarbide), GaAs (galliumarsenic), gallium phosphide (galliumphosphide), indium phosphide (indiumphosphide), indium arsenide (indiumarsenide) or indium antimonide (indiumantimonide); The alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP or other material be applicable to and/or combinations thereof.This substrate 100 has the first conductivity type.Such as, when the first conductivity type is N-type, this substrate 100 can be lightly doped n-type substrate.In addition, substrate 100 has upper surface 100A and lower surface 100B.
Then, in substrate 100, form the first emitter region 110 (being also called the first emitter layer 110).This first emitter region 110 extends in substrate 100 from the portion of upper surface 100A (also can be described as the surperficial 100A of the first emitter layer 110) of substrate 100, as shown in Figure 1, first emitter region 110 only extends into the partial depth of substrate 100, that is the thickness T1 of this first emitter region 110 is less than the thickness T2 of substrate 100.This first emitter region 110 has the second conductivity type, and this second conductivity type is different from the first conductivity type.This first emitter region 110 is formed by ion implantation step, such as, in one embodiment, when this second conductivity type is P type, can inject boron ion, indium ion or boron difluoride ion (BF in the region of this first emitter region 110 of predetermined formation
2 +).
Then, see Fig. 2, groove (trench) 120 is formed.This groove 120 from the upper surface 100A of substrate 100 extend pass through the first emitter region 110 and to enter in substrate 100 (that is to extend in the first follow-up conductivity type drift layer or hereinafter another embodiment epitaxial loayer in), and this groove 120 has the first relative side S1 and the second side S2.
Then see Fig. 3 and Fig. 4, grid structure 130 is formed.In certain embodiments, this grid structure 130 can be formed by following steps.First, see Fig. 3, compliance forms a dielectric materials layer 140 on the sidewall of groove 120 and the upper surface 100A of bottom and substrate 100.Then, the blanket property covered deposits a conductive layer 150 on dielectric materials layer 140 and inserts in groove 120.Afterwards, as shown in Figure 4, with photoetching and etching step patterned dielectric material layer 140 and conductive layer 150 to form gate dielectric 160 and gate electrode 170 respectively and to complete grid structure 130.Easy speech it, this grid structure 130 comprises gate dielectric 160 and gate electrode 170.
Above-mentioned dielectric materials layer 140 (in order to form gate dielectric 160) can be silica, silicon nitride, silicon oxynitride, high-k (high-k) dielectric material or other any applicable dielectric material or above-mentioned combination.This high-k dielectric materials can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, the nitrogen oxide of metal, metal aluminate, zirconium silicate, zircoaluminate.Such as, this high-k (high-k) dielectric material can be LaO, AlO, ZrO, TiO, Ta
2o
5, Y
2o
3, SrTiO
3(STO), BaTiO
3(BTO), BaZrO, HfO
2, HfO
3, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr) TiO
3(BST), Al
2o
3, other high-k dielectric materials of other suitable material or combinations thereof.This dielectric materials layer 140 is formed by chemical vapour deposition technique (CVD) or method of spin coating, this chemical vapour deposition technique such as can be Low Pressure Chemical Vapor Deposition (lowpressurechemicalvapordeposition, LPCVD), low temperature chemical vapor deposition method (lowtemperaturechemicalvapordeposition, LTCVD), be rapidly heated chemical vapour deposition technique (rapidthermalchemicalvapordeposition, RTCVD), plasma-assisted chemical vapour deposition method (plasmaenhancedchemicalvapordeposition, PECVD), atomic layer deposition method (the atomiclayerdeposition of atomic layer chemical vapor deposition method, or other conventional method ALD).
The material (that is material of gate electrode 170) of aforesaid conductive layer 150 can be amorphous silicon, polysilicon or above-mentioned combination.The material of this conductive layer 150 is formed by aforesaid chemical vapour deposition technique (CVD) or other any applicable depositional mode, such as, in one embodiment, available Low Pressure Chemical Vapor Deposition (LPCVD) deposits and obtained amorphous silicon conductive material layer or polysilicon conducting layers 150 between 525 ~ 650 DEG C, and its thickness range can be about
extremely about
In addition, the top of gate electrode 170 also can comprise a metal silicide layer (not illustrating), and this metal silicide can include but not limited to nickle silicide (nickelsilicide), cobalt silicide (cobaltsilicide), tungsten silicide (tungstensilicide), titanium silicide (titaniumsilicide), tantalum silicide (tantalumsilicide), platinum silicide (platinumsilicide) and silication erbium (erbiumsilicide).
As shown in Figure 4, this grid structure 130 comprises the horizontal grid part 130P be located at outside the groove 120 and vertical gate part 130V be located in groove 120, as shown in Figure 4.The mode being the central authorities departing from grid structure 130 due to vertical gate part 130V is arranged, therefore the axis of the horizontal grid part 130P of axis misalignment of this vertical gate part 130V, so grid structure 130 also can be described as asymmetric gate structure 130.
Continue see Fig. 4, gate dielectric 160 directly contacts the first emitter region 110 and substrate 100, and extends on the upper surface 100A of substrate 100, and gate electrode 170 is located on gate dielectric 160 and insert groove 120.This gate dielectric 160 makes gate electrode 170 and the first emitter region 110, the second emitter region of substrate 100 and follow-up formation is electrically insulated.Easy speech it, in grid structure 130, this gate electrode 170 to be inserted in groove 120 and is extended to the upper surface 100A (that is extending on the surface of the first emitter-base bandgap grading zones/layers 110) of substrate 100, and different at the extended distance of gate electrode 170 on the upper surface 100A of substrate 100 (or first emitter-base bandgap grading zones/layers 110) of the first side S1 and the second side S2.And gate dielectric 160 is located between gate electrode 170 and groove 120 and between gate electrode 170 and the first emitter region 110.
The horizontal grid part 130P of asymmetric gate structure 130 can extend the channel region of the final Insulated Gate Bipolar transistor formed, to reduce the current density of device and to close loss, such as, the current density of about 20% can be reduced, and make the shut-in time be down to 295ns by 435ns.
On the other hand, in this asymmetric gate structure 130, when this vertical gate part 130V more departs from the central authorities of gate electrode 170, namely represent it more close to follow-up the second emitter region being formed at gate electrode 170 both sides.And while reducing current density with horizontal grid part 130P and close loss, if this vertical gate part 130V is more close to the second emitter region, then the recruitment of the conducting voltage of the final Insulated Gate Bipolar transistor formed is lower.In certain embodiments, if the vertical gate part 130V of this grid structure 130 directly contacts the second emitter region, then the recruitment of the conducting voltage of Insulated Gate Bipolar transistor is almost 0, that is its conducting voltage raises hardly.Therefore, the vertical gate part 130V of asymmetric gate structure 130 can maintain the conducting voltage of the final Insulated Gate Bipolar transistor formed, and makes it can not raise too much, or even can not raise.
Therefore, the asymmetric gate structure 130 of this case is owing to having horizontal grid part 130P and vertical gate part 130V simultaneously, therefore it can reduce closedown loss and reduce current density, and simultaneously do not affect conducting voltage, to solve in existing Insulated Gate Bipolar transistor conducting voltage and current density or close the problem between loss with substitute for (trade-off).
Then, as shown in Figure 5, form the second emitter region 180 in the first emitter region 110 of gate electrode 170 both sides, and this second emitter region 180 has the first conductivity type.Such as, in one embodiment, this second emitter region 180 is heavy doping first conductivity type.This second emitter region 180 extends in the first emitter region 110 from the upper surface 100A (also can be described as the surperficial 100A of the first emitter layer 110) of substrate 100, in embodiments of the present invention, second emitter region 180 only extends into the partial depth of the first emitter region 110, that is the thickness T3 of this second emitter region 180 is less than the thickness T1 of the first emitter region 110.In one embodiment, this second emitter region 180 is formed by ion implantation step.Such as, when this first conductivity type is N-type, phosphonium ion or arsenic ion can be injected in the region of this second emitter region 180 of predetermined formation.
Continue see Fig. 5, in certain embodiments, the second emitter region 180 being positioned at the second side S2 of groove 120 can direct contact trench 120.From aforementioned, when being positioned at the second emitter region 180 direct contact trench 120 of the second side S2, the recruitment of the conducting voltage of Insulated Gate Bipolar transistor can be almost 0.In addition, in the present embodiment, gate electrode 170 does not extend on the upper surface 100A of the substrate 100 of the second side S2, that is, be 0 at the extended distance of gate electrode 170 on the upper surface 100A of substrate 100 or the first emitter-base bandgap grading zones/layers 110 of the second side S2.But, these those skilled in the art also may extend on the upper surface 100A of the substrate 100 of the second side S2 when understanding gate electrode 170, and the second emitter region 180 being positioned at the second side S2 also can not direct contact trench 120, this part will describe in detail in hereinafter another embodiment.
In addition, be positioned between second emitter region 180 of the first side S1 of groove 120 and groove 120 and be separated with width W 2.The width W 3 that this width W 2 is about horizontal grid part 130P deducts the distance that the width W 4 of groove 120 and the second emitter region 180 diffuse to width W 5 gained below horizontal grid part 130P.In certain embodiments, width W 2 is 0.05-0.2 times of the width W 1 of the first emitter region 110.In one embodiment, if width W 2 is wide, such as wider than 0.2 times of width W 1 of the first emitter region 110, then excessively can reduce the current density (such as decreasing beyond the current density of about 20%) of the final Insulated Gate Bipolar transistor formed, make the final Insulated Gate Bipolar transistor formed be difficult to be applied in practical semiconductor device.But, if this width W 2 is narrow, such as be narrower than 0.05 times of the width W 1 of the first emitter region 110, then effectively cannot reduce the current density (current density such as reduced is less than about 5%) of the final Insulated Gate Bipolar transistor formed, make the characteristic of final Insulated Gate Bipolar transistor short circuit current test (shortcircuittest) formed not good.
Then, continue see Fig. 5, form interlayer dielectric layer 190 on gate electrode 170.This interlayer dielectric layer 190 overlies gate structure 130 is positioned at top and the sidewall of the part outside groove 120.This interlayer dielectric layer 190 is in order to be electrically insulated by the emitter-base bandgap grading electrode of gate electrode 170 with follow-up formation.Interlayer dielectric layer 190 can be silica, silicon nitride, silicon oxynitride, boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), spin-on glasses (SOG) or other any applicable dielectric material or above-mentioned combination.Interlayer dielectric layer 190 is formed by aforesaid chemical vapour deposition technique (CVD), method of spin coating or highdensity plasma (highdensityplasma, HDP) deposition and patterning step.
Then, see Fig. 6, an additional etch step eating thrown interlayer dielectric layer 190 and the second emitter region 180 is carried out to form contact opening 200.This etching step can comprise reactive ion etching (reactiveionetch, RIE), plasma etching or other suitable etching step.Then, alternative carries out an ion implantation step to form one the 3rd emitter region 210 in the first emitter region 110, and this 3rd emitter region 210 can be heavy doping second conductivity type.The step forming the 3rd emitter region 210 in the embodiment of the present invention does not use extra mask, therefore can reduce production cost.Previous embodiment first forms groove to arrange in pairs or groups doping process again to form the 3rd emitter region 210, in other embodiments, also only can use doping process, form the 3rd emitter region in presumptive area, the degree of depth of the 3rd emitter region formed by this mode, by suitable with the degree of depth of the second emitter region 180.
Then, see Fig. 7, emitter-base bandgap grading electrode 220 is formed.This emitter-base bandgap grading electrode 220 is electrically connected with the second emitter region 180 and the 3rd emitter region 210.This emitter-base bandgap grading electrode 220 is coupled to (being electrically connected to) first emitter region 110 by the 3rd emitter region 210 again.In certain embodiments, emitter-base bandgap grading electrode 220 to be formed on interlayer dielectric layer 190 and to insert in contact opening 200.This emitter-base bandgap grading electrode 220 can be the good metal material (such as aluminium copper (AlCu), Al-Si-Cu alloy (AlSiCu)) of the gold of single or multiple lift, chromium, nickel, platinum, titanium, aluminium, iridium, rhodium, copper, above-mentioned combination or other conductivity.This emitter-base bandgap grading electrode 220 is by being such as sputtering method, galvanoplastic, resistive heating evaporation, e-beam evaporation or other any applicable depositing operation formation.In addition, interlayer dielectric layer 190 is located between gate electrode 170 and emitter-base bandgap grading electrode 220, and this interlayer dielectric layer 190 can make gate electrode 170 and emitter-base bandgap grading electrode 220 be electrically insulated.
Then, after emitter-base bandgap grading electrode 220, alternative thin substrate 100 (graphic do not illustrate this thinning step).The thickness of the substrate 100 after this thinning can be different according to operating voltage and component structure.
As shown in Figure 7, the bottom of substrate 100 is collector fate 230, and the region in substrate 100 except the first emitter region 180, emitter region 110, second, the 3rd emitter region 210 and collector fate 230 is as predetermined drift region 240.
Then, after formation emitter-base bandgap grading electrode 220 or after thin substrate 100 (if having the words of the step of carrying out thin substrate 100), alternative formation heavy doping resilient coating 250 is (that is being formed in the first follow-up conductivity type drift zones/layers) in predetermined drift region 240.This heavy doping resilient coating 250 has the first conductivity type, and can in order to reduce the size of the final Insulated Gate Bipolar transistor formed further.This heavy doping resilient coating 250 is formed by ion implantation step.Such as, when this first conductivity type is N-type, phosphonium ion or arsenic ion can be injected in the region of this heavy doping resilient coating 250 of predetermined formation.In another embodiment, the bottom surface of substrate 100 in FIG can form the heavy doping resilient coating (the heavy doping resilient coatings 250 of such as Fig. 7 ~ 8) with the first conductivity type by the mode of thermal diffusion (thermaldiffusion) in advance, the temperature of thermal diffusion process is about 1100 DEG C ~ 1200 DEG C.So, doping process collocation thermal diffusion process can be used to form the desired resilient coating with predetermined thickness.For example, the technique of doping collocation thermal diffusion first can be carried out for semiconductor substrate (such as N-type substrate), extend in semiconductor substrate respectively at two surfaces that semiconductor substrate is relative and form resilient coating, then again by this semiconductor substrate along the direction parallel with above-mentioned two surfaces to being cut into two semiconductor substrates, to the one side of the substrate after cutting, there is resilient coating, another side does not then have resilient coating, then can start to carry out follow-up step (step in such as Fig. 1) on the surface without resilient coating.
Then, see Fig. 8, carry out ion implantation step and inject the second conductivity type admixture to form collector region 260 (being also called collector layer 260) in collector fate 230 place, this collector region 260 has this second conductivity type, and extends in substrate 100 from the lower surface 100B of substrate 100.Substrate 100 be not formed the first emitter region 180, emitter region 110, second, the 3rd emitter region 210, collector region 260 and heavy doping resilient coating 250 part be as the first conductivity type drift region 255 (being also called the first conductivity type drift layer 255).And heavy doping resilient coating 250 is between this first conductivity type drift region 255 and collector region 260.It should be noted, if do not form heavy doping resilient coating 250, then substrate 100 is not formed with the first emitter region 180, emitter region 110, second, the part 270 of the 3rd emitter region 210 and collector region 260 is as the first conductivity type drift region 270 (being also called the first conductivity type drift layer 270).
Then, continue see Fig. 8, form collector electrode 280 to complete the making of Insulated Gate Bipolar transistor 300.This collector electrode 280 is electrically connected collector region 260.Collector electrode 280 can be the good metal material (such as titanium nickeline (TiNiAg)) of the gold of single or multiple lift, chromium, nickel, platinum, titanium, aluminium, iridium, rhodium, copper, above-mentioned combination or other conductivity.This collector electrode 280 is by being such as sputtering method, galvanoplastic, resistive heating evaporation, e-beam evaporation or other any applicable depositing operation formation.
Previous embodiment forms collector region again after emitter region is formed, but the present invention is not limited to this manufacture.For example, the semiconductor substrate with the second conduction type (such as P+) can be provided, the dopant concentration of this semiconductor substrate conforms to the dopant concentration of the collector region 260 in the predetermined Insulated Gate Bipolar transistor (IGBT) 300 formed, and then on this semiconductor substrate, forms resilient coating (the heavy doping resilient coatings 250 of such as Fig. 7 ~ 8) with the way selection formula of such as epitaxial growth.Then the drift region (the first conductivity type drift region 255 of such as Fig. 8) of IGBT is formed again further in the mode of such as epitaxial growth.Then other part of IGBT is formed again with the correlation step of such as Fig. 1 ~ 7, in this embodiment, aforementioned with the drift region of epitaxial growth, be just equivalent to the substrate 100 in Fig. 1, the step of similar Fig. 1 ~ 7, sequentially forms other part such as first emitter region 110 etc. in this drift region.
The Insulated Gate Bipolar transistor 300 of the embodiment of the present invention comprises collector electrode 280.Collector layer 260, electrical connection collector electrode 280, and there is the second conductivity type.First conductivity type drift layer 255, be located on collector layer 260, wherein the first conductivity type is different from the second conductivity type.First emitter layer 110, is located in the first conductivity type drift layer 255, and has the second conductivity type.Groove 120 (trench), extends in the first conductivity type drift layer 255 from the surperficial 100A of the first emitter layer 110, and wherein groove 120 has the first relative side S1 and the second side S2.Gate electrode 170, to insert in groove 120 and to extend on the surperficial 100A of the first emitter layer 110, wherein different at the extended distance of gate electrode 170 on the surperficial 100A of the first emitter layer 110 of the first side S1 and the second side S2.Gate dielectric 160, is located between gate electrode 170 and groove 120 and between gate electrode 170 and the first emitter layer 110.Second emitter region 180, be located in the first emitter layer 110 of gate electrode 170 both sides, wherein the second emitter region 180 has the first conductivity type.Interlayer dielectric layer 190, is located on the first emitter layer 110.Emitter-base bandgap grading electrode 220, be electrically connected with the first emitter layer 110 and the second emitter region 180, wherein interlayer dielectric layer 190 is located between gate electrode 170 and emitter-base bandgap grading electrode 220.Insulated Gate Bipolar transistor 300 also comprises heavy doping resilient coating 250, has the first conductivity type and is located between the first conductivity type drift layer 255 and collector layer 260.
In certain embodiments, the second emitter region 180 directly contact trench 120 of the second side S2 of groove 120 is positioned at.In addition, in certain embodiments, gate electrode 170 does not extend on the upper surface 100A of the substrate 100 of the second side S2.Moreover, be positioned between second emitter region 180 of the first side S1 of groove 120 and groove 120 and be separated with width W 2.In certain embodiments, this width W 2 can be the about 0.05-0.2 of the width W 1 of the first emitter region 110 doubly.
It should be noted, although in the embodiment shown in fig. 8, be positioned at the second direct contact trench in emitter region of the second side of groove, and gate electrode does not extend on the upper surface of the substrate of the second side.But these those skilled in the art are when the second emitter region can understanding the second side being positioned at groove also can not direct contact trench, and when the second side the second emitter region not directly contact trench time, to make the circuit of device operate on the upper surface that gate electrode must extend to the substrate of the second side.
Specifically, as shown in Figure 9, the second emitter region 180 being positioned at the second side S2 also can not direct contact trench 120, and this is positioned between second emitter region 180 of the second side S2 of groove 120 and groove 120 and is separated with width W 6.Width W 2 is greater than width W 6, and width W 6 is more than or equal to 0, when width W 6 equals 0, namely represents the second emitter region 180 directly contact trench 120 being positioned at the second side S2.And when the second side S2 the second emitter region 180 not directly contact trench 120 time, gate electrode 170 need extend on the upper surface 100A of the substrate 100 of the second side S2.Afterwards, after heat diffusion treatment, emitter region, right side 180 will be spread and directly be contacted with the second side S2 of groove 120, to form vertical passage.
It should be noted, although in above embodiment, all with the first conductivity type for N-type, the second conductivity type is that P type illustrates, but these those skilled in the art also can be P type when can understand the first conductivity type, and now the second conductivity type is then N-type.
Table 1
| The plough groove type IGBT of comparative example | Example I GBT | |
| Puncture voltage (V) | 1250 | 1250 |
| Conducting voltage (V) | 2.65 | 2.68 |
| Shut-in time (ns) | 435 | 295 |
| Latch-up current density (A/cm 2) | 1500 | 1450 |
Table 1 shows the Performance comparision of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example, and Figure 10 is current density and the voltage analysis figure of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example, Figure 11 is that Figure 10 is in the partial enlarged drawing of part A.This analysis chart simulates gained by computer software (TechnologyComputerAidedDesign, TCAD).This embodiment is tested with the structure shown in Fig. 8, wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, be such as about 0.95/5.95, and the plough groove type Insulated Gate Bipolar transistor of comparative example (the plough groove type IGBT of comparative example) and the difference of the Insulated Gate Bipolar transistor of the embodiment of the present invention are that its grid structure only has vertical gate 130V part, and do not have horizontal grid 130P part, and its second emitter region 180 directly contacts the vertical gate 130V part of the first side S1.Figure 10 display is compared to the current density of the plough groove type Insulated Gate Bipolar transistor of comparative example, and the current density of the Insulated Gate Bipolar transistor of the embodiment of the present invention decreases about 20% (part B of such as Figure 10).In addition, see Figure 10,11 and table 1, the conducting voltage of the Insulated Gate Bipolar transistor of the embodiment of the present invention is 2.68V, and the conducting voltage of the plough groove type Insulated Gate Bipolar transistor of comparative example is 2.65V.It can thus be appreciated that, the Insulated Gate Bipolar transistor of the embodiment of the present invention can not affect its conducting voltage (turnonvoltage) while the current density reducing device, and the reduction of this current density can reduce Insulated Gate Bipolar transistor is short-circuited the chance of failure of circuit test.
Figure 12 is ESD protection area and the conducting voltage analysis chart of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example.This embodiment is tested with the structure shown in Fig. 8, wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, be such as about 0.95/5.95, and the Insulated Gate Bipolar transistor that the second emitter region 180 directly contacts the groove 120 (that is the second emitter region directly contacts the vertical gate 130V part of the second side S2) of the second side S2 perform an analysis.With the difference of the Insulated Gate Bipolar transistor of the embodiment of the present invention, the plough groove type Insulated Gate Bipolar transistor (the plough groove type IGBT of comparative example) of comparative example in addition in this analysis is that its grid structure only has vertical gate 130V part, and do not have horizontal grid 130P part, and its second emitter region 180 directly contacts the vertical gate 130V part of the first side S1.And the horizontal Insulated Gate Bipolar transistor (the horizontal IGBT of comparative example) of comparative example and the difference of the Insulated Gate Bipolar transistor of the embodiment of the present invention are that its grid structure only has horizontal grid 130P part, and not there is vertical gate 130V part.
Though the plough groove type Insulated Gate Bipolar transistor that Figure 12 shows comparative example has lower conducting voltage (about 2.65V), its ESD protection area poor (about 5 μ s).And though the horizontal Insulated Gate Bipolar transistor of comparative example has preferably ESD protection area (about 7 μ s), its conducting voltage higher (about 3.7V).It can thus be appreciated that the horizontal Insulated Gate Bipolar transistor of the plough groove type Insulated Gate Bipolar transistor AND gate comparative example of comparative example cannot have above-mentioned two advantages simultaneously.In comparison, the Insulated Gate Bipolar transistor of the embodiment of the present invention can have the advantage of the horizontal Insulated Gate Bipolar transistor of the plough groove type Insulated Gate Bipolar transistor AND gate comparative example of comparative example concurrently, that is the Insulated Gate Bipolar transistor of the embodiment of the present invention has preferably conducting voltage (about 2.68V) and preferably ESD protection area (about 7 μ s) simultaneously.The Insulated Gate Bipolar transistor of the embodiment of the present invention can have the reason of above-mentioned two advantages simultaneously, be because it can not affect its conducting voltage while the current density reducing device, therefore its conducting voltage can raise and more or less the same with the plough groove type Insulated Gate Bipolar transistor of comparative example hardly.And the current density that the Insulated Gate Bipolar transistor of the embodiment of the present invention reduces can make it have preferably ESD protection area, even more or less the same with the ESD protection area of the horizontal Insulated Gate Bipolar transistor of comparative example, as shown in figure 12.
Figure 13 is the switch performance analysis chart of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example, and Figure 14 is that Figure 13 is in the partial enlarged drawing of C part.This analysis chart simulates gained by computer software (TCAD).This embodiment is tested with the structure shown in Fig. 8, wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, be such as about 0.95/5.95, and the plough groove type Insulated Gate Bipolar transistor of comparative example (the plough groove type IGBT of comparative example) is identical with the plough groove type IGBT of the comparative example of previous embodiment.Figure 13, Figure 14 and table 1 show bestows identical voltage by the Insulated Gate Bipolar transistor (example I GBT) of the embodiment of the present invention with the plough groove type Insulated Gate Bipolar transistor (the plough groove type IGBT of comparative example) of comparative example, and when closing voltage simultaneously, the shut-in time of the electric current of the Insulated Gate Bipolar transistor of the embodiment of the present invention is 295ns, and the shut-in time of the plough groove type Insulated Gate Bipolar transistor of comparative example (the plough groove type IGBT of comparative example) is 435ns.It can thus be appreciated that the grid structure of the Insulated Gate Bipolar transistor of the embodiment of the present invention significantly can reduce the shut-in time of device.
Figure 15 is the analysis of electric field figure of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example.The transverse axis of this figure represents the direction of Insulated Gate Bipolar transistor from upper surface 100A to lower surface 100B (that is the direction Y Fig. 1), and the longitudinal axis represents that this Insulated Gate Bipolar transistor is in the electric field of this position.This embodiment is tested with the structure shown in Fig. 8, wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, be such as about 0.95/5.95, and the plough groove type Insulated Gate Bipolar transistor of comparative example (the plough groove type IGBT of comparative example) is identical with the plough groove type IGBT of the comparative example of previous embodiment.As shown in Figure 15, compared to the plough groove type Insulated Gate Bipolar transistor (the plough groove type IGBT of comparative example) of comparative example, the Electric Field Distribution of the Insulated Gate Bipolar transistor internal of the embodiment of the present invention is evenly many, and A point in Figure 15 is stronger to the electric field in the interval of B point.Because stronger electric field can have the blocking effect in electric hole, reduce the shut-in time, therefore the Insulated Gate Bipolar transistor that this case has a stronger electric field significantly can reduce the shut-in time of device.
Figure 16 be the embodiment of the present invention and comparative example Insulated Gate Bipolar transistor in off position under puncture voltage analysis chart.This analysis chart simulates gained by computer software (TCAD).This embodiment is tested with the structure shown in Fig. 8, and wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, be such as about 0.95/5.95, and the plough groove type Insulated Gate Bipolar transistor of comparative example (the plough groove type IGBT of comparative example) is identical with the plough groove type IGBT of the comparative example of previous embodiment.The puncture voltage that Figure 16 and table 1 show the electric current of the Insulated Gate Bipolar transistor of the embodiment of the present invention is 1250V, and the puncture voltage of the plough groove type Insulated Gate Bipolar transistor of comparative example (the plough groove type IGBT of comparative example) is also 1250V.It can thus be appreciated that the Insulated Gate Bipolar transistor of the embodiment of the present invention can not affect its puncture voltage while the shut-in time of reducing device and current density.
Moreover, table 1 tests with the structure shown in Fig. 8, and wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, be such as about 0.95/5.95, and the plough groove type Insulated Gate Bipolar transistor of comparative example (the plough groove type IGBT of comparative example) is identical with the plough groove type IGBT of the comparative example of previous embodiment.As shown in Table 1, the latch-up current density (latchupcurrentdensity) of the electric current of the Insulated Gate Bipolar transistor of the embodiment of the present invention is 1450A/cm
2, and the latch-up current density of the plough groove type Insulated Gate Bipolar transistor of comparative example (the plough groove type IGBT of comparative example) is 1500A/cm
2.It can thus be appreciated that the Insulated Gate Bipolar transistor of the embodiment of the present invention can not affect its latch-up current density while the shut-in time of reducing device and current density.
In sum, the Insulated Gate Bipolar transistor of the embodiment of the present invention can reduce current density and close loss, and does not affect its conducting voltage, puncture voltage and latch-up current density simultaneously.In addition, the reduction of current density can reduce Insulated Gate Bipolar transistor and to be short-circuited the chance of failure of circuit test, the yield of lifting device.And owing to closing the reduction of loss, after device is closed, the carrier of flowing can reduce fast, therefore further can shorten the switching time (switchingtime) of device, the significantly performance of enhanced device.
Although embodiments of the invention and advantage thereof have disclosed as above, will be appreciated that any the technical staff in the technical field, without departing from the spirit and scope of the present invention, when changing, substitute and retouching.In addition; protection scope of the present invention is not confined to manufacturing process in specification in described specific embodiment, machine, manufacture, material composition, device, method and step; any the technical staff in the technical field can understand existing or following developed manufacturing process, machine, manufacture, material composition, device, method and step from disclosure of the present invention, all can be used according to the invention as long as can implement more or less the same function or obtain more or less the same result in described embodiment herein.Therefore, protection scope of the present invention comprises above-mentioned manufacturing process, machine, manufacture, material composition, device, method and step.In addition, each claim forms other embodiment, and protection scope of the present invention also comprises the combination of each claim and embodiment.
Claims (15)
1. an Insulated Gate Bipolar transistor, is characterized in that, comprising:
One collector electrode;
One collector layer, is electrically connected this collector electrode, and has one second conductivity type;
One first conductivity type drift layer, be located on this collector layer, wherein this first conductivity type is different from this second conductivity type;
One first emitter layer, is located in this first conductivity type drift layer, and has this second conductivity type;
One groove, extends into from the surface of this first emitter layer in this first conductivity type drift layer, and wherein this groove has one first relative side and one second side;
One gate electrode, to insert in this groove and to extend on the surface of this first emitter layer, wherein different at the extended distance of this gate electrode on the surface of this first emitter layer of this first side and this second side;
One gate dielectric, is located between this gate electrode and this groove and between this gate electrode and this first emitter layer;
One second emitter region, be located in this first emitter layer of these gate electrode both sides, wherein this second emitter region has this first conductivity type;
One interlayer dielectric layer, is located on this first emitter layer; And
One emitter-base bandgap grading electrode, be electrically connected with this first emitter layer and this second emitter region, wherein this interlayer dielectric layer is located between this gate electrode and this emitter-base bandgap grading electrode.
2. Insulated Gate Bipolar transistor as claimed in claim 1, it is characterized in that, the second emitter region being positioned at the second side of this groove directly contacts this groove.
3. Insulated Gate Bipolar transistor as claimed in claim 1, is characterized in that, be positioned between the second emitter region of the first side of this groove and this groove and be separated with a width, and this width is 0.05-0.2 times of the width of this first emitter region.
4. Insulated Gate Bipolar transistor as claimed in claim 1, it is characterized in that, the extended distance of this gate electrode in this second side on the surface of this first emitter layer is 0.
5. Insulated Gate Bipolar transistor as claimed in claim 1, it is characterized in that, this gate electrode comprises amorphous silicon, polysilicon or above-mentioned combination.
6. Insulated Gate Bipolar transistor as claimed in claim 1, is characterized in that, also comprise a heavy doping resilient coating have this first conductivity type and be located between this first conductivity type drift layer and this collector layer.
7. a manufacture method for Insulated Gate Bipolar transistor, is characterized in that, comprising:
One substrate is provided, there is one first conductivity type, and there is a upper surface and a lower surface;
Form one first emitter region, there is one second conductivity type, and extend in this substrate from the upper surface of this substrate, and this second conductivity type is different from this first conductivity type;
Form a groove, extend from the upper surface of this substrate and pass through this first emitter region in this substrate, wherein this groove has one first relative side and one second side;
Form a grid structure, comprise a gate dielectric and a gate electrode, wherein this gate electrode to be inserted in this groove and is extended on the upper surface of this substrate, the extended distance of this gate electrode wherein in this first side and this second side on the upper surface of this substrate is different, and this gate dielectric is located between this gate electrode and this groove and between this gate electrode and this first emitter region;
Form one second emitter region in this first emitter region of these gate electrode both sides, wherein this second emitter region has this first conductivity type;
Form an interlayer dielectric layer on this gate electrode;
Form an emitter-base bandgap grading electrode, this emitter-base bandgap grading electrode is electrically connected with this first emitter region, this second emitter region, and this interlayer dielectric layer is located between this gate electrode and this emitter-base bandgap grading electrode;
Form a collector region, have this second conductivity type, and extend in this substrate from the lower surface of this substrate, wherein this substrate is not formed with this first emitter region, the part of this second emitter region and this collector region is as one first conductivity type drift region; And
Form a collector electrode, this collector electrode is electrically connected this collector region.
8. the manufacture method of Insulated Gate Bipolar transistor as claimed in claim 7, it is characterized in that, the method forming this grid structure comprises:
Compliance forms a dielectric materials layer on the sidewall of this groove and the upper surface of bottom and this substrate;
Form a conductive layer and insert in this groove on this dielectric materials layer; And
This dielectric materials layer of patterning and this conductive layer are to form this gate dielectric and this gate electrode respectively.
9. the manufacture method of Insulated Gate Bipolar transistor as claimed in claim 7, it is characterized in that, the second emitter region being positioned at the second side of this groove directly contacts this groove.
10. the manufacture method of Insulated Gate Bipolar transistor as claimed in claim 7, is characterized in that, be positioned between the second emitter region of the first side of this groove and this groove and be separated with a width, and this width is 0.05-0.2 times of the width of this first emitter region.
The manufacture method of 11. Insulated Gate Bipolar transistors as claimed in claim 7, is characterized in that, the extended distance of this gate electrode in this second side on the upper surface of this substrate is 0.
The manufacture method of 12. Insulated Gate Bipolar transistors as claimed in claim 7, it is characterized in that, this gate electrode comprises amorphous silicon, polysilicon or above-mentioned combination.
The manufacture method of 13. Insulated Gate Bipolar transistors as claimed in claim 7, is characterized in that, also comprise formation one heavy doping resilient coating between this first conductivity type drift region and this collector region, wherein this heavy doping resilient coating has this first conductivity type.
The manufacture method of 14. 1 kinds of Insulated Gate Bipolar transistors, is characterized in that, comprising:
There is provided a substrate, have one second conductivity type, wherein this substrate is as a collector region;
Form an epitaxial loayer on this substrate, this epitaxial loayer has one first conductivity type, and this first conductivity type is different from this second conductivity type;
Form one first emitter region, extend in this epitaxial loayer from the surface of this epitaxial loayer, and there is this second conductivity type;
Form a groove, extend from the surface of this first emitter region and pass through this first emitter region in this epitaxial loayer, wherein this groove has one first relative side and one second side;
Form a grid structure, comprise a gate dielectric and a gate electrode, wherein this gate electrode to be inserted in this groove and is extended to the surface of this first emitter region, the extended distance of this gate electrode wherein in this first side and this second side on the surface of this first emitter region is different, and this gate dielectric is located between this gate electrode and this groove and between this gate electrode and this first emitter region;
Form one second emitter region in this first emitter region of these gate electrode both sides, wherein this second emitter region has this first conductivity type, and wherein this epitaxial loayer is not formed with the part of this first emitter region and this second emitter region is as one first conductivity type drift region;
Form an interlayer dielectric layer on this gate electrode;
Form an emitter-base bandgap grading electrode, this emitter-base bandgap grading electrode is electrically connected with this first emitter region, this second emitter region, and this interlayer dielectric layer is located between this gate electrode and this emitter-base bandgap grading electrode; And
Form a collector electrode, this collector electrode is electrically connected this collector region.
The manufacture method of 15. Insulated Gate Bipolar transistors as claimed in claim 14, is characterized in that, before being also included in this epitaxial loayer, form a heavy doping resilient coating on this substrate, wherein this heavy doping resilient coating has this first conductivity type.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020006703A1 (en) * | 1998-12-18 | 2002-01-17 | Frank Pfirsch | Field-effect transistor configuration with a trench-shaped gate electrode and an additional highly doped layer in the body region |
| US20070272978A1 (en) * | 2006-05-23 | 2007-11-29 | Infineon Technologies Austria Ag | Semiconductor device including a vertical gate zone, and method for producing the same |
| CN102386233A (en) * | 2010-08-30 | 2012-03-21 | 精工电子有限公司 | Semiconductor device |
| US20140110777A1 (en) * | 2012-10-18 | 2014-04-24 | United Microelectronics Corp. | Trench gate metal oxide semiconductor field effect transistor and fabricating method thereof |
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| US7795691B2 (en) * | 2008-01-25 | 2010-09-14 | Cree, Inc. | Semiconductor transistor with P type re-grown channel layer |
| JP5156518B2 (en) * | 2008-07-23 | 2013-03-06 | 株式会社日立製作所 | Storage control apparatus and method |
| JP5361808B2 (en) * | 2010-06-23 | 2013-12-04 | 三菱電機株式会社 | Power semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020006703A1 (en) * | 1998-12-18 | 2002-01-17 | Frank Pfirsch | Field-effect transistor configuration with a trench-shaped gate electrode and an additional highly doped layer in the body region |
| US20070272978A1 (en) * | 2006-05-23 | 2007-11-29 | Infineon Technologies Austria Ag | Semiconductor device including a vertical gate zone, and method for producing the same |
| CN102386233A (en) * | 2010-08-30 | 2012-03-21 | 精工电子有限公司 | Semiconductor device |
| US20140110777A1 (en) * | 2012-10-18 | 2014-04-24 | United Microelectronics Corp. | Trench gate metal oxide semiconductor field effect transistor and fabricating method thereof |
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| CN105374864B (en) | 2019-01-11 |
| TWI559531B (en) | 2016-11-21 |
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