CN105356820A - Middle and high voltage frequency conversion speed regulation double CPU control system and control method thereof - Google Patents
Middle and high voltage frequency conversion speed regulation double CPU control system and control method thereof Download PDFInfo
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- CN105356820A CN105356820A CN201510901147.2A CN201510901147A CN105356820A CN 105356820 A CN105356820 A CN 105356820A CN 201510901147 A CN201510901147 A CN 201510901147A CN 105356820 A CN105356820 A CN 105356820A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
- H02P27/085—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation wherein the PWM mode is adapted on the running conditions of the motor, e.g. the switching frequency
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P2209/00—Indexing scheme relating to controlling arrangements characterised by the waveform of the supplied voltage or current
- H02P2209/09—PWM with fixed limited number of pulses per period
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Abstract
The invention discloses a middle and high voltage frequency conversion speed regulation double CPU control system, which comprises an algorithm DSP master control chip, a logic DSP master control chip, a double-port RAM chip, power units and a FPGA master control chip; the algorithm DSP master control chip is connected with the FPGA master control chip; the logic DSP master control chip is connected with the FPGA master control chip; the double-port RAM chip is connected with the algorithm DSP master control chip and the logic DSP master control chip; the FPGA master control chip is connected with the algorithm DSP master control chip, the logic DSP master control chip and each power unit; and the power units are connected with the FPGA master control chip through fiber interfaces. The algorithm DSP master control chip and the logic DSP master control chip work in a parallel way, thereby improving reliability and real-time performance of the control system; because the FPGA master control chip can send PWM waves and logic control commands to each power unit at the same time, the synchronization performance of each power unit is guaranteed, thereby raising system stability.
Description
Technical field
The present invention relates to variable-frequency control technique field, be specifically related to a kind of middle high-pressure frequency control two-ways cpu system and control method thereof.
Background technology
At present, middle high-pressure RHVC utilizes power unit cascade, gets up to realize High voltage output by multistage low pressure and low power units in series.Wherein program harmonic wave of output voltage is little, improves electrical machinery life and reduces electromagnetic interference etc.In addition, in the middle high-pressure RHVC of cascade of power units formula, controller has been used for motor control strategy, many level pulse widths (PWM) algorithm, the tasks such as the input and output process of fiber optic serial communication, host computer communication, digital quantity/analog quantity.The real-time of controller and disposal ability determine reliability, the stability of whole system Electric Machine Control greatly.
Controller of the prior art mainly comprises: main control unit and multiple peripheral control unit.Wherein, peripheral control unit is the unit possessing certain logic processing capability, such as: DSP, ARM, FPGA, CPLD etc.Each peripheral control unit is responsible for the control of a power cell, all peripheral control units directly and main control unit carry out data communication, main control unit plays the effect of commander in chief, namely main control unit sends control command to each peripheral control unit, and peripheral control unit to receive after the instruction of main control unit by optical fiber communication sending controling instruction to each power cell.Peripheral control unit transmitting element control command gives each power cell, and processing power unit feeds back the running state information of coming simultaneously, then feeds back to main control unit.
Because controller can only the execution instruction of serial, send out to power cell the poor synchronization that PWM ripple controls, therefore, cause each power cell error operate time large, and control performance is undesirable, cost is high, reliability is low.
Summary of the invention
For the defect existed in prior art, the object of the present invention is to provide a kind of middle high-pressure frequency control two-ways cpu system and control method thereof.
For reaching above object, the technical scheme that the present invention takes is:
A kind of middle high-pressure frequency control two-ways cpu system, comprises algorithm DSP main control chip, logic DSP main control chip, dual port RAM chip, power cell and FPGA main control chip,
Algorithm DSP main control chip, it is connected with described FPGA main control chip, and it is for being sent to described FPGA main control chip by the inversion modulating wave instruction of the V/F of motor or vector control, and periodically reads the blockade PWM ripple order in described FPGA main control chip;
Logic DSP main control chip, it is connected with described FPGA main control chip, and it is for issuing described FPGA main control chip by the logic control order of motor, and the running state information periodically reading in described FPGA main control chip described in each power cell;
Dual port RAM chip, it is connected with described algorithm DSP main control chip, described logic DSP main control chip respectively, for the data communication between described algorithm DSP main control chip and described logic DSP main control chip;
FPGA main control chip, it is connected with described algorithm DSP main control chip, logic DSP main control chip and power cell described in each respectively, the V/F of described motor or the inversion modulating wave instruction of vector control and the carrier wave of its inner setting are compared, generate the PWM ripple that power cell described in each is corresponding, by the logic control order of described motor, carry out integrated logic with the fault message of power cell described in each to judge to produce and block the order of PWM ripple, for the logic control of described motor;
Power cell, it connects described FPGA main control chip by optical fiber interface, its receive that described FPGA main control chip exports each described in PWM ripple corresponding to power cell, described PWM ripple is for controlling power cell action described in each, realize V/F or the vector control of motor, and its running state information is sent to FPGA main control chip.
On the basis of technique scheme, described FPGA main control chip comprises a SRAM module, PWM ripple generation module, the 2nd SRAM module, unit information processing module, unit communication processing module,
One SRAM module, itself and described algorithm DSP main control chip are bi-directionally connected, for receiving the V/F of motor or the inversion modulating wave instruction of vector control of the transmission of described algorithm DSP main control chip, and send described blockade ripple pwm command to described algorithm DSP main control chip;
PWM ripple generation module, its input is connected with the output of described unit information processing module with the output of a described SRAM module respectively, its output is connected with the input of described unit communication processing module with the input of a described SRAM module respectively, it receives the described V/F of described motor of a SRAM module output or the blockade PWM ripple order of the inversion modulating wave instruction of vector control and the output of described unit information processing module, described inversion modulating wave and the carrier wave that sets in it are compared, generate the PWM ripple of each power cell, described unit communication processing module is exported to by defeated for described PWM ripple,
2nd SRAM module, itself and described logic DSP main control chip are bi-directionally connected, and it receives the logic control order of the motor that described logic DSP main control chip sends, and sends the running state information of power cell described in each to described logic DSP main control chip;
Unit information processing module, its input is connected with the output of described 2nd SRAM module with the output of described unit communication processing module respectively, its output is connected with the input of described 2nd SRAM module with the input of described PWM ripple generation module respectively, for receive that described unit communication processing module forwards each described in the running state information of power cell, and to described 2nd SRAM module forwards running state information, it judges whether to send to described PWM ripple generation module to block the order of PWM ripple according to the fault message of power cell described in each;
Unit communication processing module, itself and each described power cell are bi-directionally connected, its forward described PWM ripple generation CMOS macro cell each described in PWM ripple corresponding to power cell, it forwards the running state information of described power cell to described unit information processing module.
On the basis of technique scheme, described logic DSP main control chip is provided with organizes Wiring port more, and described Wiring port connects HMI respectively, host computer, user control I/O signal module, analog input and output module and Systematical control I/O signal module.
On the basis of technique scheme, be provided with data acquisition unit in described algorithm DSP main control chip, described data acquisition unit is for gathering the input voltage of RHVC, input current, output voltage, output current and motor rotate speed feedback signal.
On the basis of technique scheme, a kind of control method of middle high-pressure frequency control two-ways cpu system,
Logical process is carried out in the logic control order of logic DSP main control chip to motor, logic control order is sent to described algorithm DSP main control chip and described FPGA main control chip;
The inversion modulating wave instruction of the V/F of motor or vector control is sent to FPGA main control chip by algorithm DSP main control chip;
Described inversion modulating wave and the carrier wave that sets in it are made comparisons by FPGA main control chip, generate the PWM ripple of power cell described in each;
Power cell receive that described PWM ripple sends to each described in the corresponding PWM ripple of power cell, carry out V/F or the vector control of motor.
On the basis of technique scheme, described FPGA main control chip comprises a SRAM module, PWM ripple generation module, the 2nd SRAM module, unit information processing module, unit communication processing module,
One SRAM module, itself and described algorithm DSP main control chip are bi-directionally connected, for receiving the V/F of motor or the inversion modulating wave instruction of vector control of the transmission of described algorithm DSP main control chip, and send described blockade ripple pwm command to described algorithm DSP main control chip;
PWM ripple generation module, its input is connected with the output of described unit information processing module with the output of a described SRAM module respectively, its output is connected with the input of described unit communication processing module with the input of a described SRAM module respectively, and PWM ripple generation module receives the V/F of motor of a SRAM module output or the blockade PWM ripple order of the inversion modulating wave instruction of vector control and the output of unit information processing module, described inversion modulating wave and the carrier wave that sets in it are compared, generate the PWM ripple of each power cell, described PWM ripple is exported to described unit communication processing module,
2nd SRAM module, itself and described logic DSP main control chip are bi-directionally connected, and it receives the logic control order of the motor that described logic DSP main control chip sends, and sends the running state information of power cell described in each to described logic DSP main control chip;
Unit information processing module, its input is connected with the output of described 2nd SRAM module with the output of described unit communication processing module respectively, its output is connected with the input of described 2nd SRAM module with the input of described PWM ripple generation module respectively, for receive that described unit communication processing module forwards each described in the running state information of power cell, and to described 2nd SRAM module forwards running state information, it judges whether to send to described PWM ripple generation module to block the order of PWM ripple according to the fault message of power cell described in each;
Unit communication processing module, itself and each described power cell are bi-directionally connected, its forward described PWM ripple generation CMOS macro cell each described in PWM ripple corresponding to power cell, it forwards the running state information of described power cell to described unit information processing module.
On the basis of technique scheme, the control method of described FPGA main control chip is as follows,
A described SRAM module receives the V/F of motor or the inversion modulating wave instruction of vector control of the transmission of described algorithm DSP main control chip; And send blockade ripple pwm command to described algorithm DSP main control chip;
Described 2nd SRAM module its receive the logic control order of motor that described logic DSP main control chip sends; And the running state information of power cell described in each is sent to described logic DSP main control chip;
Unit information processing module receive that described unit communication processing module forwards each described in the running state information of power cell, and to described 2nd SRAM module forwards running state information; It judges whether to send to described PWM ripple generation module to block the order of PWM ripple according to the fault message of power cell described in each;
Be provided with carrier wave in described PWM ripple generation module, it receives the inversion modulating wave exported from a described SRAM module, compares, generate the PWM ripple of each power cell of generation of each power cell with the carrier wave set in it; And send blockade ripple pwm command to a described SRAM module;
Unit communication processing module forwards the PWM ripple of each power cell sent from described PWM ripple generation module, and each power cell is according to the PWM ripple received, and each power cell does corresponding actions process; And forward the running state information of described power cell to described unit information processing module.
Compared with prior art, the invention has the advantages that:
(1) the present invention is by algorithm DSP main control chip and the concurrent working of logic DSP main control chip, and be independently responsible for algorithm or logical control task, thus effectively improve the reliability of control system, real-time than prior art middle controller can only serial to perform the asynchronous serial communication of instruction high; In addition, because FPGA main control chip can send PWM ripple and logic control order to each power cell simultaneously, thus ensure that the synchronism that each power cell controls, improve the stability of system.
(2) in the present invention, FPGA main control unit comprises SRAM modules A and the 2nd SRAM module, thus making algorithm DSP main control chip and logic DSP main control chip to carry out read-write operation to SRAM modules A and the 2nd SRAM module and not to clash simultaneously, access time only needed for tens nanoseconds.
Accompanying drawing explanation
Fig. 1 is systematic schematic diagram of the present invention.
Fig. 2 is system configuration schematic diagram of the present invention.
Fig. 3 is control method flow chart of the present invention.
In figure: 11-algorithm DSP main control chip, 12-FPGA main control chip, 13-logic DSP main control chip, 14-dual port RAM chip, 15-power cell, 121-the one SRAM module, 122-PWM ripple generation module, 123-the 2nd SRAM module, 124-unit information processing module, 125-unit communication processing module.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Shown in Figure 1, a kind of middle high-pressure frequency control two-ways cpu system and control method thereof, comprise algorithm DSP main control chip 11, logic DSP main control chip 13, dual port RAM chip 14, power cell 15 and FPGA main control chip 12,
Algorithm DSP main control chip 11, it is connected with dual port RAM chip 14 with FPGA main control chip 12, it is for being sent to FPGA main control chip 12 by the inversion modulating wave instruction of the V/F of motor or vector control, and it periodically reads the blockade PWM ripple order in FPGA main control chip 12; It periodically reads frequency, input current, input voltage, mains frequency, output current, output voltage and input and output side fault message that middle and high RHVC is run, and write in dual port RAM chip 14, periodically read the logic control order in dual port RAM chip 14, target frequency, control mode;
Logic DSP main control chip 13, it is connected with dual port RAM chip 14 with FPGA main control chip 12, it is for issuing FPGA main control chip 12 by the logic control order of motor, it periodically reads the running state information of each power cell 15 as input voltage from FPGA main control chip 12, target frequency, control mode, periodically by the logic control order to motor, target frequency, in control mode write dual port RAM chip 14, in in periodic reading dual port RAM chip 14, the frequency that high RHVC is run, input current, input voltage, mains frequency, output current, output voltage and input and output side fault message,
Dual port RAM chip 14, its respectively with algorithm DSP main control chip 11, logic DSP main control chip 13 is connected, algorithm DSP main control chip 11 periodically in, the frequency that high RHVC is run, input current, input voltage, mains frequency, output current, output voltage and input and output side fault message write in dual port RAM chip 14, logic DSP main control chip 13 is periodically by the logic control order to motor, target frequency, in control mode write dual port RAM chip 14, for the data communication between algorithm DSP main control chip 11 and logic DSP main control chip 13,
FPGA main control chip 12, it is connected with algorithm DSP main control chip 11, logic DSP main control chip 13 and each power cell 15 respectively, the V/F of motor or the inversion modulating wave instruction of vector control and the carrier wave of its inner setting are compared, generate the PWM ripple of each power cell 15 correspondence, by the logic control order of motor, carry out integrated logic with the fault message of each power cell 15 received to judge to produce and block the order of PWM ripple, for realizing the logic control of starting and stopping to motor, rotating forward, reversion, acceleration-deceleration;
Power cell 15, it connects FPGA main control chip 12 by optical fiber interface, it receives the PWM ripple of each power cell 15 correspondence that FPGA main control chip 12 exports, control conducting and the cut-off of switching tube in each power cell 15, realize V/F or the vector control of motor, and by its running state information as the input voltage of each power cell 15, busbar voltage, fault message send to FPGA main control chip 12;
Wherein, FPGA main control chip 12 comprises a SRAM module 121, PWM ripple generation module the 122, the 2nd SRAM module 123, unit information processing module 124, unit communication processing module 125,
One SRAM module 121, itself and algorithm DSP main control chip 11 are bi-directionally connected, the V/F to motor sent for receiving algorithm DSP main control chip 11 or the inversion modulating wave instruction of vector control, and send blockade ripple pwm command to algorithm DSP main control chip 11;
PWM ripple generation module 122, its input is connected with the output of unit information processing module 124 with the output of a SRAM module 121 respectively, its output is connected with the input of unit communication processing module 125 with the input of a SRAM module 121 respectively, it receives the V/F of motor of SRAM module 121 output or the blockade PWM ripple order of the inversion modulating wave instruction of vector control and unit information processing module 124 output, inversion modulating wave and the carrier wave that sets in it are compared, generate the PWM ripple of each power cell 15, PWM ripple is exported to unit communication processing module 125,
2nd SRAM module 123, itself and logic DSP main control chip 13 are bi-directionally connected, the logic control order of the motor that its receive logic DSP main control chip 13 sends, and the running state information sending each power cell 15 to logic DSP main control chip 13 is as input voltage, busbar voltage and fault message, logic DASP main control chip carries out corresponding logical process according to the fault message of each power cell 15, and running state information is sent to HMI display;
Unit information processing module 124, its input is connected with the output of the 2nd SRAM module 123 with the output of unit communication processing module 125 respectively, its output is connected with the input of the 2nd SRAM module 123 with the input of PWM ripple generation module 122 respectively, running state information for each power cell 15 of receiving element Communications Processor Module 125 forwarding enters input voltage, busbar voltage and fault message, and forward running state information to the 2nd SRAM module 123, and it judges whether to send to PWM ripple generation module 122 to block the order of PWM ripple according to the fault message of each power cell 15,
Unit communication processing module 125, itself and each power cell 15 are bi-directionally connected, it forwards the PWM ripple of each power cell 15 correspondence that PWM ripple generation module 122 generates, and the running state information of its repeating power unit 15 is if input voltage, busbar voltage and fault message are to unit information processing module 124;
Logic DSP main control chip 13 is provided with organizes Wiring port more, Wiring port connects HMI respectively, host computer, user controls I/O signal module, analog input and output module and Systematical control I/O signal module, I/O signal is controlled for the treatment of user, Systematical control I/O signal and 4-20mA analog input and output, user's Human machine interface is provided and carries out communication with host computer, logic DSP main control chip 13 reads the input voltage of RHVC by dual port RAM chip 14, input current, output voltage, output current can be shown to user by HMI, and in input, output voltage is or/and input, when output current is abnormal, send fault or warning message, with reminding user,
Be provided with data acquisition unit in algorithm DSP main control chip 11, data acquisition unit is for gathering the input voltage of RHVC, input current, output voltage, output current and motor rotate speed feedback signal.
The control method of above-mentioned middle high-pressure frequency control two-ways cpu system,
Logical process is carried out in the logic control order of logic DSP main control chip 13 pairs of motors, logic control order is sent to algorithm DSP main control chip 11 and FPGA main control chip 12;
The inversion modulating wave instruction of the V/F of motor or vector control is sent to FPGA main control chip 12 by algorithm DSP main control chip 11;
Inversion modulating wave and the carrier wave that sets in it are made comparisons by FPGA main control chip 12, generate the PWM ripple of each power cell 15;
Power cell 15 receives the corresponding PWM ripple of each power cell 15 that PWM ripple sends to, and carries out V/F or the vector control of motor.
Wherein, the control method of FPGA main control chip 12 is as follows,
The V/F of motor that one SRAM module 121 receiving algorithm DSP main control chip 11 sends or the inversion modulating wave instruction of vector control; And send blockade ripple pwm command to algorithm DSP main control chip 11;
The logic control order of the motor that its receive logic DSP main control chip 13 of the 2nd SRAM module 123 sends; And the running state information of each power cell 15 is sent to logic DSP main control chip 13;
The running state information of each power cell 15 that unit information processing module 124 receiving element Communications Processor Module 125 forwards, and forward running state information to the 2nd SRAM module 123; It judges whether to send to PWM ripple generation module 122 to block the order of PWM ripple according to the fault message of each power cell 15;
Be provided with carrier wave in PWM ripple generation module 122, it receives the inversion modulating wave exported from a SRAM module 121, compares, generate the PWM ripple of each power cell 15 of generation of each power cell 15 with the carrier wave set in it; And send blockade ripple pwm command to a SRAM module 121;
Unit communication processing module 125 forwards the PWM ripple of each power cell 15 sent from PWM ripple generation module 122, and each power cell 15 is according to the PWM ripple received, and each power cell 15 does corresponding actions process; And the running state information of repeating power unit 15 is to unit information processing module 124.
The present invention is not limited to above-mentioned execution mode, and for those skilled in the art, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications are also considered as within protection scope of the present invention.The content be not described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.
Claims (7)
1. a middle high-pressure frequency control two-ways cpu system, it is characterized in that: comprise algorithm DSP main control chip (11), logic DSP main control chip (13), dual port RAM chip (14), power cell (15) and FPGA main control chip (12)
Algorithm DSP main control chip (11), it is connected with described FPGA main control chip (12), it is for being sent to described FPGA main control chip (12) by the inversion modulating wave instruction of the V/F of motor or vector control, and periodically reads the blockade PWM ripple order in described FPGA main control chip (12);
Logic DSP main control chip (13), it is connected with described FPGA main control chip (12), it is for issuing described FPGA main control chip (12) by the logic control order of motor, and the running state information periodically reading in described FPGA main control chip (12) described in each power cell (15);
Dual port RAM chip (14), it is connected with described algorithm DSP main control chip (11), described logic DSP main control chip (13) respectively, for the data communication between described algorithm DSP main control chip (11) and described logic DSP main control chip (13);
FPGA main control chip (12), it is connected with described algorithm DSP main control chip (11), logic DSP main control chip (13) and power cell (15) described in each respectively, the V/F of described motor or the inversion modulating wave instruction of vector control and the carrier wave of its inner setting are compared, generate the PWM ripple that power cell described in each (15) is corresponding, by the logic control order of described motor, carry out integrated logic with the fault message of power cell described in each (15) to judge to produce and block the order of PWM ripple, for the logic control of described motor;
Power cell (15), it connects described FPGA main control chip (12) by optical fiber interface, its receive that described FPGA main control chip (12) exports each described in PWM ripple corresponding to power cell (15), described PWM ripple is for controlling power cell described in each (15) action, realize V/F or the vector control of motor, and its running state information is sent to FPGA main control chip (12).
2. a kind of middle high-pressure frequency control two-ways cpu system as claimed in claim 1, it is characterized in that: described FPGA main control chip (12) comprises a SRAM module (121), PWM ripple generation module (122), the 2nd SRAM module (123), unit information processing module (124), unit communication processing module (125)
One SRAM module (121), itself and described algorithm DSP main control chip (11) are bi-directionally connected, for the inversion modulating wave instruction of the V/F or vector control that receive the motor that described algorithm DSP main control chip (11) sends, and send described blockade ripple pwm command to described algorithm DSP main control chip (11);
PWM ripple generation module (122), its input is connected with the output of described unit information processing module (124) with the output of a described SRAM module (121) respectively, its output is connected with the input of described unit communication processing module (125) with the input of a described SRAM module (121) respectively, it receives the blockade PWM ripple order that the V/F of described motor that exports of a described SRAM module (121) or the inversion modulating wave instruction of vector control and described unit information processing module (124) export, described inversion modulating wave and the carrier wave that sets in it are compared, generate the PWM ripple of each power cell (15), described unit communication processing module (125) is exported to by defeated for described PWM ripple,
2nd SRAM module (123), itself and described logic DSP main control chip (13) are bi-directionally connected, it receives the logic control order of the motor that described logic DSP main control chip (13) sends, and sends the running state information of power cell described in each (15) to described logic DSP main control chip (13);
Unit information processing module (124), its input is connected with the output of described 2nd SRAM module (123) with the output of described unit communication processing module (125) respectively, its output is connected with the input of described 2nd SRAM module (123) with the input of described PWM ripple generation module (122) respectively, for receive that described unit communication processing module (125) forwards each described in the running state information of power cell (15), and forward running state information to described 2nd SRAM module (123), it judges whether to block the order of PWM ripple to the transmission of described PWM ripple generation module (122) according to the fault message of power cell described in each (15),
Unit communication processing module (125), itself and each described power cell (15) are bi-directionally connected, its forward that described PWM ripple generation module (122) generates each described in PWM ripple corresponding to power cell (15), it forwards the running state information of described power cell (15) to described unit information processing module (124).
3. a kind of middle high-pressure frequency control two-ways cpu system as claimed in claim 1, it is characterized in that: described logic DSP main control chip (13) is provided with organizes Wiring port more, described Wiring port connects HMI respectively, host computer, user control I/O signal module, analog input and output module and Systematical control I/O signal module.
4. a kind of middle high-pressure frequency control two-ways cpu system as claimed in claim 1, it is characterized in that: be provided with data acquisition unit in described algorithm DSP main control chip (11), described data acquisition unit is for gathering the input voltage of RHVC, input current, output voltage, output current and motor rotate speed feedback signal.
5. the control method of a kind of middle high-pressure frequency control two-ways cpu system as claimed in claim 1, is characterized in that:
Logical process is carried out in the logic control order of logic DSP main control chip (13) to motor, logic control order is sent to described algorithm DSP main control chip (11) and described FPGA main control chip (12);
The inversion modulating wave instruction of the V/F of motor or vector control is sent to FPGA main control chip (12) by algorithm DSP main control chip (11);
Described inversion modulating wave and the carrier wave that sets in it are made comparisons by FPGA main control chip (12), generate the PWM ripple of power cell described in each (15);
Power cell (15) receive that described PWM ripple sends to each described in the corresponding PWM ripple of power cell (15), carry out V/F or the vector control of motor.
6. control method as claimed in claim 5, it is characterized in that: described FPGA main control chip (12) comprises a SRAM module (121), PWM ripple generation module (122), the 2nd SRAM module (123), unit information processing module (124), unit communication processing module (125)
One SRAM module (121), itself and described algorithm DSP main control chip (11) are bi-directionally connected, for the inversion modulating wave instruction of the V/F or vector control that receive the motor that described algorithm DSP main control chip (11) sends, and send described blockade ripple pwm command to described algorithm DSP main control chip (11);
PWM ripple generation module (122), its input is connected with the output of described unit information processing module (124) with the output of a described SRAM module (121) respectively, its output is connected with the input of described unit communication processing module (125) with the input of a described SRAM module (121) respectively, and PWM ripple generation module (122) receives the blockade PWM ripple order that the V/F of motor that exports of a SRAM module (121) or the inversion modulating wave instruction of vector control and unit information processing module (124) export, described inversion modulating wave and the carrier wave that sets in it are compared, generate the PWM ripple of each power cell (15), described PWM ripple is exported to described unit communication processing module (125),
2nd SRAM module (123), itself and described logic DSP main control chip (13) are bi-directionally connected, it receives the logic control order of the motor that described logic DSP main control chip (13) sends, and sends the running state information of power cell described in each (15) to described logic DSP main control chip (13);
Unit information processing module (124), its input is connected with the output of described 2nd SRAM module (123) with the output of described unit communication processing module (125) respectively, its output is connected with the input of described 2nd SRAM module (123) with the input of described PWM ripple generation module (122) respectively, for receive that described unit communication processing module (125) forwards each described in the running state information of power cell (15), and forward running state information to described 2nd SRAM module (123), it judges whether to block the order of PWM ripple to the transmission of described PWM ripple generation module (122) according to the fault message of power cell described in each (15),
Unit communication processing module (125), itself and each described power cell (15) are bi-directionally connected, its forward that described PWM ripple generation module (122) generates each described in PWM ripple corresponding to power cell (15), it forwards the running state information of described power cell (15) to described unit information processing module (124).
7. control method as claimed in claim 6, is characterized in that: the control method of described FPGA main control chip (12) is as follows,
A described SRAM module (121) receives the V/F of the motor that described algorithm DSP main control chip (11) sends or the inversion modulating wave instruction of vector control; And block ripple pwm command to the transmission of described algorithm DSP main control chip (11);
Described 2nd SRAM module (123) its receive the logic control order of the motor that described logic DSP main control chip (13) sends; And the running state information of power cell described in each (15) is sent to described logic DSP main control chip (13);
Unit information processing module (124) receive that described unit communication processing module (125) forwards each described in the running state information of power cell (15), and forward running state information to described 2nd SRAM module (123); It judges whether to block the order of PWM ripple to the transmission of described PWM ripple generation module (122) according to the fault message of power cell described in each (15);
Carrier wave is provided with in described PWM ripple generation module (122), it receives the inversion modulating wave exported from a described SRAM module (121), compare with the carrier wave set in it, generate the PWM ripple of each power cell of generation (15) of each power cell (15); And send blockade ripple pwm command to a described SRAM module (121);
Unit communication processing module (125) forwards the PWM ripple of each power cell (15) sent from described PWM ripple generation module (122), each power cell (15) is according to the PWM ripple received, and each power cell (15) does corresponding actions process; And forward the running state information of described power cell (15) to described unit information processing module (124).
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Effective date of registration: 20160804 Address after: 432000 No. 2, space Road, Tian Tian Industrial Park, Xiaogan Economic Development Zone, Hubei, China Applicant after: Dayu Electric Technology Co., Ltd. Address before: 12, building 430000, building A3, finance port 77, Optics Valley Avenue, Wuhan, Hubei Applicant before: Dayu Electrical Technology Co., Ltd. |
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