CN105355626A - ESD (electro-static discharge) structure of trench type MOSFET and technological method - Google Patents
ESD (electro-static discharge) structure of trench type MOSFET and technological method Download PDFInfo
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- CN105355626A CN105355626A CN201510648882.7A CN201510648882A CN105355626A CN 105355626 A CN105355626 A CN 105355626A CN 201510648882 A CN201510648882 A CN 201510648882A CN 105355626 A CN105355626 A CN 105355626A
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 230000011218 segmentation Effects 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 abstract 5
- 210000000746 body region Anatomy 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000006735 deficit Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012372 quality testing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an integrated ESD (electro-static discharge) structure of a trench type MOSFET; a trench type protective ring is arranged around the trench type MOSFET; the ESD structure is integrated in a protective ring trench; the protective ring trench passes through the bottom of a body region to be positioned in an epitaxial layer; the trench is filled with polycrystalline silicon; the polycrystalline silicon is subjected into interval doping in subsections of N-P or P-N, or N-P- until -N-P or P-N- until -P-N to form one or more equivalently concatenated diodes; and the electrodes in the first ends and the tail ends of the concatenated diodes are connected with the grid electrode and the source electrode of the trench type MOSFET respectively. According to the ESD structure of the trench type MOSFET, the polycrystalline silicon, with the alternatively-arranged Ns and Ps at intervals, is formed in the protective ring trench to equivalently form the ESD diodes; the two electrodes of the equivalent ESD diodes formed by PN junctions are connected with the source electrode and the grid electrode of the MOSFET respectively through metal leads to form the ESD protection structure of the MOSFET. According to the technological method for the ESD structure of the trench type MOSFET, by the adoption of the protective ring, the procedures of ESD polycrystalline silicon depositing and etching are reduced, so that the processing steps are simplified and the cost is reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, refer to a kind of ESD structure of trench MOSFET especially, the invention still further relates to the process of the ESD structure of described trench MOSFET.
Background technology
ESD (Electro-StaticDischarge) is meant to " static discharge ".ESD formed since being mid-term in 20th century to study the generation of electrostatic, the subject of harm and electrostatic defending etc.Therefore, be accustomed to the equipment being used for electrostatic defending to be referred to as ESD in the world, Chinese is electrostatic impedor.Electrostatic is a kind of natural phenomena of objective reality, and the mode of generation is multiple, as contact, friction, appliance chamber induction etc.The feature of electrostatic be gather for a long time, high voltage, low electricity, small area analysis and action time short feature.
The action of human body self or with the contact of other objects, be separated, rub or the factor such as induction, the electrostatic of several kilovolts of volts even up to ten thousand can be produced.
Electrostatic causes serious harm in multiple field.Triboelectrification and static electricity on human body are that two in electronics industry endangers greatly, usually cause electric equipment products fluctuation of service, even damage.The destruction that ESD causes electronic product and damage have abrupt impairment and latent injury two kinds.So-called abrupt impairment, refers to device and is seriously damaged, afunction.This damage can be able to find in quality testing in process of production usually, therefore to the cost keeped in repair of mainly doing over again that factory brings.And latent injury refers to device portions and damaged, function is not yet lost, and can not find in the detection of production process, but product can be made in the middle of use to become unstable, bad during fashion, thus larger to product quality formation harm.
For the trench MOSFET of integrated esd protection, its source draws PAD and grid draws PAD domain as shown in Figure 1, usual esd protection adopts a-circle-by-a-circle N, P is spaced the PN junction formed as Fig. 3 annular, form diode, schematic diagram as shown in Figure 2, ESD diode is connected in series with between source electrode at the grid of trench MOSFET, ESD polysilicon is positioned at the below (being partial enlarged drawing on the right of Fig. 1) of grid PAD as shown in Figure 1, the general number being converted into PN junction according to the demand of device withstand voltage, then esd protection structure is as shown in Figure 3 made, current mainstay uses groove to do the guard ring of die perimeter, the PN junction guard ring formed is injected with alternative body, the groove of guard ring (only need use regional area to be described in one week around die region in figure, other region illustrated trench are as good as).ESD polysilicon is usually located at the below of grid PAD, constrains the area of grid PAD.
The process of this esd protection structure is: the technique such as groove and grid first completing MOSFET, as shown in Figure 4; And then deposit thick layer about
oxide layer, deposit ESD polysilicon, forms esd protection structure through over etching and ion implantation; as shown in Figure 5,7,8 two extraction electrodes being namely respectively ESD diode in figure, finally by metal interconnection; one end connects grid, and one end connects source electrode, thus forms esd protection circuit.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of ESD structure of trench MOSFET, utilizes guard ring groove to form the PN junction of the serial connection replaced along N, the P in groove direction.
The technical problem that the present invention also will solve is the process of the ESD structure providing described trench MOSFET.
For solving the problem, the ESD structure of trench MOSFET of the present invention, comprise: there is guard ring groove around trench MOSFET, described ESD structure assembly is in the groove of guard ring, described guard ring groove is arranged in epitaxial loayer through bottom tagma, fills polysilicon in groove;
N-P or P-N is carried out in described polysilicon segmentation, or N-P-...-N-P or P-N-... the undoped spacer of-P-N, to form the diode of one or more equivalence serial connection, the diode head and the tail two end electrodes of serial connection connects grid and the source electrode of trench MOSFET respectively.
Further, according to the withstand voltage demand of the ESD of trench MOSFET, be converted into the number of the PN junction of equivalence, determine that in the groove to guard ring, polysilicon carries out the segments injected at N, P interval, the number of the diode of the equivalence namely formed.
The process of the ESD structure of trench MOSFET of the present invention, comprises following step:
1st step, uses hard mask in extension, define guard ring figure, and etching forms the groove of guard ring;
2nd step, removes hard mask, forms layer of oxide layer as gate oxide at whole epitaxial surface;
3rd step, depositing polysilicon in the groove of guard ring also returns quarter to epitaxial surface;
4th step, whole epitaxial surface growth layer of oxide layer, then carries out tagma injection;
5th step, uses the mask plate that source region is injected, or guard ring mask plate carries out the impurity injection of guard ring groove, and according to domain, part of trench is injected transoid, forms the PN junction of the serial connection that N, P are alternately arranged;
6th step, inter-level dielectric deposit, etching forms contact hole, is drawn by polysilicon in groove;
7th step, forms barrier metal, carries out tungsten deposit, makes metal lead wire, is drawn by polysilicon in groove and forms ESD circuit, and be connected with the grid of MOSFET and source electrode respectively at the two ends of this ESD circuit.
In described 1st step, the gash depth of the guard ring of etching is 1 ~ 2 μm.
In described 2nd step, the thickness of the oxide layer of deposit is
In described 3rd step, for NMOS, the polysilicon of deposit in the groove of guard ring is N-type; For PMOS, the polysilicon of deposit in groove is P type; Polysilicon doping concentration is 10
18~ 10
19atoms/cm
3.
In described 4th step, tagma Implantation Energy is 120 ~ 300keV, and dosage is 10
13~ 10
15atoms/cm
2.
In described 7th step, barrier metal is titanium and/or titanium nitride.
The ESD structure of trench MOSFET of the present invention; utilize the groove of guard ring; the polysilicon of N, P alternate intervals arrangement is formed in groove; form the PN junction of one or more serial connection; equivalence becomes ESD diode; and the equivalent ESD diode the two poles of the earth formed by this PN junction by metal lead wire are connected with the source electrode of MOSFET, grid respectively, form the esd protection structure of MOSFET.The process of the ESD structure of trench MOSFET of the present invention, uses the mode of guard ring, decreases ESD polysilicon deposition and etch step, simplify processing step, reduce cost.
Accompanying drawing explanation
Fig. 1 is the domain of the integrated ESD of trench MOSFET;
Fig. 2 is the equivalent circuit diagram of the integrated ESD of MOSFET;
Fig. 3 is the schematic diagram of the esd protection ring of existing trench MOSFET;
Fig. 4 ~ 5 are process schematic representations of the integrated ESD of existing trench MOSFET;
Fig. 6 is the domain schematic diagram of the ESD structure of trench MOSFET of the present invention;
Fig. 7 is the esd protection circular groove grooved profile schematic diagram of the ESD structure of trench MOSFET of the present invention;
Fig. 8 ~ 14 are process sequence diagram of the ESD structure of trench MOSFET of the present invention;
Figure 15 is the processing step flow chart of the ESD structure of trench MOSFET of the present invention.
Description of reference numerals
1 is extension, and 2 is gate oxides, and 3 is polysilicons, and 4 is thick silicon oxide layers, and 5 is gate metals, and 6 is source metals, and 7,8 is the two poles of the earth of ESD diode, and 9 is hard masks, and 10 is tagmas, and 11 is inter-level dielectrics, and a is gash depth.
Embodiment
The ESD structure of trench MOSFET of the present invention, as shown in Figure 6, comprise: around trench MOSFET, have guard ring groove, described ESD structure assembly is in the groove of guard ring, described guard ring groove is arranged in epitaxial loayer through bottom tagma, fills polysilicon in groove;
N-P or P-N is carried out in described polysilicon segmentation, or N-P-...-N-P or P-N-... the undoped spacer of-P-N, to form the diode of one or more equivalence serial connection, its structure as shown in Figure 7, is esd protection circular groove grooved profile schematic diagram.The diode head and the tail two end electrodes of serial connection connects grid and the source electrode of trench MOSFET respectively.As in Fig. 6, the groove of multilayer guard ring is drawn by common electrode 7,8, is connected, forms ESD circuit by the grid of metal and MOSFET and source electrode.
Composition graphs 7, the present invention according to the withstand voltage demand of the ESD of trench MOSFET, can be converted into the number of the PN junction of equivalence, to determine that polysilicon carries out the segments of N, P interval injection, the number of the diode of the equivalence namely formed.
The process of the ESD structure of trench MOSFET of the present invention, comprises following step:
1st step, uses hard mask 9 to define guard ring figure in extension 1, and etching Formation Depth a is the groove of the guard ring of 1 ~ 2 μm; As shown in Figure 8.
2nd step, removes hard mask 9, forms a layer thickness to be on whole extension 1 surface
oxide layer 2 as gate oxide; As shown in Figure 9.
3rd step, as shown in Figure 10, depositing polysilicon 3 in the groove of guard ring also returns quarter to extension 1 surface; For NMOS, the polysilicon of deposit in groove is N-type; For PMOS, the polysilicon of deposit in groove is P type; Polysilicon doping concentration is 10
18~ 10
19atoms/cm
3.
4th step, whole extension 1 superficial growth layer of oxide layer, then carries out tagma 10 and injects, as shown in figure 11; Tagma 10 Implantation Energy is 120 ~ 300keV, and dosage is 10
13~ 10
15atoms/cm
2.
5th step, uses the mask plate that source region is injected, or guard ring mask plate carries out the impurity injection of guard ring groove, and according to domain, part of trench is injected transoid, forms the PN junction of the serial connection that N, P are alternately arranged; As shown in figure 12, there is shown the formation structural representation of groove X-direction and Y-direction, as apparent from Y-direction can trench polisilicon N, P arrangement.
6th step, inter-level dielectric 11 deposit, as shown in figure 13, etching forms contact hole, is drawn by polysilicon in groove.
7th step, forms the barrier metal of titanium and/or titanium nitride, carries out tungsten deposit; make metal lead wire; as shown in figure 14, the polysilicon in guard ring groove is drawn and forms ESD circuit, and the two ends 7,8 of this ESD circuit are connected with the grid of MOSFET and source electrode respectively.ESD structure completes.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. the ESD structure of a trench MOSFET, there is groove-shaped guard ring around trench MOSFET, it is characterized in that: described ESD structure assembly is in the groove of groove-shaped guard ring, and the groove of described guard ring is arranged in epitaxial loayer through bottom tagma, fills polysilicon in groove;
N-P or P-N is carried out in described polysilicon segmentation, or N-P-...-N-P or P-N-... the undoped spacer of-P-N, to form the diode of one or more equivalence serial connection, the diode head and the tail two end electrodes of serial connection connects grid and the source electrode of trench MOSFET respectively.
2. the ESD structure of trench MOSFET as claimed in claim 1; it is characterized in that: according to the withstand voltage demand of the ESD of trench MOSFET; be converted into the number of the PN junction of equivalence; to determine the segments polysilicon in the groove of guard ring being carried out to the injection of N, P interval, the number of the diode of the equivalence namely formed.
3. form the process of the ESD structure of trench MOSFET as claimed in claim 1, it is characterized in that: comprise following step:
1st step, uses hard mask in extension, define guard ring figure, and etching forms the groove of groove-shaped guard ring;
2nd step, removes hard mask, forms layer of oxide layer as gate oxide at whole epitaxial surface;
3rd step, depositing polysilicon in the groove of guard ring also returns quarter to epitaxial surface;
4th step, whole epitaxial surface growth layer of oxide layer, then carries out tagma injection;
5th step, uses the mask plate that source region is injected, or guard ring mask plate carries out the impurity injection of the polysilicon of the groove of guard ring, and according to domain, part of trench is injected transoid, forms the PN junction of the serial connection that N, P are alternately arranged;
6th step, inter-level dielectric deposit, etching forms contact hole, is drawn by polysilicon in groove;
7th step, forms barrier metal, carries out tungsten deposit, makes metal lead wire, is drawn by polysilicon in groove and forms ESD circuit, and be connected with the grid of MOSFET and source electrode respectively at the two ends of this ESD circuit.
4. the process of the ESD structure of trench MOSFET as claimed in claim 3, it is characterized in that: in described 1st step, the gash depth of the guard ring of etching is 1 ~ 2 μm.
5. the process of the ESD structure of trench MOSFET as claimed in claim 3, is characterized in that: in described 2nd step, the thickness of the oxide layer of deposit is
6. the process of the ESD structure of trench MOSFET as claimed in claim 3, it is characterized in that: in described 3rd step, for NMOS, the polysilicon of deposit in groove is N-type; For PMOS, the polysilicon of deposit in groove is P type; Polysilicon doping concentration is 10
18~ 10
19atoms/cm
3.
7. the process of the ESD structure of trench MOSFET as claimed in claim 3, is characterized in that: in described 4th step, tagma Implantation Energy is 120 ~ 300keV, and dosage is 10
13~ 10
15atoms/cm
2.
8. the process of the ESD structure of trench MOSFET as claimed in claim 3, is characterized in that: in described 7th step, barrier metal is titanium and/or titanium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510648882.7A CN105355626B (en) | 2015-10-09 | 2015-10-09 | The ESD structures and process of trench MOSFET |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510648882.7A CN105355626B (en) | 2015-10-09 | 2015-10-09 | The ESD structures and process of trench MOSFET |
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| Publication Number | Publication Date |
|---|---|
| CN105355626A true CN105355626A (en) | 2016-02-24 |
| CN105355626B CN105355626B (en) | 2018-04-17 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI620302B (en) * | 2017-06-06 | 2018-04-01 | 旺宏電子股份有限公司 | Semiconductor structure and method of operation thereof |
| CN107994015A (en) * | 2017-11-13 | 2018-05-04 | 厦门市三安集成电路有限公司 | Electrostatic protection structure and its manufacture method in a kind of monolithic integrated microwave circuit |
| CN108933120A (en) * | 2017-05-23 | 2018-12-04 | 旺宏电子股份有限公司 | Semiconductor structure and its operating method |
| US20180358354A1 (en) * | 2017-06-07 | 2018-12-13 | Macronix International Co., Ltd. | Semiconductor structure and operation method thereof |
| CN109326591A (en) * | 2018-10-08 | 2019-02-12 | 深圳市南硕明泰科技有限公司 | A kind of power device protection chip and its manufacturing method |
| CN110797336A (en) * | 2018-08-02 | 2020-02-14 | 中芯国际集成电路制造（天津）有限公司 | Electrostatic protection circuit, electrostatic protection device and forming method thereof |
| CN111326568A (en) * | 2020-03-10 | 2020-06-23 | 苏州晶界半导体有限公司 | Nitride device with guard ring structure |
| CN112234058A (en) * | 2020-09-24 | 2021-01-15 | 芜湖启源微电子科技合伙企业(有限合伙) | SiC MOSFET device integrated with gate protection structure |
| CN113257674A (en) * | 2021-04-19 | 2021-08-13 | 深圳基本半导体有限公司 | Diode chip structure and manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6407413B1 (en) * | 2000-02-01 | 2002-06-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with guard ring and Zener diode layer thereover |
| CN1787193A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for mfg. electrostatic preventing structure of deep slot type power MOS tube |
-
2015
- 2015-10-09 CN CN201510648882.7A patent/CN105355626B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6407413B1 (en) * | 2000-02-01 | 2002-06-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with guard ring and Zener diode layer thereover |
| CN1787193A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for mfg. electrostatic preventing structure of deep slot type power MOS tube |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108933120B (en) * | 2017-05-23 | 2020-06-30 | 旺宏电子股份有限公司 | Semiconductor structure and operation method thereof |
| CN108933120A (en) * | 2017-05-23 | 2018-12-04 | 旺宏电子股份有限公司 | Semiconductor structure and its operating method |
| TWI620302B (en) * | 2017-06-06 | 2018-04-01 | 旺宏電子股份有限公司 | Semiconductor structure and method of operation thereof |
| US10833151B2 (en) | 2017-06-07 | 2020-11-10 | Macronix International Co., Ltd. | Semiconductor structure and operation method thereof |
| US20180358354A1 (en) * | 2017-06-07 | 2018-12-13 | Macronix International Co., Ltd. | Semiconductor structure and operation method thereof |
| CN107994015B (en) * | 2017-11-13 | 2020-07-17 | 厦门市三安集成电路有限公司 | Electrostatic protection structure in monolithic microwave integrated circuit and manufacturing method thereof |
| CN107994015A (en) * | 2017-11-13 | 2018-05-04 | 厦门市三安集成电路有限公司 | Electrostatic protection structure and its manufacture method in a kind of monolithic integrated microwave circuit |
| CN110797336A (en) * | 2018-08-02 | 2020-02-14 | 中芯国际集成电路制造（天津）有限公司 | Electrostatic protection circuit, electrostatic protection device and forming method thereof |
| CN109326591A (en) * | 2018-10-08 | 2019-02-12 | 深圳市南硕明泰科技有限公司 | A kind of power device protection chip and its manufacturing method |
| CN111326568A (en) * | 2020-03-10 | 2020-06-23 | 苏州晶界半导体有限公司 | Nitride device with guard ring structure |
| CN112234058A (en) * | 2020-09-24 | 2021-01-15 | 芜湖启源微电子科技合伙企业(有限合伙) | SiC MOSFET device integrated with gate protection structure |
| CN113257674A (en) * | 2021-04-19 | 2021-08-13 | 深圳基本半导体有限公司 | Diode chip structure and manufacturing method |
| CN113257674B (en) * | 2021-04-19 | 2023-03-07 | 深圳基本半导体有限公司 | Diode chip structure and manufacturing method |
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| Publication number | Publication date |
|---|---|
| CN105355626B (en) | 2018-04-17 |
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