CN105355618A - Semiconductor package and carrier - Google Patents
Semiconductor package and carrier Download PDFInfo
- Publication number
- CN105355618A CN105355618A CN201410445891.1A CN201410445891A CN105355618A CN 105355618 A CN105355618 A CN 105355618A CN 201410445891 A CN201410445891 A CN 201410445891A CN 105355618 A CN105355618 A CN 105355618A
- Authority
- CN
- China
- Prior art keywords
- semiconductor package
- electric connection
- depressed
- encapsulated layer
- package part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 230000000994 depressogenic effect Effects 0.000 claims description 22
- 238000000034 method Methods 0.000 abstract description 10
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 2
- 238000003466 welding Methods 0.000 abstract 1
- 210000002683 foot Anatomy 0.000 description 18
- 235000012431 wafers Nutrition 0.000 description 17
- 238000010586 diagram Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000000084 colloidal system Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000012447 hatching Effects 0.000 description 4
- 238000012856 packing Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011435 rock Substances 0.000 description 3
- 229910001021 Ferroalloy Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000677 High-carbon steel Inorganic materials 0.000 description 1
- 229910001209 Low-carbon steel Inorganic materials 0.000 description 1
- 229910000954 Medium-carbon steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910001037 White iron Inorganic materials 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- QMQXDJATSGGYDR-UHFFFAOYSA-N methylidyneiron Chemical compound [C].[Fe] QMQXDJATSGGYDR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A semiconductor package and a carrier, the carrier comprising: the plurality of electric connecting pads are provided with a first side and a second side which are opposite, and the first side of the electric connecting pads is provided with a concave part and a peripheral part which surrounds the concave part, so that the electric connecting pads can not sway left and right in the routing process, and the condition that the welding line deviates from a preset position is avoided.
Description
Technical field
The present invention about a kind of encapsulation procedure, espespecially a kind of semiconductor package part and bearing part.
Background technology
Meet along with electronic industry the exhibition of breaking out, many high-order electronic products are all gradually towards toward light, thin, short, little contour aggregation degree future development, and semiconductor package also develops the different circuit module of many kinds.Conventional semiconductor wafer using lead frame (LeadFrame) as chip carrier to form semiconductor packaging part.This lead frame comprises a wafer holder and is formed at the most lead foots around this wafer holder, to be bonded in wafer holder until semiconductor wafer and after being electrically connected this wafer and lead foot with bonding wire, to form the semiconductor package part of this tool lead frame via the inner segment of a potting resin this wafer coated, wafer holder, bonding wire and lead foot.
The kenel of the semiconductor sealing using lead frame as chip carrier and of a great variety, as QFP semiconductor package part (QuadFlatPackage), QFN (Quad-FlatNon-leaded) semiconductor package part, SOP semiconductor package part (SmallOutlinePackage), or DIP semiconductor package part (Dualin-linePackage) etc., and be promote semiconductor package part radiating efficiency with take into account chip-size package (ChipScalePackage, CSP) small size requirement, current is encapsulation main flow mainly with the QFN semiconductor package part exposed bottom wafer holder or dew cushion (ExposedPad) semiconductor package part.
Existing QFN semiconductor package part is a kind of special circuit module, not namely being formed as the outer lead foot for being electrically connected with the external world in existing QFP semiconductor package part, so, will being reduced the size of semiconductor package part, and it combines and adopts surperficial coupling mode.Surface is coupled in semiconductor and printed circuit board (PCB) is done in engaging process, encapsulation unit is directly welded knot on printed circuit board (PCB), and making can fluid-tight engagement without the pin of lead foot semiconductor package part and circuit board.
As shown in Fig. 1 and Figure 1A, existing QFN semiconductor package part 1, its lead frame 10 comprises to be put crystal cup 11 and is multiplely located on this and puts lead foot 12 around crystal cup 11, and put crystal cup 11 end face connects put semiconductor wafer 13 in this, then this semiconductor wafer 13 and each this lead foot 12 is electrically connected with bonding wire 130, packing colloid 14 is formed again afterwards on this lead frame 10, crystal cup 11 is put with coated this, lead foot 12, semiconductor wafer 13 and bonding wire 130, and this wafer holder 11 bottom surface and lead foot 12 bottom surface all expose outside this packing colloid 14, the heat that this semiconductor wafer 13 is produced effectively is transmitted to the external world, and make this QFN semiconductor package part 1 this lead foot 12 exposed surface of mat directly with external device such as printed circuit board (PCB) (scheming summary) is electrically connected.
But, in existing QFN semiconductor package part 1, form this lead foot 12 and this wafer holder 11 by the mode etching (etching) this lead frame 10, so the peripheral region 121 of this lead foot 12 is by the impact of lateral erosion effect, its thickness t is made to be less than the thickness h of the zone line 120 of this lead foot 12, as shown in Figure 1B, namely the peripheral region 121 of this depression is around this zone line 120, so that when routing processing procedure (namely forming this bonding wire 130), this routing machine is easily by the impact of this peripheral region 121, such as this lead foot 12 rolls, thus there is the problem that this bonding wire 130 is partial to precalculated position, or to make because this lead foot 12 rocks this bonding wire 130 cannot firm routing on this lead foot 12, cause this bonding wire 130 that fracture or off-line occur, and then have a strong impact on the reliability of processing procedure.
Therefore, how overcoming the variety of problems of above-mentioned prior art, is an important topic in fact.
Summary of the invention
In view of the disappearance of above-mentioned prior art, the invention provides a kind of semiconductor package part and bearing part, with the situation avoiding bonding wire that skew precalculated position occurs.
This semiconductor package part, it comprises: encapsulated layer, and it has relative first surface and second surface; Multiple electric connection pad, it is embedded in the first surface of this encapsulated layer, and this electric connection pad has the first relative side and the second side, make the first side of this electric connection pad expose to the first surface of this encapsulated layer, the first side of this electric connection pad has depressed part and the outer part around this depressed part again; And electronic component, it to be embedded in this encapsulated layer and to be electrically connected those electric connection pads.
In aforesaid semiconductor package part, the surface of the maximum ga(u)ge of this outer part flushes the first surface of this encapsulated layer.
In aforesaid semiconductor package part, this electronic component is electrically connected those electric connection pads with multiple conductive projection or multiple bonding wire.
The present invention also provides a kind of bearing part, and it comprises: multiple electric connection pad, and it has the first relative side and the second side, and the first side of this electric connection pad has depressed part and the outer part around this depressed part.
In aforesaid semiconductor package part and bearing part, this depressed area is in the middle section of this first side.
In aforesaid semiconductor package part and bearing part, the thickness of this depressed part is less than the thickness of this outer part.
In aforesaid semiconductor package part and bearing part, also comprise and put brilliant pad, it is embedded in this encapsulated layer, and to arrange this electronic component, and those electric connection pads are positioned at this puts brilliant pad around.
As from the foregoing, in semiconductor package part of the present invention and bearing part, main by the design of this outer part around this depressed part, with when the routing processing procedure, this electric connection pad can not roll, and makes this bonding wire that the situation in relatively precalculated position can not occur, and make the firm routing of this bonding wire energy on this electric connection pad because this electric connection pad can not rock, thus can avoid this bonding wire that the situation of fracture or off-line occurs, so compared to prior art, the present invention effectively can promote the reliability of processing procedure.
Accompanying drawing explanation
Fig. 1 is the local upper schematic diagram of existing QFN semiconductor package part (omission packing colloid);
Figure 1A is the schematic diagram of the A-A hatching of Fig. 1;
Figure 1B is the schematic diagram of the B-B hatching of Fig. 1;
Fig. 2 is the local upper schematic diagram of QFN semiconductor package part of the present invention (omission encapsulated layer)
Fig. 2 A is the schematic diagram of the A-A hatching of Fig. 2; And
Fig. 2 B is the schematic diagram of the B-B hatching of Fig. 2.
Symbol description
1,2 semiconductor package parts
10 lead frames
11 put crystal cup
12 lead foots
120 middle sections
121 outer peripheral areas
13 semiconductor wafers
130,230 bonding wires
14 packing colloids
20 bearing parts
21 put brilliant pad
22 electric connection pads
22a first side
22b second side
220 depressed parts
221 outer parts
23 electronic components
24 encapsulated layers
24a first surface
24b second surface
H, h ', t, t ' thickness.
Embodiment
By specific instantiation, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented by other different instantiations or be applied, and the every details in this specification also based on different viewpoints and application, can carry out various modification and change under not departing from spirit of the present invention.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only for coordinating specification to disclose, for understanding and the reading of those skilled in the art, be not intended to limit this and create enforceable qualifications, so the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that this creation can produce and the object that can reach, still all should drop on technology contents that this creation discloses and obtain in the scope that can contain.Simultaneously, quote in this specification as " first ", " second ", " one " and " on " etc. term, also only for ease of understanding of describing, but not create enforceable scope for limiting this, the change of its relativeness or adjustment, under changing technology contents without essence, create enforceable category when being also considered as this.
Fig. 2, Fig. 2 A and Fig. 2 B is the schematic diagram of square planar guide-pin-free of the present invention (QFN) semiconductor package part 2.
As shown in Figure 2, this semiconductor package part 2 comprises: have the encapsulated layer 24 of relative first surface 24a and second surface 24b, be embedded in multiple electric connection pads 22 of this first surface 24a and be embedded in this encapsulated layer 24 and be electrically connected the electronic component 23 of those electric connection pads 22.
Described electric connection pad 22 has the first relative side 22a and the second side 22b, the first side 22a of this electric connection pad 22 is made to expose to the first surface 24a of this encapsulated layer 24, first side 22a of this electric connection pad 22 has depressed part 220 and the outer part 221 around this depressed part 220 again, as shown in Figure 2 B.
In the present embodiment, this depressed part 220 is positioned at the middle section of this first side 20a, this outer part 221 is made to become feet (namely this electric connection pad 22 is in arch table-like), and the thickness h of this depressed part 220 ' distance of this second side 20b (namely with) be less than the thickness t ' of this outer part 221.
In addition, the second side 20b of this electric connection pad 22 is flat surface, and the surface of this outer part 221 flushes the first surface 24a of this encapsulated layer 24.
Again, in time encapsulating, can in conjunction with the conducting element of such as soldering tin material (figure summary) the first side 22a of this electric connection pad 22 on.
Described electronic component 23 with multiple conductive projection (figure slightly) or multiple bonding wire 230 the second side 22b in conjunction with those electric connection pads 22, to be electrically connected those electric connection pads 22.
In the present embodiment, this electronic component 22 is active member, passive device or its combination person, and this active member such as semiconductor wafer, and this passive device such as resistance, electric capacity and inductance.
In addition, this semiconductor package part 2 also comprises puts brilliant pad 21, its the first side 24a being embedded in this encapsulated layer 24 exposes to this first side 24a, to arrange this electronic component 23, and those electric connection pads 22 are positioned at this puts around brilliant pad 21, and make this put brilliant pad 21 to form a bearing part 20 with those electric connection pads 22.
In addition, this bearing part 20 is lead frame, and forms the metal material of material as copper, ferroalloy etc. of this bearing part 20.Such as, this ferroalloy can be selected from mild steel, medium carbon steel, high-carbon steel, casting pig, white iron and any iron carbon bianry alloy being doped into other foreign atom.
In semiconductor package part 2 of the present invention, by the design (namely this depressed part 220 be positioned at the middle section of this first side 20a) of this outer part 221 around this depressed part 220, with in routing processing procedure (namely forming this bonding wire 230) or when covering brilliant processing procedure (namely in conjunction with this conductive projection), this electric connection pad 22 can not roll, so the situation in relatively precalculated position can not be there is in this bonding wire 230, and make the firm routing of this bonding wire 230 energy on this electric connection pad 22 because this electric connection pad 22 can not rock, thus can avoid this bonding wire 230 that the situation of fracture or off-line occurs, therefore, effectively can promote the reliability of processing procedure.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (11)
1. a semiconductor package part, it comprises:
Encapsulated layer, it has relative first surface and second surface;
Multiple electric connection pad, it is embedded in the first surface of this encapsulated layer, and this electric connection pad has the first relative side and the second side, make the first side of this electric connection pad expose to the first surface of this encapsulated layer, the first side of this electric connection pad has depressed part and the outer part around this depressed part again; And
Electronic component, it to be embedded in this encapsulated layer and to be electrically connected those electric connection pads.
2. semiconductor package part as claimed in claim 1, it is characterized by, this depressed area is in the middle section of this first side.
3. semiconductor package part as claimed in claim 1, it is characterized by, the thickness of this depressed part is less than the thickness of this outer part.
4. semiconductor package part as claimed in claim 1, it is characterized by, the surface of the maximum ga(u)ge of this outer part flushes the first surface of this encapsulated layer.
5. semiconductor package part as claimed in claim 1, it is characterized by, this electronic component is electrically connected those electric connection pads with multiple conductive projection or multiple bonding wire.
6. semiconductor package part as claimed in claim 1, is characterized by, and this semiconductor package part also comprises puts brilliant pad, and it is embedded in this encapsulated layer, to arrange this electronic component.
7. semiconductor package part as claimed in claim 6, is characterized by, and those electric connection pads are positioned at this and put brilliant pad around.
8. a bearing part, it comprises:
Multiple electric connection pad, it has the first relative side and the second side, and the first side of this electric connection pad has depressed part and the outer part around this depressed part.
9. bearing part as claimed in claim 8, it is characterized by, this depressed area is in the middle section of this first side.
10. bearing part as claimed in claim 8, it is characterized by, the thickness of this depressed part is less than the thickness of this outer part.
11. bearing parts as claimed in claim 8, is characterized by, and this bearing part also comprises puts brilliant pad, and it is for carrying electronic component, and those electric connection pads are positioned at this puts brilliant pad around.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103128586A TW201608682A (en) | 2014-08-20 | 2014-08-20 | Semiconductor package and carrier member |
| TW103128586 | 2014-08-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105355618A true CN105355618A (en) | 2016-02-24 |
Family
ID=55331557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410445891.1A Pending CN105355618A (en) | 2014-08-20 | 2014-09-03 | Semiconductor package and carrier |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105355618A (en) |
| TW (1) | TW201608682A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030006055A1 (en) * | 2001-07-05 | 2003-01-09 | Walsin Advanced Electronics Ltd | Semiconductor package for fixed surface mounting |
| US20110298126A1 (en) * | 2010-06-04 | 2011-12-08 | Siliconware Precision Industries Co., Ltd. | Carrier-free semiconductor package and fabrication method |
| CN102496608A (en) * | 2011-12-23 | 2012-06-13 | 日月光半导体制造股份有限公司 | Semiconductor packaging possessing clamp part and manufacturing method thereof |
| CN103107145A (en) * | 2011-11-15 | 2013-05-15 | 矽品精密工业股份有限公司 | Semiconductor package, prefabricated lead frame and manufacturing method thereof |
-
2014
- 2014-08-20 TW TW103128586A patent/TW201608682A/en unknown
- 2014-09-03 CN CN201410445891.1A patent/CN105355618A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030006055A1 (en) * | 2001-07-05 | 2003-01-09 | Walsin Advanced Electronics Ltd | Semiconductor package for fixed surface mounting |
| US20110298126A1 (en) * | 2010-06-04 | 2011-12-08 | Siliconware Precision Industries Co., Ltd. | Carrier-free semiconductor package and fabrication method |
| CN103107145A (en) * | 2011-11-15 | 2013-05-15 | 矽品精密工业股份有限公司 | Semiconductor package, prefabricated lead frame and manufacturing method thereof |
| CN102496608A (en) * | 2011-12-23 | 2012-06-13 | 日月光半导体制造股份有限公司 | Semiconductor packaging possessing clamp part and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201608682A (en) | 2016-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102867800B (en) | Functional chip is connected to packaging part to form package on package | |
| US8222716B2 (en) | Multiple leadframe package | |
| TWI495082B (en) | Multi-layer semiconductor package | |
| US9275945B2 (en) | Method of manufacturing semiconductor device and semiconductor device | |
| CN106783792A (en) | There is a kind of plastic-sealed body lateral leads side to climb the encapsulating structure of tin performance | |
| CN102456648B (en) | Method for manufacturing package substrate | |
| PH12014000026B1 (en) | Semiconductor component and method of manufacture | |
| CN107785344A (en) | Electronic package and manufacturing method thereof | |
| CN104766838A (en) | Package stack structure and method for fabricating the same | |
| CN206595254U (en) | There is a kind of plastic-sealed body lateral leads side to climb the encapsulating structure of tin performance | |
| CN105845585A (en) | Chip packaging method and chip packaging structure | |
| KR101474189B1 (en) | Integrated circuit package | |
| US20080185698A1 (en) | Semiconductor package structure and carrier structure | |
| CN103107145A (en) | Semiconductor package, prefabricated lead frame and manufacturing method thereof | |
| JP2005311137A (en) | Semiconductor device, manufacturing method thereof, and lead frame thereof and mounting structure | |
| CN105355618A (en) | Semiconductor package and carrier | |
| CN100481407C (en) | Pin ball grid array encapsulation structure of wafer | |
| US7492037B2 (en) | Package structure and lead frame using the same | |
| CN102751203A (en) | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure | |
| CN201829483U (en) | Lead frame and packaging structure of flipchip thin quad flat non-leaded package (FCTQFN) | |
| CN102832190B (en) | Semiconductor device with flip chip and manufacturing method of semiconductor device | |
| CN101685807B (en) | Heat radiating type semiconductor packaging element and manufacture method thereof | |
| KR100876864B1 (en) | Semiconductor package having bidirectional input / output terminals and manufacturing method thereof | |
| CN104952736A (en) | Quad flat non-leaded package structure and method thereof | |
| CN104299955B (en) | A kind of quad flat non-pin package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160224 |