CN105337606B - The drive circuit with grid clamping of support pressure test - Google Patents
The drive circuit with grid clamping of support pressure test Download PDFInfo
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- CN105337606B CN105337606B CN201410320669.9A CN201410320669A CN105337606B CN 105337606 B CN105337606 B CN 105337606B CN 201410320669 A CN201410320669 A CN 201410320669A CN 105337606 B CN105337606 B CN 105337606B
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Abstract
Embodiments of the present invention are related to the drive circuit with grid clamping of support pressure test.Generator circuit is coupled to apply control signal to the gate terminal of power transistor, to drive output node.Reference voltage is generated, reference voltage is with the first voltage value as the benchmark for controlling signal and with the higher second voltage value for being used in pressure test.Clamp circuit is provided between reference voltage and power crystal tube grid to work in both of which.In one mode, clamp circuit applies the first clamp voltage when generator circuit applies control signal with the voltage progress clamper at the grid to power transistor.In another mode, clamp circuit applies higher second clamp voltage to carry out clamper to the grid of power transistor during gate stress is tested.
Description
Technical field
Present invention relates in general to a kind of electronic circuit more particularly to drive circuits.
Background technology
It is familiar to the person skilled in the art that NMOS work(is used in high-side driver, low-end driver or half-bridge driver topology
The drive circuit of rate transistor designs and implements mode.For example, in high-end embodiment, the leakage of NMOS power transistors
Extreme son is coupled to service voltage node, and the source terminal of NMOS power transistors is coupled to the output section to be driven
Point.The gate terminal of NMOS power transistors is coupled to receive grid control signal, and voltage level is to the NOMOS transistors
It is switched on or the degree of shutdown is controlled.
Many general designs requirements are associated with the design of drive circuit, such as：Ensure that the minimum of NMOS transistor is led
Be powered resistance, and grid control signal is needed with high voltage and preferably the voltage is accurate；B) such as with as electricity
In some proprietary applications of the semibridge system topology of machine driver applications, it may be necessary to limit the electric current at output node；
C) built-in gate stress circuit is provided to ensure the robust operation of drive circuit；D) grid of pair nmos transistor is electric to source electrode
Pressure, which is controlled, to be needed to use clamp circuit (such as with fast transient) in some conditions；And e) ensure clamp circuit
Have no effect on gate stress test.
Meet above all general designs to require to be proved to for circuit designer be one difficult
Task.For example, if circuit designer is using inaccurate grid clamping, clamp voltage will be due to temperature and process corner
Change and shows wide operating voltage range.In fact, in some cases, which may be overlapped to drive circuit
Within normal range of operation and the absolute maximum rating (AMR) of transistor arrangement can be extended through.If designer is another
Outer to select accurate grid clamping, then circuit design becomes extremely complex, this is partially due to need to implement to have in output
The additional circuit device of additional bias current.Still further, needing complicated circuit device and will be driven during pressure test
Dynamic device control circuit device disconnects from the gate terminal of NMOS transistor and further disconnects clamp circuit.
Therefore, this field needs a kind of drive circuit using NMOS power transistors, the circuit to have in normal work
The grid clamping of gate protection (clamper) is all supported during operation mode and during gate stress test pattern.
Invention content
In one embodiment, a kind of circuit includes：Generator circuit is configured as receiving reference voltage in datum node
And control signal is exported to be applied to the gate terminal of power transistor；First current source is configurable to generate the first electricity
It flows to be applied to the datum node；Second current source is configurable to generate the second electric current；Switching circuit is configured as ringing
It should be in gate stress test enable signal and selectively by the second current coupling to the datum node；First resistor device, coupling
It closes between datum node and the driving node of power transistor, reference voltage bridges the first resistor device and generates；Wherein institute
It is variable to state reference voltage, the lower value when pressure test is not enabled with the function as the first electric current and
High value with the function as the first and second electric currents when gate stress test is enabled；And clamp circuit, it is coupling in institute
It states between datum node and the gate terminal of power transistor and is configured as applying the clamper of the function as reference voltage
Voltage.
In one embodiment, a kind of circuit includes：Generator circuit is configured as receiving reference voltage in datum node
And control signal is exported to be applied to the gate terminal for the power transistor for being configured as driving output node；First crystal
Pipe；Second transistor；The source drain path of wherein described first and second transistor be coupled in series in the datum node and
Between the gate terminal of power transistor；Third transistor is coupled with second transistor to form current mirror circuit；With
Four transistors have source drain path and the coupling being coupling between the gate terminal of power transistor and output node
To the gate terminal of the output of current mirror circuit.
In one embodiment, a kind of driving circuit for having the power transistor of gate terminal and leading-out terminal,
Including：Generator circuit, the gate terminal application driving control signal being configured as to power transistor are described defeated to drive
Go out terminal；Reference voltage generator is configured as generating reference voltage in datum node, which has as control letter
Number benchmark the first voltage value and higher second value for being used during pressure test；Be coupling in datum node and
Circuit device between the gate terminal of power transistor, the circuit device is operable for use as variable gate clamp circuit,
It shows：First clamp voltage is applied in when generator circuit applies control signal with the grid to power transistor
The voltage at place carries out clamper；With higher second clamp voltage, generator circuit during gate stress test pattern from
It is applied in the voltage at the grid to power transistor when the grid of power transistor disconnects and carries out clamper.
Description of the drawings
In order to more be fully understood by present disclosure and its advantage, retouched referring now to what is carried out below in conjunction with attached drawing
It states, wherein：
The configuration of drive circuit during Figure 1A diagram normal mode of operation；
The configuration of drive circuit during Figure 1B diagram gate stress test patterns；With
The circuit diagram of Fig. 2 illustrated driver circuits.
Specific implementation mode
Referring now to Figure 1A, during illustrating normal mode of operation (that is, when being operated to be driven to load)
Drive circuit 10 configuration.Drive circuit 10 includes NMOS power transistors 12.The drain electrode of NMOS power transistors 12
(D) terminal is coupled to service voltage node 14, and source electrode (S) terminal of NMOS power transistors be coupled to be driven it is defeated
Egress (OUT) 16.In the illustrated embodiment, and example is only used as not to limit to or limit, drive circuit 10 is
High-side driver and service voltage node 14 are positive supply voltage VB.Grid (G) terminal of NMOS power transistors is coupled to
Transmit the control signal lines 18 of grid control signal.
Grid control signal on circuit 18 is generated by VGS generator circuits 20.Operation for VGS generator circuits
Reference voltage (REF) generated by current source 22, be configured as exporting across resistor R1 and the fixed reference electric current that applies
I1.Current source 22 can for example generate as the fixed reference electric current I1 of the function of band gap voltage (VBG) and make I1=VBG/
RBG (RBG includes band-gap circuit resistance and VGB=1.25V).Resistor R1 is coupling in generates reference voltage (REF) at which
Between node 24 and output node 16.Current source 22 is coupling in the node 24 for generating reference voltage (REF) at which and supply saves
Between point 26.In the illustrated embodiment, and only as an example, supply node 26 is charge pump circuit (being not explicitly shown)
The positive supply voltage VCP generated, wherein VCP ＞ VB (for example, VCP=VB+10V), and to come from VGS generator circuits 20
Grid control signal output can be more than voltage at the drain terminal of NMOS power transistors 12.
VGS generator circuits 20 respond input signal (IN) and are generated with equal to reference voltage (REF)
The grid control signal of maximum voltage.VGS clamp circuits 30 are coupling in the gate terminal and source terminal of NMOS power transistors 12
Between son, and it is used for the maximum voltage clamper on gate terminal being more than reference voltage (REF) but to be less than NMOS power
The numerical value of specified (AMR) voltage of absolute maximum of transistor 12.
Referring now to Figure 1B, which illustrates the configurations of the drive circuit during gate stress test pattern.The circuit is rung
Pressure test pattern should be entered in pressure enable signal (EN), the pressure enable signal is by the output of VGS generator circuits 20
It is disconnected from the gate terminal of NMOS power transistors 12 (in response to signal EN/bar), so that gate terminal floats,
And pressure voltage generator 32 is connected between the gate terminal and source terminal that NMOS power transistors 12 float.Voltage
Generator 32 generates pressure voltage (Vst), is applied in apply pressure to the floating grid terminal of NMOS power transistors 12.
Pressure voltage (Vst) should be more than reference voltage (REF) and should further be preferably more than NMOS power transistors 12
Specified (AMR) voltage of absolute maximum.In this case, VGS clamp circuits 30 are further by from NMOS power transistors
12 floating grid terminal disconnects or alternatively shows the clamp voltage more than specified (AMR) voltage of absolute maximum
And pressure enable signal (EN) is responded.
Referring now to Figure 2, which illustrates the circuit diagrams of drive circuit 110.Drive circuit 110 includes that NMOS power is brilliant
Body pipe 112.Drain electrode (D) terminal of NMOS power transistors 112 is coupled to service voltage node 114, and NMOS power crystals
Source electrode (S) terminal of pipe is coupled to the output node to be driven (OUT).In the illustrated embodiment, it and is only used as and shows
Example and it is unrestricted, drive circuit 110 is high-side driver and service voltage node 114 is positive supply voltage VB.NMOS power
Grid (G) terminal of transistor is coupled to the control signal lines 118 of transmission grid control signal.
Grid control signal on circuit 118 is generated by VGS generator circuits 120.With for VGS generator circuits
The variable reference voltage (VarREF) of lower the first voltage value (V1) of operation generated by the first current source 122, first
Current source 122 is configured as exporting the fixed reference electric current I1 that across resistor R1 is applied.Current source 122 can for example generate work
So that (RBG1 includes first band gap circuit to I1=VBG/RBG1 for the fixed reference electric current I1 of the function of band gap voltage (VBG)
Resistance and VGB=1.25V).Resistor R1 is coupling in the node 124 for generating variable reference voltage (VarREF) at which and output
Between node 116.First current source 122 is coupling in the node 124 and supply node 126 for generating reference voltage (REF) at which
Between.In the illustrated embodiment, and only as an example, supply node 126 (is not explicitly shown) by charge pump circuit
The positive supply voltage VCP generated, wherein VCP ＞ VB (for example, VCP=VB+10V), and to come from VGS generator circuits
120 grid control signal output can be more than the voltage at the drain terminal of NMOS power transistors 112.
VGS generator circuits respond input signal (IN), and generate to have and be equal to variable reference voltage
(VarREF) grid control signal of the maximum voltage of lower the first voltage value (V1).
VGS clamp circuits 130 are coupling between the gate terminal and source terminal of NMOS power transistors 112, and
It is used in normal mode by the maximum voltage clamper on gate terminal being more than reference voltage (REF) but to be less than NMOS power crystalline substances
The value of specified (AMR) voltage of absolute maximum of body pipe 112.VGS clamp circuits 130 include NMOS transistor 132 and PMOS crystal
Pipe 134 has and is coupled in series in the node 124 of generation variable reference voltage (VarREF) at which and in NMOS power transistors
The source drain path between circuit 118 at 112 grid (G) terminal.In the configuration, the source of transistor 132 and 134
Pole is coupled in node 136.The gate terminal of NMOS transistor 132 is coupled to the grid (G) of NMOS power transistors 112
Circuit 118 at terminal.The gate terminal of PMOS transistor 134 is coupled to node 136.In it ＆ apos transistor
132 and 134 are all turned off and their body diode (being not explicitly shown) prevents grid in NMOS power transistors 112
(G) electric current flowing between terminal and node 124.However, as will be described, when as clamp circuit, transistor
132 and 134 conductings.
VGS clamp circuits 130 further comprise PMOS transistor 138, and source drain path is in NMOS power transistors
Between circuit 118 and output node (OUT) 116 at 112 grid (G) terminal, at node 140 resistor R2 connect coupling
It closes.The gate terminal of PMOS transistor 138 is coupled to the gate terminal of PMOS transistor 134 and forms current mirror circuit 142.
VGS clamp circuits 130 further comprise that NMOS transistor 144, drain terminal are coupled to the grid of NMOS power transistors 112
(G) circuit 118 at terminal, and its source terminal is coupled to output node (OUT) 116.The gate terminal of NMOS transistor 144
Son is coupled to node 140.
Drive circuit 110 further comprises that gate stress circuit 132, gate stress circuit 132 include being configured to make a living
At the second current source 150 of fixed reference electric current I2.Current source 150 can for example generate the function as band gap voltage (VBG)
Fixed reference electric current I2 and make I2=VBG/RBG2 (RBG2 include the second band-gap circuit resistance and VGB=1.25V).Switch
Circuit 152 be coupling in the second current source 150 output and at which generate variable reference voltage (VarREF) node 124 it
Between.Switching circuit 152 is controlled by pressure enable signal (EN), and electric current I2 is selectively connectable with during pressure test pattern
And be added with the electric current I1 at node 124 so that across resistor R1 is applied, it is used for variable reference voltage to generate
(VarREF) higher second voltage value (V2).
In the normal manipulation mode of the drive circuit 110 when pressure enable signal (EN) is for instance in logic low,
Switching circuit 152 is opened a way and only across resistor R1 applies electric current I1 in node 124 and generates equal to lower the first voltage value
(V1) variable reference voltage (VarREF), wherein：
VGS clamp circuits 130 show the clamp voltage of the function as transistor 132 and 134 according to following equation
VClamp：
It can be by adjusting the size of transistor 132 so that drain electrode is very small to source voltage.Voltage VGB is stable
's.Therefore, the magnitude of clamp voltage VClamp mainly by the grid of transistor 134 to source voltage and is applied to band gap voltage
The scaling (R1/RBG1) of VBG is influenced.
When the grid of NMOS power transistors 112 is to source voltage (VG-VOUT) be less than VClamp when, transistor 132,
134, it 138 and 144 is turned off.It is used for preventing electric current from node 124 with transistor 132 and 134 associated parasitic body diodes
It is flowed to the circuit 118 at grid (G) terminal of NMOS power transistors 112.VGS clamp circuits 130 therefore not shadow
Grid (G) terminal of NMOS power transistors 112 is rung, and in turn not to 116 Injection Current of output node (OUT).
However, when the grid of NMOS power transistors 112 is to source voltage (VG-VOUT) more than VClamp when, electric current passes through
Circuit 118 of the transistor 132 and 134 from grid (G) terminal of NMOS power transistors 112 is flowed towards node 124.The electricity
Stream is mirrored and across resistor R2 applies by the current mirror 142 by transistor 138, at node 140
Voltage.When the pressure drop rise across resistor R2 to enough levels, the conducting of transistor 144 and by NMOS power transistors 112
Grid (G) terminal pull down.Therefore it is lower that voltage at grid (G) terminal of NMOS power transistors 112 is clamped
One voltage value (V1).In a preferred embodiment, resistor R2 has very high numerical value (for example,~megohm).
When pressure enable signal (EN) for instance in it is logically high when drive circuit 110 gate stress test pattern
In, switching circuit 152 is closed and across resistor R1 applies electric current I1 and electric current I2 in node 124 and generates equal to higher the
The variable reference voltage (VarREF) of two voltage values (V2), wherein：
Logically high pressure enable signal (EN) is by the output of VGS generator circuits 120 from NMOS power transistors 112
Gate terminal disconnects (in response to signal EN/bar), so that the gate terminal of transistor 112 floats.At this point it is possible to
Pressure test voltage is applied to gate terminal using pressure test voltage source (for example, with reference to the label 32 in Figure 1B).It is in
The variable reference voltage (VarREF) of higher second value (V2) be used for being lifted at voltage on 130 other side of clamp circuit and
Increase VClamp voltages.Which ensure that clamp circuit will not be applied to transistor 112 in pressure test voltage (Vst) by power supply 32
Gate terminal when be undesirably connected.
If the grid of NMOS power transistors 112 is to source voltage (VG-VOUT) it is less than the VClamp levels after increasing,
There is no electric current on the gate terminal of transistor 112 then and therefore clamp circuit 130 does not have shadow for gate stress test pattern
It rings.
If the grid of NMOS power transistors 112 is to source voltage (VG-VOUT) horizontal more than the VClamp after increasing,
Although being then applied with pressure test voltage, electric current is still through transistor 134 and 144 and from the gate terminal subflow of transistor 112
Grid voltage is clamped down on into the levels of the VClamp after increase to node 124.
Drive circuit shows a variety of advantages：A) due to for reference voltage there is only a current path,
So benchmark and clamper are merged to reduce the electric current in output by the circuit；B) since transistor 132 and 134 passes through two
A back-to-back diode provides isolation and makes the clamp circuit only ability when grid voltage is more than variable reference voltage (VarREF)
It is active, to AMR, grid to source voltage, gate stress are tested and are worked normally with 124 relevant clamper of node
All there is enough accuracy, and further clamper has no effect on normal work for all scenario；C) circuit passes through increasing
Biasing on big node 124 and operated with gate stress test and improved clamper level to desired value, keep away simultaneously
The circuit configuration disconnected is exempted from；D) the MOSFET equipment (132,134,138) of circuit is not needed to grid to source electrode electricity
Pressure carries out Additional Protection (they are self-protectings).
Skilled persons will note that there are two circuits when clamp circuit is activated.There are negative-feedbacks to return
Road has the electricity via transistor 138 and 144 and resistor R2 to output node 116 from the gate terminal of transistor 122
Stream.There is also positive feedback loop, have from the grid of transistor 112 to the electric current of node 124, it will be so that at node 124
Voltage increased and therefore improve clamp voltage level.Positive feedback current is conducted before negative feedback current.By right
The value of resistor R1 and transistor 144 is appropriately arranged with, and can pass through transistor 144 very small forward direction nA electric currents
Generate the pull-down current of number mA.Clamper is acted sufficiently strong and is protected to the grid of power transistor 112.
Although being shown by way of example to drive circuit 110 using high-end topology in Fig. 2, will manage
Solution, those skilled in the art can be directed to low side topology and semibridge system topology implements the design.
Those skilled in the art will readily appreciate that material and method can be varied from and be still within model of the invention
Within enclosing.It is further appreciated that the present invention provides can for many other than the specific environment that is illustrated to embodiment
The creative concept of application.Therefore, appended claims are intended to such processing, machine, manufacture, substance combination, means, side
Method or step are included within the scope of it.
Claims (21)
1. a kind of electronic circuit, including：
Generator circuit is configured as receiving reference voltage in datum node and exports control signal to be applied to power crystalline substance
The gate terminal of body pipe；
First current source is configurable to generate the first electric current to be applied to the datum node；
Second current source is configurable to generate the second electric current；
Switching circuit, be configured to respond to gate stress test enable signal and selectively extremely by second current coupling
The datum node；
First resistor device is coupling between the datum node and the driving node of the power transistor, the reference voltage
It is generated across the first resistor device；
The wherein described reference voltage is variable, when pressure test is not enabled with the function as first electric current
Lower value, and gate stress test be enabled when with as the function of first electric current and second electric current compared with
High level；And
Clamp circuit is coupling between the datum node and the gate terminal of the power transistor and is configured as
Apply the clamp voltage of the function as the reference voltage.
2. circuit according to claim 1 further comprises that the power transistor, the power transistor have described
Gate terminal and the source drain path for being coupled to the driving node.
3. circuit according to claim 1, wherein the clamp circuit includes：
The first transistor；
Second transistor；
The source drain path of the wherein described the first transistor and the second transistor be coupled in series in the datum node and
Between the gate terminal of the power transistor.
4. circuit according to claim 3, wherein the clamp circuit further comprises：
It is coupled to the gate terminal of the first transistor of the gate terminal of the power transistor；And
It is coupled to described the second of the intermediate node of the series coupled point in the first transistor and the second transistor
The gate terminal of transistor.
5. circuit according to claim 4, wherein the clamp circuit further comprises that third transistor, the third are brilliant
Body pipe is coupled with the second transistor to form current mirror circuit.
6. circuit according to claim 5, wherein the clamp circuit further comprises second resistor, second electricity
Hinder source electrode-leakage of the device between the gate terminal and the driving node of the power transistor with the third transistor
Pole path coupled in series.
7. circuit according to claim 6, wherein the clamp circuit further comprises the 4th transistor, the described 4th is brilliant
Body pipe have be coupling in the source drain path between the gate terminal of the power transistor and the driving node with
And it is coupled to the gate terminal of the second resistor.
8. circuit according to claim 1, wherein the generator circuit is configured to respond to input signal and generates
The control signal is to be applied to the gate terminal of the power transistor.
9. circuit according to claim 1, wherein the generator circuit is configured to be made in pressure test
It is disconnected from the gate terminal of the power transistor when energy.
10. circuit according to claim 1, wherein the clamp voltage it is relatively low when pressure test is not enabled and
Gate stress test is higher when being enabled.
11. a kind of electronic circuit, including：
Generator circuit is configured as receiving reference voltage in datum node and exporting control signal being configured to be applied to
For the gate terminal of the power transistor of driving output node；
The first transistor；
Second transistor；
The source drain path of the wherein described the first transistor and the second transistor be coupled in series in the datum node and
Between the gate terminal of the power transistor；
Third transistor is coupled with the second transistor to form current mirror circuit；And
4th transistor has the source being coupling between the gate terminal of the power transistor and the output node
Gate-drain path and be coupled to the current mirror circuit output gate terminal.
12. circuit according to claim 11 further comprises that the power transistor, the power transistor have institute
State gate terminal and the source drain path for being coupled to the output node.
13. circuit according to claim 11 further comprises that resistor, the resistor are coupling in the datum node
Between the driving node of the power transistor, the reference voltage is generated across the resistor.
14. circuit according to claim 13, further comprises：
First current source is configurable to generate the first electric current to be applied to the datum node；
Second current source is configurable to generate the second electric current；
Switching circuit is configured to respond to pressure test enable signal and selectively by second current coupling to described
Datum node；
The reference voltage at the wherein described datum node has when pressure test is not enabled is used as first electric current
Function lower value, and when pressure test is enabled with the function as first electric current and second electric current
High value.
15. circuit according to claim 14, wherein the generator circuit is configured as when pressure test is enabled
It is disconnected from the gate terminal of the power transistor.
16. circuit according to claim 11, further comprise the output for being coupling in the current mirror circuit and described
Resistor between output node.
17. circuit according to claim 11, wherein the first transistor and the second transistor are in response to pressure
It tests enable signal and applies variable clamp voltage to the gate terminal of the power transistor, the variable clamper
Voltage is relatively low when pressure test is not enabled and higher when gate stress test is enabled.
18. it is a kind of for the driving circuit with gate terminal and the power transistor of leading-out terminal, including：
Generator circuit is configured as applying driving control signal to the gate terminal of the power transistor to drive
The leading-out terminal；
Reference voltage generator is configured as generating reference voltage in datum node, and the reference voltage, which has, is used as the control
The first voltage value of the benchmark of signal processed and with higher second voltage value for being used during pressure test；
The circuit device being coupling between the datum node and the gate terminal of the power transistor, the circuit dress
Set operable for use as variable gate clamp circuit, the variable gate clamp circuit is shown：
First clamp voltage is applied in when the generator circuit applies the control signal with to the power transistor
Voltage at the grid carries out clamper；And
Higher second clamp voltage, in the generator circuit from the power transistor during gate stress test pattern
The grid be applied in when disconnecting clamper carried out with the voltage at the grid to the power transistor.
19. driving circuit according to claim 18, wherein the circuit device includes：
The first transistor has the gate terminal for the gate terminal for being coupled to the power transistor；With
Second transistor；
The source drain path of the wherein described the first transistor and the second transistor be coupled in series in the datum node and
Between the gate terminal of the power transistor.
20. driving circuit according to claim 19, wherein the circuit device further comprises：
Third transistor is coupled with the second transistor to form current mirror circuit；And
4th transistor has the source being coupling between the gate terminal of the power transistor and the leading-out terminal
Gate-drain path and be coupled to the current mirror circuit output gate terminal.
21. driving circuit according to claim 18, wherein the reference voltage generator includes：
First current source is configurable to generate the first electric current to be applied to the datum node；
Second current source is configurable to generate the second electric current；
Switching circuit is configured to respond to pressure test enable signal and selectively by second current coupling to described
Datum node；
Wherein the first voltage value is to be arranged to first electric current when the generator circuit applies the control signal
The lower value of function, and the wherein described second voltage value be in the generator circuit during gate stress test pattern from
The grid of the power transistor is arranged to the function of first electric current and second electric current when disconnecting
High value.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810875748.4A CN109039328B (en) | 2014-06-30 | 2014-06-30 | Driver circuit with gate clamp supporting stress test |
| CN201410320669.9A CN105337606B (en) | 2014-06-30 | 2014-06-30 | The drive circuit with grid clamping of support pressure test |
| US14/449,232 US9331672B2 (en) | 2014-06-30 | 2014-08-01 | Driver circuit with gate clamp supporting stress testing |
| US15/088,898 US9490786B2 (en) | 2014-06-30 | 2016-04-01 | Driver circuit with gate clamp supporting stress testing |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410320669.9A CN105337606B (en) | 2014-06-30 | 2014-06-30 | The drive circuit with grid clamping of support pressure test |
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| CN201810875748.4A Division CN109039328B (en) | 2014-06-30 | 2014-06-30 | Driver circuit with gate clamp supporting stress test |
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| CN105337606A CN105337606A (en) | 2016-02-17 |
| CN105337606B true CN105337606B (en) | 2018-08-31 |
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| CN201410320669.9A Active CN105337606B (en) | 2014-06-30 | 2014-06-30 | The drive circuit with grid clamping of support pressure test |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10168363B1 (en) * | 2018-03-14 | 2019-01-01 | STMicroelectronics Design & Application S.R.O. | Current sensor with extended voltage range |
| US10901045B2 (en) * | 2018-03-16 | 2021-01-26 | Infineon Technologies Ag | Battery diagnostics system and method using second path redundant measurement approach |
| US11302859B2 (en) * | 2018-09-20 | 2022-04-12 | Boréas Technologies Inc. | Zero-power wake-up sensing circuit in piezoelectric haptic feedback |
| EP3644501B1 (en) * | 2018-10-24 | 2021-12-15 | ams International AG | Output driver with reverse current blocking capabilities |
| US10726881B1 (en) * | 2019-04-08 | 2020-07-28 | Texas Instruments Incorporated | Supply voltage clamping for improved power supply rejection ratio |
| US10855258B1 (en) * | 2019-08-16 | 2020-12-01 | Cirrus Logic, Inc. | Voltage control |
| US11651819B2 (en) * | 2020-07-24 | 2023-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and method of operating the same |
| CN113760032B (en) * | 2021-09-18 | 2022-11-08 | 普冉半导体(上海)股份有限公司 | Low-power consumption clamping circuit |
| CN115987266B (en) * | 2023-01-16 | 2023-11-28 | 深圳市思远半导体有限公司 | Switching circuit, control method and chip of NMOS switching tube |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204180046U (en) * | 2014-06-30 | 2015-02-25 | 意法半导体研发(深圳)有限公司 | Electronic circuit and drive circuit |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6049445A (en) * | 1998-09-18 | 2000-04-11 | International Business Machines Corporation | Overvoltage and electrostatic discharge protection for a receiver circuit |
| US7439796B2 (en) * | 2006-06-05 | 2008-10-21 | Texas Instruments Incorporated | Current mirror with circuitry that allows for over voltage stress testing |
| US7589945B2 (en) * | 2006-08-31 | 2009-09-15 | Freescale Semiconductor, Inc. | Distributed electrostatic discharge protection circuit with varying clamp size |
| JP4851357B2 (en) * | 2007-02-09 | 2012-01-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and test method thereof |
| US8030986B2 (en) * | 2009-08-28 | 2011-10-04 | Freescale Semiconductor, Inc. | Power transistor with turn off control and method for operating |
| DE102009047670B4 (en) * | 2009-12-08 | 2020-07-30 | Robert Bosch Gmbh | Circuit device with a semiconductor component |
| JP2012085382A (en) * | 2010-10-07 | 2012-04-26 | Toyota Motor Corp | Overcurrent protection apparatus |
| JP5464196B2 (en) * | 2011-11-18 | 2014-04-09 | 株式会社デンソー | Power semiconductor element drive circuit |
| US8729950B2 (en) * | 2012-05-30 | 2014-05-20 | Fairchild Semiconductor Corporation | High voltage clamp circuit |
| US8736316B2 (en) * | 2012-10-12 | 2014-05-27 | Allegro Microsystems, Llc | Current driver with output current clamping |
-
2014
- 2014-06-30 CN CN201810875748.4A patent/CN109039328B/en active Active
- 2014-06-30 CN CN201410320669.9A patent/CN105337606B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204180046U (en) * | 2014-06-30 | 2015-02-25 | 意法半导体研发(深圳)有限公司 | Electronic circuit and drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105337606A (en) | 2016-02-17 |
| CN109039328A (en) | 2018-12-18 |
| CN109039328B (en) | 2022-08-26 |
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Address after: 5 / F East B501, South B502, North B503, 6th floor, block B, TCL Industrial Research Institute building, No. 006, Gaoxin South 1st Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: STMicroelectronics (Shenzhen) R&D Co.,Ltd. Address before: 518057, 4/5 building, B block, South SKYWORTH building, South Zone, Shenzhen hi tech Zone, Nanshan District science and Technology Park, Guangdong, China Patentee before: STMicroelectronics (Shenzhen) R&D Co.,Ltd. |