CN105336596B - A kind of preparation method of high-k boundary layer - Google Patents
A kind of preparation method of high-k boundary layer Download PDFInfo
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- CN105336596B CN105336596B CN201510624053.5A CN201510624053A CN105336596B CN 105336596 B CN105336596 B CN 105336596B CN 201510624053 A CN201510624053 A CN 201510624053A CN 105336596 B CN105336596 B CN 105336596B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 41
- 230000007704 transition Effects 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 239000000243 solution Substances 0.000 claims abstract description 22
- 239000000126 substance Substances 0.000 claims abstract description 21
- 229910052735 hafnium Inorganic materials 0.000 claims abstract description 15
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 239000011259 mixed solution Substances 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 43
- 229910052681 coesite Inorganic materials 0.000 claims description 23
- 229910052906 cristobalite Inorganic materials 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 23
- 229910052682 stishovite Inorganic materials 0.000 claims description 23
- 229910052905 tridymite Inorganic materials 0.000 claims description 23
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 19
- 125000002887 hydroxy group Chemical group [H]O* 0.000 claims description 12
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 8
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 4
- 229910018557 Si O Inorganic materials 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 claims description 2
- 238000005406 washing Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of preparation method of high-k boundary layer, including：Step S1：Silicon-based substrate is provided, and utilizes H2SO4And H2O2Mixed solution silicon-based substrate is cleaned；Step S2：Silicon-based substrate is cleaned using RCA ablutions；Step S3：Silicon-based substrate is cleaned using HF solution；Step S4：SiO is grown using thermal oxidation method2/ SiON transition zones；Step S5：SiO is cleaned using SC1 chemical solution cleans technique2/ SiON transition zones；Step S6：In the SiO Jing Guo SC1 chemical solution cleans2Depositing high dielectric constant gate dielectric layer on/SiON transition zones.The high-k boundary layer obtained by the preparation method of the present invention can effectively reduce the interface state density of high-k boundary layer, and improve the property of hafnium base gate dielectric layer then grown, and then improve the performance of device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of preparation methods of high-k boundary layer.
Background technology
With the continuous development of large scale integrated circuit technology, the metal oxide as si-substrate integrated circuit core devices
The characteristic size of semiconductor field effect transistor (MOSFET) always complies with Moore's Law and constantly reduces, then must reduce grid
The thickness of pole dielectric layer reduces the good performance of length holding of grid to utilize.But existing field-effect transistor (MOS)
Gate dielectric layer thickness it is less and less, already close to its limit value.So in order to reduce electric leakage of the grid, high-k is used
(k) gate dielectric layer, you can allow under smaller physical thickness, equally keep identical effective thickness.
In order to reduce the interface state density between high-dielectric-coefficient grid medium layer and silicon-based substrate, generally by the two it
Between add in one layer of gate medium transition zone almost without defect, such as SiO2/ SiON is commonly called as high-k boundary layer.But by
In the high-k boundary layer only grown by conventional thermal oxidation method be not easy with the hafnium base gate dielectric material of high-k it
Between formed Hf-Si-O mixed structure so that interface state density between the two is excessively high, so influence device performance.
Seek a kind of interface state density that can effectively reduce between the hafnium based dielectric material of high-k and silicon-based substrate
The preparation method of high-k boundary layer become one of the technical issues of those skilled in the art are urgently to be resolved hurrily.
Therefore in view of the problems of the existing technology, this case designer actively studies by the experience of the industry for many years is engaged in
Improvement then has a kind of preparation method of high-k boundary layer of the invention.
Invention content
High-k boundary layer the present invention be directed in the prior art, only be grown by conventional thermal oxidation method be not easy with
The mixed structure of Hf-Si-O is formed between the hafnium base gate dielectric material of high-k so that interface state density between the two
It is excessively high, and then provide a kind of preparation method of high-k boundary layer the defects of the performance of influence device.
Purpose to realize the present invention, the present invention provide a kind of preparation method of high-k boundary layer, the Gao Jie
The preparation method of electric constant boundary layer, including：
Perform step S1：Silicon-based substrate is provided, and utilizes H2SO4And H2O2Mixed solution to the silicon-based substrate carry out
Cleaning；
Perform step S2：The silicon-based substrate is cleaned using RCA ablutions；
Perform step S3：The silicon-based substrate is cleaned using HF solution；
Perform step S4：SiO is grown using thermal oxidation method2/ SiON transition zones；
Perform step S5：Using SC1 (NH4OH/H2O2/H2O) chemical solution cleans technique cleans the SiO2/SiON mistakes
Cross layer；
Perform step S6：In the SiO Jing Guo SC1 chemical solution cleans2Depositing high dielectric constant grid are situated between on/SiON transition zones
Matter layer.
Optionally, the SiO obtained after step S4 is performed2The thickness of/SiON transition zones is 0~10 angstrom.
Optionally, the SiO after step S5 is performed2/ SiON transition zones have hydroxyl (- OH).
Optionally, the SiO with hydroxyl (- OH)2The thickness of/SiON transition zones is 0~8 angstrom.
Optionally, the thermal oxidation method growth SiO2/ SiON transition zones, further comprise tropical resources, pecvd nitride
Attached doping process.
Optionally, using SC1 (NH4OH/H2O2/H2O) chemical solution cleans technique cleans the SiO2/ SiON transition zones,
Further comprise the cleaning method with doping property.
Optionally, the cleaning method of the doping property makes boundary layer for Siconi wash cycles method and chemical oxidation mode
Adulterate fluorine (F) element.
Optionally, the high-dielectric-coefficient grid medium layer is hafnium base gate dielectric layer.
In conclusion the high-k interface obtained by the preparation method of high-k boundary layer of the present invention
Layer can effectively reduce the interface state density of high-k boundary layer, and improve the hafnium base gate dielectric layer then grown
Property, and then improve the performance of device.
Description of the drawings
Fig. 1 show the flow chart of the preparation method of high-k boundary layer of the present invention；
Fig. 2 show the high-k boundary layer obtained by the preparation method of high-k boundary layer of the present invention
With the comparison figure of the interface state density of traditional high-k boundary layer.
Specific embodiment
For the present invention will be described in detail create technology contents, construction feature, institute's reached purpose and effect, below in conjunction with reality
It applies example and attached drawing is coordinated to be described in detail.
In the present invention, in order to reduce the interface state density between high-dielectric-coefficient grid medium layer and silicon-based substrate, preferably
Ground sets high-k boundary layer between the high-dielectric-coefficient grid medium layer and the silicon-based substrate.Without limitation,
The high-dielectric-coefficient grid medium layer is hafnium base gate dielectric layer.The high-k boundary layer is SiO2/ SiON transition zones, and
The SiO2/ SiON transition zones have hydroxyl (- OH).
Referring to Fig. 1, Fig. 1 show the flow chart of the preparation method of high-k boundary layer of the present invention.The Gao Jie
The preparation method of electric constant boundary layer, including：
Perform step S1：Silicon-based substrate is provided, and utilizes H2SO4And H2O2Mixed solution to the silicon-based substrate carry out
Cleaning；
Perform step S2：The silicon-based substrate is cleaned using RCA ablutions；
Perform step S3：The silicon-based substrate is cleaned using HF solution；
Perform step S4：SiO is grown using thermal oxidation method2/ SiON transition zones；
Perform step S5：Using SC1 (NH4OH/H2O2/H2O) chemical solution cleans technique cleans the SiO2/ SiON transition
Layer；
Perform step S6：In the SiO Jing Guo SC1 chemical solution cleans2Depositing high dielectric constant grid are situated between on/SiON transition zones
Matter layer.
In order to more intuitively disclose the technical solution of the present invention, the advantageous effect of the present invention is highlighted, in conjunction with specific implementation
Mode is illustrated the method and principle of the present invention.In a specific embodiment, the thickness of the high-k boundary layer,
Process is only to enumerate, and is not construed as the limitation to technical solution of the present invention.The preparation side of the high-k boundary layer
Method, including：
Perform step S1：Silicon-based substrate is provided, and utilizes H2SO4And H2O2Mixed solution to the silicon-based substrate carry out
Cleaning, to remove the organic matter on silicon-based substrate surface；
Perform step S2：The silicon-based substrate is cleaned using RCA ablutions；Wherein, RCA ablutions can be tradition
Wet chemical cleans method, it will not be described here.
Perform step S3：The silicon-based substrate is cleaned using HF solution, to effectively remove silicon-based substrate surface
Native oxide, so as to reduce the thickness of boundary layer；
Perform step S4：SiO is grown using thermal oxidation method2/ SiON transition zones；
Perform step S5：Using SC1 (NH4OH/H2O2/H2O) chemical solution cleans technique cleans the SiO2/ SiON transition
Layer, so that the SiO2/ SiON transition zones have hydroxyl (- OH)；
Perform step S6：In the SiO Jing Guo SC1 chemical solution cleans2Depositing high dielectric constant grid are situated between on/SiON transition zones
Matter layer.For example, the dielectric layer of high dielectric constant is hafnium base gate dielectric layer.
More specifically, for example in the step S4, the thermal oxidation method grows SiO2/ SiON transition zones further wrap
Include the attached doping process of tropical resources, pecvd nitride.The SiO2The thickness of/SiON transition zones is 0~10 angstrom.In the step
In rapid S5, using SC1 (NH4OH/H2O2/H2O) chemical solution cleans technique cleans the SiO2/ SiON transition zones, so that institute
State SiO2/ SiON transition zones have hydroxyl (- OH), the SiO with hydroxyl (- OH)2The thickness of/SiON transition zones is 0~8
Angstrom.In step s 5, using SC1 (NH4OH/H2O2/H2O) chemical solution cleans technique cleans the SiO2/ SiON transition zones, into
One step include with doping property cleaning method and other chemical cleaning technologies, such as existing Siconi wash cycles method and
Chemical oxidation mode makes boundary layer adulterate fluorine (F) element, to improve the NBTI effects of device.
Referring to Fig. 2, and it show the preparation method by high-k boundary layer of the present invention with reference to refering to Fig. 1, Fig. 2
The comparison figure of the high-k boundary layer obtained and the interface state density of traditional high-k boundary layer.As this field
Technical staff, it is readily appreciated that ground by step S4, i.e., grows SiO using thermal oxidation method2After/SiON transition zones, step is performed
S5, using SC1 (NH4OH/H2O2/H2O) chemical solution cleans technique cleans the SiO2/ SiON transition zones, so that described
SiO2/ SiON transition zones have hydroxyl (- OH), the SiO2The hydroxyl (- OH) of/SiON transition zones is easy to being used as high dielectric normal
The hafnium base gate dielectric layer of number forms the mixed structure of Hf-Si-O, so as to improve interface state between the two, it will be apparent that reduces boundary
The face density of states, and the property of hafnium base gate dielectric layer film then grown is improved, improve device performance.
It is apparent that the high-k boundary layer obtained by the preparation method of high-k boundary layer of the present invention,
The interface state density of high-k boundary layer can be effectively reduced, and improves the property of hafnium base gate dielectric layer then grown
Matter, and then improve the performance of device.
In conclusion the high-k interface obtained by the preparation method of high-k boundary layer of the present invention
Layer can effectively reduce the interface state density of high-k boundary layer, and improve the hafnium base gate dielectric layer then grown
Property, and then improve the performance of device.
Those skilled in the art, can be to this hair it will be appreciated that without departing from the spirit or scope of the present invention
It is bright to carry out various modifications and modification.Thus, if any modification or modification fall into the protection of the appended claims and equivalent
In the range of when, it is believed that the present invention covers these modifications and variations.
Claims (8)
1. a kind of preparation method of high-k boundary layer, the high-k boundary layer are located at hafnium base gate dielectric layer and silicon
Between base substrate, which is characterized in that the preparation method of the high-k boundary layer, including：
Perform step S1：Silicon-based substrate is provided, and utilizes H2SO4And H2O2Mixed solution the silicon-based substrate is cleaned；
Perform step S2：The silicon-based substrate is cleaned using RCA ablutions；
Perform step S3：The silicon-based substrate is cleaned using HF solution；
Perform step S4：SiO is grown using thermal oxidation method2/ SiON transition zones；
Perform step S5：Using SC1 (NH4OH/H2O2/H2O) chemical solution cleans technique cleans the SiO2/ SiON transition zones,
So that the SiO2/ SiON transition zones have hydroxyl (- OH), further using Siconi wash cycles method and chemical oxidation side
Formula makes boundary layer adulterate fluorine (F) element, to improve the NBTI effects of device, the SiO2The hydroxyl (- OH) of/SiON transition zones with
The hafnium base gate dielectric layer forms the mixed structure of Hf-Si-O；
Perform step S6：In the SiO Jing Guo SC1 chemical solution cleans2Depositing high dielectric constant gate dielectric layer on/SiON transition zones.
2. the preparation method of high-k boundary layer as described in claim 1, which is characterized in that the institute after step S4 is performed
The SiO of acquisition2The thickness of/SiON transition zones is 0~10 angstrom.
3. the preparation method of high-k boundary layer as described in claim 1, which is characterized in that the institute after step S5 is performed
State SiO2/ SiON transition zones have hydroxyl (- OH).
4. the preparation method of high-k boundary layer as claimed in claim 3, which is characterized in that it is described have hydroxyl (-
OH SiO)2The thickness of/SiON transition zones is 0~8 angstrom.
5. the preparation method of high-k boundary layer as described in claim 1, which is characterized in that the thermal oxidation method growth
SiO2/ SiON transition zones further comprise the attached doping process of tropical resources, pecvd nitride.
6. the preparation method of high-k boundary layer as described in claim 1, which is characterized in that using SC1 (NH4OH/
H2O2/H2O) chemical solution cleans technique cleans the SiO2/ SiON transition zones further comprise the cleaning with doping property
Method.
7. the preparation method of high-k boundary layer as claimed in claim 6, which is characterized in that described to adulterate the clear of property
Washing method makes boundary layer adulterate fluorine (F) element for Siconi wash cycles method and chemical oxidation mode.
8. the preparation method of the high-k boundary layer as described in claim 1~7 any claim, which is characterized in that
The high-dielectric-coefficient grid medium layer is hafnium base gate dielectric layer.
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| CN105336596B true CN105336596B (en) | 2018-06-26 |
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| CN106328496B (en) * | 2016-10-27 | 2019-08-23 | 上海华力微电子有限公司 | A kind of preparation method of high K boundary layer |
| CN106653589A (en) * | 2016-12-16 | 2017-05-10 | 上海华力微电子有限公司 | High-pressure and low-thermal budget high-K post-annealing process |
| CN109003879B (en) * | 2017-06-06 | 2021-03-19 | 中芯国际集成电路制造(上海)有限公司 | Forming method of gate dielectric layer |
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|---|---|---|---|---|
| CN102044442A (en) * | 2009-10-14 | 2011-05-04 | 中国科学院微电子研究所 | Method for improving interface feature of gate medium having high dielectric constant |
| CN102592974A (en) * | 2012-03-20 | 2012-07-18 | 中国科学院上海微系统与信息技术研究所 | Preparation method for high-K medium film |
| CN103199013A (en) * | 2013-03-14 | 2013-07-10 | 上海华力微电子有限公司 | Improving method for PMOS gate-oxide negative bias temperature instability |
| CN103295891A (en) * | 2012-03-02 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for gate dielectric layer and manufacturing method for transistor |
| CN104425231A (en) * | 2013-09-10 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044442A (en) * | 2009-10-14 | 2011-05-04 | 中国科学院微电子研究所 | Method for improving interface feature of gate medium having high dielectric constant |
| CN103295891A (en) * | 2012-03-02 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for gate dielectric layer and manufacturing method for transistor |
| CN102592974A (en) * | 2012-03-20 | 2012-07-18 | 中国科学院上海微系统与信息技术研究所 | Preparation method for high-K medium film |
| CN103199013A (en) * | 2013-03-14 | 2013-07-10 | 上海华力微电子有限公司 | Improving method for PMOS gate-oxide negative bias temperature instability |
| CN104425231A (en) * | 2013-09-10 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
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