CN105334361A - All-solid-state nanosecond pulse generation system - Google Patents
All-solid-state nanosecond pulse generation system Download PDFInfo
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- CN105334361A CN105334361A CN201510844197.1A CN201510844197A CN105334361A CN 105334361 A CN105334361 A CN 105334361A CN 201510844197 A CN201510844197 A CN 201510844197A CN 105334361 A CN105334361 A CN 105334361A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
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Abstract
The embodiment of the invention discloses an all-solid-state nanosecond pulse generation system. The all-solid-state nanosecond pulse generation system comprises a direct-current power supply, a solid Marx circuit, a current sensor, an FPGA control circuit and a protection and control circuit. The FPGA control circuit is electrically connected to the direct-current power supply and the solid Marx circuit. The direct-current power supply is electrically connected to the FPGA control circuit and the solid Marx circuit and supplies power to the FPGA control circuit and the solid Marx circuit. The solid Marx circuit is electrically connected to a load, and the current sensor is arranged between the solid Marx circuit and the load and electrically connected to the FPGA control circuit through the protection and control circuit. The protection and control circuit comprises a voltage comparison circuit and an RS holding circuit, the voltage comparison circuit is electrically connected with the RS holding circuit, the current sensor is electrically connected to the voltage comparison circuit, and the RS holding circuit is electrically connected to the FPGA control circuit. According to the system, whether a loop has a fault or not is judged through the voltage comparison circuit, then a fault signal holding function for fault signals is achieved through the RS holding circuit, and therefore the stability of the system is improved.
Description
Technical field
The present invention relates to pulse generating system technical field, particularly relate to a kind of all solid state nanosecond pulse generation systems.
Background technology
Along with the development of economy and society, electricity needs also increases thereupon.Power system safety and stability runs and becomes ever more important, and electric power primary equipment is as the part of electric system most critical, and its safety and stability is directly connected to the safety of electric system.Power transformer is topmost electric power primary equipment, under the very strong driving force effect that short-circuit current produces, Transformer Winding possibility loss of stability, causes the permanent deformation phenomenons such as bird caging, bulge or displacement, will directly cause sudden damage accident time serious.Test proves that deformation of transformer winding has cumulative effect, therefore promptly and accurately finds Transformer Winding obstacle, to power transformer so that whole safe operation of power system most important.
In prior art, frequency response method is that winding deformation of power transformer detects comparatively conventional method.Transformer Winding is under the voltage effect of upper frequency, each winding all can be considered a passive linear two-port network be made up of linear resistance, inductance, electric capacity equal distribution parameter, its bulk properties describe by transport function, if winding deforms, the parameter such as distributed inductance, electric capacity of winding inside must change, and frequency response characteristic changes.Frequency response method is by detecting the frequency response characteristic of Transformer Winding, and carries out vertical and horizontal to testing result and compare, and according to the intensity of variation of frequency response characteristic, judges the contingent winding deformation situation of transformer.
Need by pulse generating system when frequency response method detects deformation of transformer winding situation, but pulse generator failure signal is generally Exponential Decay Wave, this signal exports as square-wave signal after comparer compares with normal value, if using this signal as failure control signal, then when high level, its exterior shows as normal condition, during low level, its exterior shows as malfunction, greatly reduces the security of system like this.
Summary of the invention
Provide a kind of all solid state nanosecond pulse generation systems in the embodiment of the present invention, fault time normal during to solve fault-signal in prior art, reduces security of system sex chromosome mosaicism.
In order to solve the problems of the technologies described above, the embodiment of the invention discloses following technical scheme:
The invention discloses a kind of all solid state nanosecond pulse generation systems, comprising: direct supply, solid-state Marx circuit, current sensor, FPGA control circuit and protecting control circuit;
Described FPGA control circuit is electrically connected to described direct supply and solid-state Marx circuit respectively;
Described direct supply is electrically connected to described FPGA control circuit and solid-state Marx circuit, for described FPGA control circuit and solid-state Marx circuit are powered;
Described Marx circuit is electrically connected to load, and described current sensor is arranged between described Marx circuit and load, and described current sensor is electrically connected to described FPGA control circuit by described protecting control circuit; Wherein,
Described protecting control circuit comprises voltage comparator circuit and RS holding circuit; described voltage comparator circuit is electrically connected with described RS holding circuit; described current sensor is electrically connected to described voltage comparator circuit, and described RS holding circuit is electrically connected to described FPGA control circuit.
Preferably, described all solid state nanosecond pulse generation systems also comprises voltage control circuit and synchronous trigger control circuit, and described voltage control circuit is electrically connected with described FPGA control circuit and direct supply respectively and controls the output voltage of described direct supply;
Described synchronous trigger control circuit is electrically connected with described FPGA control circuit and solid-state Marx circuit respectively and controls solid-state Marx circuit output pulse.
Preferably, described voltage comparator circuit comprises RC shaping circuit, follow circuit, threshold voltage settings circuit and voltage compare computing circuit, described RC shaping circuit, follow circuit and voltage compare computing circuit are electrically connected successively, and described threshold voltage settings circuit is electrically connected with described voltage compare computing circuit;
Described voltage compare computing circuit is electrically connected with described RS holding circuit.
Preferably, described voltage comparator circuit also comprises high-voltage switch gear diode, and described high-voltage switch gear diode one end is electrically connected with described RC shaping circuit, the other end is connected with described current sensor.
Preferably, described RS holding circuit comprises rest-set flip-flop and reset circuit, and described rest-set flip-flop is electrically connected with described reset circuit, and described rest-set flip-flop is electrically connected with described voltage comparator circuit.
Preferably, described RS holding circuit also comprises fault detector, and described malfunction indicator lamp is electrically connected with described rest-set flip-flop.
Preferably, described fault detector comprises light emitting diode.
Preferably, current limiting safeguard resistor is electrically connected with between described direct supply and solid-state Marx circuit.
Preferably, described synchronous trigger control circuit comprises semiconductor switch, and described semiconductor switch controls the break-make between described synchronous trigger control circuit and solid-state Marx circuit.
Beneficial effect of the present invention comprises: realize voltage compare by design voltage comparator circuit and RS holding circuit, judge whether loop voltage exceedes threshold value, if exceed threshold value, export fault-signal, fault-signal is after RS holding circuit, realizing fault and keep function, until trouble shooting, thus avoiding system when breaking down, failover state time normal when external presentation is, effectively raises the security of system.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, for those of ordinary skills, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The one all solid state nanosecond pulse generation systems structural representation that Fig. 1 provides for the embodiment of the present invention;
A kind of voltage comparator circuit structural representation that Fig. 2 provides for the embodiment of the present invention;
A kind of RS holding circuit structural representation that Fig. 3 provides for the embodiment of the present invention;
In Fig. 1-Fig. 3, symbol represents:
1-direct supply, the solid-state Marx circuit of 2-, 3-current sensor; 4-FPGA control circuit, 5-protecting control circuit, 6-voltage comparator circuit; 7-RS holding circuit, 8-RC shaping circuit, 9-follow circuit; 10-threshold voltage settings circuit; 11-voltage compare computing circuit, 12-reset circuit, 13-voltage control circuit; the synchronous trigger control circuit of 14-, 15-RS trigger.
Embodiment
The embodiment of the present invention provides a kind of all solid state nanosecond pulse generation systems, technical scheme in the present invention is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, should belong to the scope of protection of the invention.
Technical scheme in the embodiment of the present invention is understood better in order to make those skilled in the art person, and enable the above-mentioned purpose of the embodiment of the present invention, feature and advantage become apparent more, below in conjunction with accompanying drawing, technical scheme in the embodiment of the present invention is described in further detail.
See Fig. 1, it is the one all solid state nanosecond pulse generation systems structural representation that the embodiment of the present invention provides.
Pulse generating system disclosed by the invention comprises direct supply 1, solid-state Marx circuit 2, current sensor 3, FPGA control circuit 4 and protecting control circuit 5.
FPGA control circuit 4 is electrically connected to direct supply 1 and solid-state Marx circuit 2 respectively; direct supply 1 is electrically connected to FPGA control circuit 4 and solid-state Marx circuit 2; for FPGA control circuit 4 and solid-state Marx circuit 2 are powered; FPGA control circuit 4 is controlled direct supply 1 and is charged to solid-state Marx circuit 2 by protective resistance; and power for FPGA control circuit 4, FPGA control circuit 4 sends pulse signal steering order to solid-state Marx circuit 2 simultaneously.
Marx circuit is electrically connected to load, and current sensor 3 is arranged between Marx circuit and load, and current sensor 3 is electrically connected to FPGA control circuit 4 by protecting control circuit 5; Wherein, protecting control circuit 5 comprises voltage comparator circuit 6 and RS holding circuit 7, and voltage comparator circuit 6 is electrically connected with RS holding circuit 7, and current sensor 3 is electrically connected to voltage comparator circuit 6, RS holding circuit 7 and is electrically connected to FPGA control circuit 4.Marx circuit can form high-voltage nanosecond pulse in load, current sensor 3 sends the current signal in the discharge loop detected to voltage comparator circuit 6, voltage comparator circuit 6 judges whether voltage exceedes threshold value, if exceed threshold value, voltage comparator circuit 6 sends fault-signal to RS holding circuit 7, fault-signal by RS holding circuit 7, RS holding circuit 7 can fault-signal is low level again time can continue to remain low level, until failure removal.
As shown in Figure 1, the solid-state nanosecond pulse generation systems that the present embodiment provides also comprises voltage control circuit 13 and synchronous trigger circuit, voltage control circuit 13 is electrically connected with FPGA control circuit 4 and direct supply 1 respectively and controls the output voltage of described direct supply 1, and synchronous trigger control circuit 14 is electrically connected with FPGA control circuit 4 and solid-state Marx circuit 2 and controls solid-state Marx circuit 2 respectively and exports pulse.Voltage control circuit 13 is mainly by the control of FPGA control circuit 4, thus control the output voltage of direct supply 1, synchronous trigger control circuit 14 also by the control of FPGA control circuit 4, thus controls solid-state Marx circuit 2 and exports the pulse width of pulse, repetition frequency and number etc.
Seen from the above description, FPGA control circuit 4 is core of the present invention, and FPGA control circuit 4 is used for the whole workflow of gating pulse generation systems.When needs use pulse generating system to detect Transformer Winding operating mode, FPGA control circuit 4 receives steering order, and forward voltage control circuit 13, voltage control circuit 13 controls the output voltage of DC voltage, while forward voltage control circuit 13, also the synchronous trigger control circuit 14 of conducting, synchronous trigger control circuit 14 triggers solid-state Marx circuit 2, makes solid-state Marx circuit 2 in load, form the pulse of high-voltage nanosecond level.Electric current now in current sensor 3 Real-Time Monitoring loop, current sensor 3 sends the current signal monitored to voltage comparator circuit 6, as a kind of voltage comparator circuit 6 structural representation that Fig. 3 provides for the embodiment of the present invention.
As shown in Figure 2, voltage comparator circuit 6 comprises RC shaping circuit 8, follow circuit 9, threshold voltage settings circuit 10 and voltage compare computing circuit, RC shaping circuit 8, follow circuit 9 and voltage compare computing circuit are electrically connected successively, threshold voltage settings circuit 10 is electrically connected with voltage compare computing circuit, and voltage compare computing circuit is electrically connected with RS holding circuit 7.And needed first through high-voltage switch gear diode V1 before current signal enters voltage mark signal, the breakdown reverse voltage of high-voltage switch gear diode V1 can reach 250V, its effect is the negative half-wave voltage signal that may occur prevented in current reflux and filtering sensor.Current signal is entering RC shaping circuit 8 after high-voltage switch gear diode; the signal entering RC shaping circuit 8 carries out clamper by a high-voltage switch gear diode V2 too; the effect of high-voltage switch gear diode V2 be by the current signal clamper of input in 0.3V-407V, can effectively protect operational amplifier LMH6658 like this.Signal is after RC shaping circuit 8, the signal exported is Millisecond signal, greatly delay the rising edge of signal, so that operational amplifier has time enough to follow, wherein first operational amplifier LMH6658 mainly plays Following effect, and the signal amplitude of operational amplifier input and output is identical, RC shaping circuit 8 outputs signal the reverse input end 6 that the signal exported by 1 end after follow circuit 9 enters second operational amplifier LMH6658, and compare with the setting threshold value being connected to positive input 5, when the voltage signal recorded exceedes setting threshold value, it is 0 that 7 ends of computing comparer LMH6658 export, now pulse producer is in malfunction, otherwise, then 7 ends export is 1, now pulse producer is in normal condition.
The signal entering 6 ends of computing comparer LMH6658 after RC shaping circuit 8 is Exponential Decay Wave, then the output signal of computing comparer LMH6658 is square-wave signal, when square-wave signal is in high level, its exterior shows as normally, when square-wave signal is in high level, its exterior shows as fault, if directly using this signal as fault-signal, its exterior performance is unstable, therefore RS holding circuit 7 is designed, RS holding circuit 7 makes fault-signal export as continuing maintenance during low level, until trouble shooting.
See Fig. 3, a kind of RS holding circuit structural representation that the embodiment of the present invention provides.As shown in Figure 3, fault holding circuit adopts 74F00 to form rest-set flip-flop 15, its inside is integrated into Sheffer stroke gate, and when system malfunctions, voltage comparator circuit 6 now can export square-wave signal, when signal is in low level, 1 pin of RS holding circuit 7 is low level, and because 74F00 is Sheffer stroke gate integrated chip, now 3 pins are in high level state, emergency light is bright, and emergency light is set to light emitting diode.S1 is the reset switch in reset circuit 12, when fault-signal is not removed, S1 does not press, now No. 5 pins are in high level state as seen from the figure, and 4 good pins are connected with No. 3 pins, so level state is high level, so No. 4 pins and No. 5 pins are high level, after Sheffer stroke gate, No. 6 pins export as low level, are high level due to No. 4 with No. 5 pins, thus No. 6 pins can to remain level constant.No. 6 pins are connected with No. 2 pins, now No. 2 pins are also low level, now, even if external fault signal becomes high level (namely No. 1 pin becomes high level), because No. 2 pins are defined as low level, still be high level after the Sheffer stroke gate of 74F00, now and achieve low level keep function.When trouble shooting, press the reset switch S1 in reset circuit 12, No. 5 pins just become low level, and so No. 6 pins become high level, and outside reply is normal, No. 1 pin now input high level, and so No. 3 pins export as low level, and signal fault lamp goes out.
Seen from the above description; FPGA control circuit 4 has control voltage, controls the function of trigger pulse and protection circuit; the output voltage controlling direct supply 1 is realized by regulating circuit; control trigger pulse to be realized by synchronous trigger control circuit 14, protection circuit realizes mainly through voltage comparator circuit 6 and RS holding circuit 7.In use, hold input pulse parameter information by PC, after single-chip microcomputer process, data are delivered to FPGA control circuit 4, FPGA control circuit 4 after calculation process, send voltage control signal and trigger pulse control signal.
As seen from the above-described embodiment, all solid state nanosecond pulse generation systems disclosed by the invention realizes and the comparing of voltage threshold by arranging voltage comparator circuit 6, then fault-signal is exported when voltage exceedes threshold value, for normal switching state during fault when pulse generating system occurs when preventing fault, the security of reduction system, realized the maintenance function of fault-signal by RS holding circuit 7, thus when fault, malfunction can be kept until trouble shooting always.
It should be noted that, in this article, the such as relational terms of " first " and " second " etc. and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
The above is only the specific embodiment of the present invention, those skilled in the art is understood or realizes the present invention.To be apparent to one skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (9)
1. an all solid state nanosecond pulse generation systems, it is characterized in that, comprising: direct supply (1), solid-state Marx circuit (2), current sensor (3), FPGA control circuit (4) and protecting control circuit (5);
Described FPGA control circuit (4) is electrically connected to described direct supply (1) and solid-state Marx circuit (2) respectively;
Described direct supply (1) is electrically connected to described FPGA control circuit (4) and solid-state Marx circuit (2), is described FPGA control circuit (4) and solid-state Marx circuit (2) power supply;
Described Marx circuit is electrically connected to load, described current sensor (3) is arranged between described Marx circuit and load, and described current sensor (3) is electrically connected to described FPGA control circuit (4) by described protecting control circuit (5); Wherein,
Described protecting control circuit (5) comprises voltage comparator circuit (6) and RS holding circuit (7); described voltage comparator circuit (6) is electrically connected with described RS holding circuit (7); described current sensor (3) is electrically connected to described voltage comparator circuit (6), and described RS holding circuit (7) is electrically connected to described FPGA control circuit (4).
2. all solid state nanosecond pulse generation systems according to claim 1, it is characterized in that, described all solid state nanosecond pulse generation systems also comprises voltage control circuit (13) and synchronous trigger control circuit (14), and described voltage control circuit (13) is electrically connected with described FPGA control circuit (4) and direct supply (1) and controls the output voltage of described direct supply (1) respectively;
Described synchronous trigger control circuit (14) is electrically connected with described FPGA control circuit (4) and solid-state Marx circuit (2) respectively and controls solid-state Marx circuit (2) and exports pulse.
3. all solid state nanosecond pulse generation systems according to claim 1, it is characterized in that, described voltage comparator circuit (6) comprises RC shaping circuit (8), follow circuit (9), threshold voltage settings circuit (10) and voltage compare computing circuit (11), described RC shaping circuit (8), follow circuit (9) and voltage compare computing circuit (11) are electrically connected successively, and described threshold voltage settings circuit (10) is electrically connected with described voltage compare computing circuit (11);
Described voltage compare computing circuit (11) is electrically connected with described RS holding circuit (7).
4. all solid state nanosecond pulse generation systems according to claim 3, it is characterized in that, described voltage comparator circuit (6) also comprises high-voltage switch gear diode, and described high-voltage switch gear diode one end is electrically connected with described RC shaping circuit (8), the other end is connected with described current sensor (3).
5. all solid state nanosecond pulse generation systems according to claim 1, it is characterized in that, described RS holding circuit (7) comprises rest-set flip-flop (15) and reset circuit (12), described rest-set flip-flop (15) is electrically connected with described reset circuit (12), and described rest-set flip-flop (15) is electrically connected with described voltage comparator circuit (6).
6. all solid state nanosecond pulse generation systems according to claim 5, is characterized in that, described RS holding circuit (7) also comprises fault detector, and described malfunction indicator lamp is electrically connected with described rest-set flip-flop (15).
7. all solid state nanosecond pulse generation systems according to claim 6, it is characterized in that, described fault detector comprises light emitting diode.
8. all solid state nanosecond pulse generation systems according to claim 1, is characterized in that, is electrically connected with current limiting safeguard resistor between described direct supply (1) and solid-state Marx circuit (2).
9. all solid state nanosecond pulse generation systems according to claim 2, it is characterized in that, described synchronous trigger control circuit (14) comprises semiconductor switch, and described semiconductor switch controls the break-make between described synchronous trigger control circuit (14) and solid-state Marx circuit (2).
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| CN201510844197.1A CN105334361A (en) | 2015-11-26 | 2015-11-26 | All-solid-state nanosecond pulse generation system |
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| CN201510844197.1A CN105334361A (en) | 2015-11-26 | 2015-11-26 | All-solid-state nanosecond pulse generation system |
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| CN105634441A (en) * | 2016-04-01 | 2016-06-01 | 中国人民解放军军械工程学院 | High-efficiency and double-exponential electromagnetic pulse generation device |
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Application publication date: 20160217 |