CN105304476A - High-K gate dielectric layer formation method and semiconductor device - Google Patents
High-K gate dielectric layer formation method and semiconductor device Download PDFInfo
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- CN105304476A CN105304476A CN201410365791.8A CN201410365791A CN105304476A CN 105304476 A CN105304476 A CN 105304476A CN 201410365791 A CN201410365791 A CN 201410365791A CN 105304476 A CN105304476 A CN 105304476A
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Abstract
The invention provides a high-K gate dielectric layer formation method and a semiconductor device. The method comprises the following steps: providing a semiconductor substrate, a dielectric layer being formed on the semiconductor substrate, and a gate opening being formed in the dielectric layer; and depositing a high-K material layer, wherein the high-K material layer covers the bottom portion and side wall of the gate opening, and the high-K material layer is made of the mixture of HfO2 and ZrO2. The method helps to improve the film quality of a high-K gate dielectric layer, and helps to form the high-K gate dielectric layer having higher K value and thinner equivalent oxide layer thickness.
Description
Technical field
The present invention relates to semiconductor device and semiconductor process techniques, particularly relate to a kind of formation method and semiconductor device of high K gate dielectric layer.
Background technology
When high K gate dielectric layer metal gate pole technique (HKMG) begins to show, ZrO
2owing to there is higher dielectric constant (K) and lower unformed shape to crystal state inversion temperature, and receive and pay close attention to widely.But, adopt ZrO
2there is following shortcoming: ZrO under higher treatment temperature
2and it is also unstable between silicon.
And HfO
2dielectric constant be about 20, and enough fire-resistant under common silicon treatment process condition, can't with silicon substrate or the reaction of the polysilicon electrode on it.Therefore, prior art adopts HfO at present usually
2form high K gate dielectric layer.
Fig. 1 and Fig. 2 shows the forming process of a kind of high K gate dielectric layer in prior art.
With reference to figure 1, provide Semiconductor substrate 10, this Semiconductor substrate 10 is formed with dielectric layer 11, in dielectric layer 11, is formed with gate openings 12; Deposition HfO
2layer 13, this HfO
2the surface of the layer bottom of 13 cover gate openings 12, sidewall and dielectric layer 13.
Wherein, in Semiconductor substrate 10, isolation structure 101 can also be formed with, source region 102 and drain region 103 in the Semiconductor substrate 10 of gate openings 12 both sides, can be formed.In addition, side wall (spacer) 111 can be formed in the dielectric layer 11 around gate openings 12.
With reference to figure 2, depositing cap layers (caplayer) 14, this cap layers 14 covers HfO2 layer 13.In prior art, the material of cap layers 14 is generally TiN.
Such as, but adopt the high K gate dielectric layer that as above method is formed to have multiple shortcoming, film quality is poor, and causes its equivalent oxide thickness (EOT) thicker because its K value is not high enough.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of formation method and semiconductor device of high K gate dielectric layer, be conducive to the film quality improving high K gate dielectric layer, and contribute to being formed the high K gate dielectric layer with higher K value and thinner equivalent oxide thickness.
For solving the problems of the technologies described above, the invention provides a kind of formation method of high K gate dielectric layer, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with dielectric layer, in described dielectric layer, be formed with gate openings;
Deposition hafnium layer, described hafnium layer covers bottom and the sidewall of described gate openings, and the material of described hafnium layer is HfO
2and ZrO
2mixture.
According to one embodiment of present invention, described HfO
2and ZrO
2mixture in, Hf:Zr>1:1.
According to one embodiment of present invention, after depositing described hafnium layer, the method also comprises: depositing cap layers, and described cap layers covers described hafnium layer.
According to one embodiment of present invention, after depositing described hafnium layer, before depositing described cap layers, described method also comprises:
Carry out first step deposition after annealing, to remove the pollutant in described hafnium layer;
Carry out second step deposition after annealing, with the electric charge reducing in described hafnium layer and on described hafnium layer and Semiconductor substrate contact interface.
According to one embodiment of present invention, described first step deposition after annealing carries out in oxygenous atmosphere.
According to one embodiment of present invention, the temperature of described first step deposition after annealing is 550 ~ 650 DEG C, and the time is 20 ~ 30 seconds, and atmosphere is O
2and N
2mist, wherein O
2volume ratio be 2% ~ 4%.
According to one embodiment of present invention, described second step deposition after annealing carries out in the atmosphere of hydrogen.
According to one embodiment of present invention, the temperature of described second step deposition after annealing is 350 ~ 400 DEG C, and pressure is 10 ~ 20Atm, and the time is 30 ~ 60 minutes, and atmosphere is H
2and N
2mist, wherein H
2volume ratio be 5% ~ 10%.
According to one embodiment of present invention, described cap layers comprises: the first cap layers stacked gradually, absorbed layer and the second cap layers, and the material of described first cap layers is TiN, and the material of described absorbed layer is Ti, the material TiN of described second cap layers.
According to one embodiment of present invention, described cap layers comprises: the first cap layers stacked gradually and absorbed layer, and the material of described first cap layers is TiN, and the material of described absorbed layer is rich titanium TiN.According to one embodiment of present invention, after depositing cap layers, described method also comprises: carry out high pressure annealing to described Semiconductor substrate.
According to one embodiment of present invention, the temperature of described high pressure annealing is 400 ~ 450 DEG C, and pressure is 10 ~ 20Atm, and the time is 0.8 ~ 1.2 minute, and atmosphere is O
2with the mist of Ar, wherein O
2volume ratio be 5% ~ 10%.
According to one embodiment of present invention, atomic layer deposition method is adopted to deposit described hafnium layer.
Present invention also offers a kind of semiconductor device, comprising:
Semiconductor substrate;
Form dielectric layer on the semiconductor substrate, in this dielectric layer, there is gate openings;
Hafnium layer, covers bottom and the sidewall of described gate openings, and the material of described hafnium layer is HfO
2and ZrO
2mixture.
According to one embodiment of present invention, described HfO
2and ZrO
2mixture in, Hf:Zr>1:1.
According to one embodiment of present invention, this semiconductor device also comprises: cap layers, covers described hafnium layer.
According to one embodiment of present invention, described cap layers comprises the first cap layers, absorbed layer and the second cap layers that stack gradually, described in state the first cap layers material be TiN, the material of described absorbed layer is Ti, the material TiN of described second cap layers.
According to one embodiment of present invention, described cap layers comprises the first cap layers and absorbed layer that stack gradually, and the material of described first cap layers is TiN, and the material of described absorbed layer is rich titanium TiN.
Compared with prior art, the present invention has the following advantages:
In the formation method of the high K gate dielectric layer of the embodiment of the present invention, the material of high K gate dielectric layer is HfO
2and ZrO
2mixture.At HfO
2middle introducing ZrO
2can obtain that crystal grain (grain) size is less, the better rete of consistency, more crystal boundary (grainboundary) can be obtained thus pollutant is more easily therefrom diffused out in annealing process, and the gas being conducive to depositing after annealing employing more unimpededly carries out annealing in process by crystal boundary arrival fault location, therefore can obtain higher K value and thinner equivalent oxide thickness.
Furthermore, at deposition HfO
2and ZrO
2mixture after, before depositing cap layers, first step deposition after annealing (PDA is successively carried out to Semiconductor substrate, PostDepositionAnneal) and second step deposition after annealing, remove the pollutant in hafnium layer and electric charge respectively, to improve film quality further, put forward high-k.
In addition, the cap layers of the embodiment of the present invention is preferably the laminated construction of TiN, Ti and TiN or the laminated construction of TiN and rich titanium TiN, is a kind of better oxygen absorber, can strengthens oxygen clean-up effect compared with the cap layers of traditional TiN material.
Accompanying drawing explanation
Fig. 1 to Fig. 2 shows the cross-sectional view that in the formation method of a kind of high K gate dielectric layer of prior art, each step is corresponding;
Fig. 3 is the schematic flow sheet of the formation method of the high K gate dielectric layer of the embodiment of the present invention;
Fig. 4 to Figure 13 shows the cross-sectional view that in the formation method of the high K gate dielectric layer of the embodiment of the present invention, each step is corresponding.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.
With reference to figure 3, the formation method of the high K gate dielectric layer of the present embodiment comprises the steps:
Step S11, provides Semiconductor substrate, and described Semiconductor substrate is formed with dielectric layer, is formed with gate openings in described dielectric layer;
Step S12, deposition hafnium layer, described hafnium layer covers bottom and the sidewall of described gate openings, and the material of described hafnium layer is HfO
2and ZrO
2mixture;
Step S13, depositing cap layers, described cap layers covers described hafnium layer.
Be described in detail below in conjunction with Fig. 4 to Figure 13.
With reference to figure 4, provide Semiconductor substrate 20, this Semiconductor substrate 20 is formed with dummy grid (dummygate) 204, side wall (spacer) 211 around dummy grid 204, can also be formed.
Wherein, the material of Semiconductor substrate 20 can be various conventional semi-conducting materials, such as, can be silicon substrate, silicon-on-insulator (SOI) substrate etc., be described in the present embodiment for silicon substrate.The material of dummy grid 204 can be such as polysilicon, or also can be the laminated construction of silica and polysilicon.As a nonrestrictive example, can be formed with isolation structure 201 in Semiconductor substrate 20, such as, can be that shallow trench isolation is from (STI) structure.
With reference to figure 5, in formation source region, both sides 202 and the drain region 203 of dummy grid 204, formation method can be ion implantation.The ionic type injected is as the criterion with type of device, and for PMOS transistor, injecting ionic type is P type ion, such as boron ion; For nmos pass transistor, injecting ionic type is N-type ion, such as phosphonium ion.
With reference to figure 6, the Semiconductor substrate 20 around dummy grid 204 forms dielectric layer 21.The material of dielectric layer 21 can be various conventional interlayer dielectric layer (ILD) materials, such as silicon dioxide.
With reference to figure 7, remove dummy grid, form gate openings 22 in the position of dummy grid.Such as, after removing the polysilicon layer that comprises of this dummy grid and oxide layer, described gate openings 22 is defined.After the above-mentioned polysilicon layer of removal and oxide layer, interface oxide layer (IL can also be formed in Semiconductor substrate 20 surface bottom gate openings 22, InterfacialoxideLayer), the Semiconductor substrate 20 bottom this interface oxide layer cover gate opening 22.The formation method of this interface oxide layer can be thermal reaction method or chemical reaction method.
With reference to figure 8, afterwards, deposition hafnium layer 23, the material of this hafnium layer 23 is HfO
2and ZrO
2mixture.The bottom of hafnium layer 23 cover gate opening 22 and sidewall, in addition, the surface of the hafnium layer 23 of deposition also blanket dielectric layer 21 in the lump.Further, hafnium layer 23 part be positioned at bottom gate openings 22 covers described interface oxide layer.As a preferred embodiment, adopt ald (ALD) method to form this hafnium layer 23, ald has good Step Coverage (stepcoverage) ability and consistency of thickness.
By ZrO
2introduce HfO
2less crystallite dimension and the better rete of consistency can be obtained.ZrO
2and HfO
2in the rete be mixed to form, there is more crystal boundary, in other words, ZrO
2and HfO
2have more " path " in the hafnium layer 23 formed, in follow-up annealing process, various pollutant (contaminants) more easily can be diffused out by these paths, reparation gas also can reach the defective position of tool more easily, more quickly by these paths and Lacking oxygen (oxygenvacancies) is annealed, and will be described in detail after a while.Wherein, this pollutant is the pollutant component introduced in each processing step, such as, can comprise Al etc.
Wherein, HfO
2and ZrO
2the preferred proportioning of mixture be Hf:Zr>1:1, namely Hf Elements Atom number is greater than Zr Elements Atom number, and Hf:Zr can be such as 2:1,3:1 etc.Because Zr element is too much, although the crystal grain of hafnium layer 23 can be less, make hafnium layer 23 evenly, also can cause the problems such as device leaks electricity, reliability simultaneously.
As a preferred embodiment, after deposition hafnium layer 23, successively can carry out two steps deposition after annealing (PDA), wherein first step deposition after annealing is mainly used in removing the pollutant in hafnium layer 23, second step deposition after annealing is mainly used in reducing the electric charge on the contact interface in hafnium layer 23 and between hafnium layer 23 and interface oxide layer, and the dangling bonds between silicon in passivation hafnium layer 23 and Semiconductor substrate 20.
Preferably, first step deposition after annealing carries out in oxygenous atmosphere, and second step deposition after annealing carries out in the atmosphere of hydrogen.
More preferably, the technological parameter of first step deposition after annealing is as follows: temperature is 550 ~ 600 DEG C, and the time is 20 ~ 30 seconds, and atmosphere is O
2and N
2mist, wherein O
2volume ratio be 2% ~ 4%, pressure can be normal pressure, such as, be approximately standard atmospheric pressure.Under this parameter area, Lacking oxygen can be repaired fast, and the regrowth that dielectric layer 21 can't be brought too much.
It should be noted that, in first step deposition post anneal, O
2volume ratio, can do between pressure and temperature and weigh, especially O
2volume ratio and pressure between can do and weigh.Such as, pressure can be a bit larger tham above-mentioned scope, correspondingly O
2volume ratio be slightly smaller than above-mentioned scope.Through first step deposition after annealing, the pollutant in hafnium layer 23 can pass through HfO
2and ZrO
2between crystal boundary formed numerous paths more easily diffuse out.In addition, first step deposition after annealing is also conducive to the phase transition (phasetransformation) promoting hafnium layer 23.
More preferably, the technological parameter of second step deposition after annealing is as follows: temperature is 350 ~ 400 DEG C, and pressure is 10 ~ 20Atm, and the time is 30 ~ 60 minutes, and atmosphere is H
2and N
2mist, wherein H
2volume ratio be 5% ~ 10%.Under this parameter area, be conducive to reducing the possibility that hafnium layer 23 and Semiconductor substrate 20 react, most hydrogen can be reacted and repair.In addition, second step deposition after annealing can also promote the passivation (passivation) of the dangling bonds (danglingbonds) between Hf, Zr and silicon substrate, thus reduces the hysteresis (hysteresis) of the transistor device formed.
It should be noted that, H
2volume ratio, can do between pressure and temperature and weigh, especially H
2volume ratio and pressure between can do and weigh.Such as, pressure can be a bit larger tham above-mentioned scope, correspondingly H
2volume ratio be slightly smaller than above-mentioned scope.
With reference to figure 9, depositing cap layers 24, this cap layers 24 covers hafnium layer 23.As a preferred embodiment, cap layers 24 is laminated construction, comprises the first cap layers 241, absorbed layer (absorptionlayer) 242 and the second cap layers 243 that stack gradually.As a nonrestrictive example, the thickness of the first cap layers 241 can be
the thickness of absorbed layer 242 can be
the thickness of the second cap layers 242 can be
As a preferred embodiment, the material of the first cap layers 241 can be TiN, and the material of absorbed layer 242 can be Ti, and the material of the second cap layers 242 can be TiN.Above-mentioned material, compared with traditional simple cap layers adopting TiN to prepare, is better oxygen absorber (oxygengetter), can strengthens oxygen clean-up effect (oxygenscavengingeffect).
Or cap layers 24 can also be other structures, can be such as the laminated construction of the first cap layers and absorbed layer, wherein the material of the first cap layers be TiN, and the material of absorbed layer is rich titanium TiN (Ti-richTiN).
After formation cap layers 24, high pressure annealing (HPA, HighPressureAnneal) can be carried out to Semiconductor substrate 20.This high pressure annealing is extremely important for minimizing interface charge, and oxygen dipole (oxygendipole) is repaired, the minimizing of Lacking oxygen (oxygenvacancy) and oxonium ion (oxygenion) is also particularly important.
As a preferred embodiment, the technological parameter forming the high pressure annealing after cap layers 24 is as follows: temperature is 400 ~ 450 DEG C, and pressure is 10 ~ 20Atm, and the time is 0.8 ~ 1.2 minute, and atmosphere is O
2with the mist of Ar, wherein O
2volume ratio be 5% ~ 10%.
With reference to Figure 10, remove cap layers 24, expose hafnium layer 23.
With reference to Figure 11, in gate openings 22 (see Figure 10), fill gate electrode 25, the material of this gate electrode 25 can be metal gate material conventional in rear grid (gate-last) technique.
With reference to Figure 12, in the dielectric layer 21 above source region 202 and drain region 203 and hafnium layer 23, form contact hole (contact) 26.The forming process of contact hole 26 can comprise photoetching, etching etc.
With reference to Figure 13, filled conductive material in contact hole 26 (see Figure 12), forms embolism (plug) 27.The material of embolism 27 can be various suitable electric conducting materials, such as tungsten.
Afterwards, can also subsequent technique be continued, such as, continue to form multilayer interconnect structure on this gate electrode 25 and dielectric layer 21, etc.
The structure of the semiconductor device that the present embodiment is formed as shown in Figure 9, comprising: Semiconductor substrate 20; Dielectric layer 21, is formed in Semiconductor substrate 20, has gate openings 22 in this dielectric layer 21; Hafnium layer 23, the bottom of cover gate opening 22 and sidewall, the material of hafnium layer 23 is HfO
2and ZrO
2mixture; Cap layers 24, covers hafnium layer 23.Wherein, cap layers 24 can comprise the first cap layers 241, absorbed layer 242, second cap layers 243 that stack gradually.In addition, in Semiconductor substrate 20, isolation structure 201 can be had, source region 202 and the drain region 203 of MOS transistor can be formed in the Semiconductor substrate 20 of gate openings 22 both sides, in the dielectric layer 21 around gate openings 20, side wall 211 can be formed with.Wherein, interface oxide layer can also be formed with between the Semiconductor substrate 20 bottom gate openings 22 and hafnium layer 23.
With reference to Figure 13, after subsequent technique, the cap layers 24 in Fig. 9 is removed, and this semiconductor device also comprises: be filled in the gate electrode 25 in gate openings 22 (see Fig. 9), and this gate electrode 25 covers on hafnium layer 23; Be arranged in the contact hole of dielectric layer 21 above source region 202 and drain region 203 and hafnium layer 23; Fill embolism 27 in the contact hole.
By upper, the present embodiment is at HfO
2middle introducing ZrO
2be conducive to forming more crystal boundary, correspondingly formed more " path " in hafnium layer 23.Pollutant more easily can diffuse out via these paths, and after deposit in annealing process, repair gas can pass more readily these paths and arrive defective locations fast and Lacking oxygen is annealed, higher pressure contributes to repairing gas and is utilised more efficiently.For cap layers, in TiN, insert Ti contribute to strengthening oxygen clean-up effect, and under the help of high pressure annealing, this oxygen clean-up effect will be more effective.These means all contribute to the film quality improving high K gate dielectric layer above, can obtain having thinner equivalent oxide thickness, more high-k, high-quality high-K gate dielectric layer in HKMG technique.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (18)
1. a formation method for high K gate dielectric layer, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with dielectric layer, in described dielectric layer, be formed with gate openings;
Deposition hafnium layer, described hafnium layer covers bottom and the sidewall of described gate openings, and the material of described hafnium layer is HfO
2and ZrO
2mixture.
2. the formation method of high K gate dielectric layer according to claim 1, is characterized in that, described HfO
2and ZrO
2mixture in, Hf:Zr>1:1.
3. the formation method of high K gate dielectric layer according to claim 1, is characterized in that, also comprises: depositing cap layers after depositing described hafnium layer, and described cap layers covers described hafnium layer.
4. the formation method of high K gate dielectric layer according to claim 3, is characterized in that, after depositing described hafnium layer, also comprises before depositing described cap layers:
Carry out first step deposition after annealing, to remove the pollutant in described hafnium layer;
Carry out second step deposition after annealing, with the electric charge reducing in described hafnium layer and on described hafnium layer and Semiconductor substrate contact interface.
5. the formation method of high K gate dielectric layer according to claim 4, is characterized in that, described first step deposition after annealing carries out in oxygenous atmosphere.
6. the formation method of high K gate dielectric layer according to claim 4, is characterized in that, the temperature of described first step deposition after annealing is 550 ~ 600 DEG C, and the time is 20 ~ 30 seconds, and atmosphere is O
2and N
2mist, wherein O
2volume ratio be 2% ~ 4%.
7. the formation method of high K gate dielectric layer according to claim 4, is characterized in that, described second step deposition after annealing carries out in the atmosphere of hydrogen.
8. the formation method of high K gate dielectric layer according to claim 4, is characterized in that, the temperature of described second step deposition after annealing is 350 ~ 400 DEG C, and pressure is 10 ~ 20Atm, and the time is 30 ~ 60 minutes, and atmosphere is H
2and N
2mist, wherein H
2volume ratio be 5% ~ 10%.
9. the formation method of high K gate dielectric layer according to claim 3, it is characterized in that, described cap layers comprises: the first cap layers stacked gradually, absorbed layer and the second cap layers, and the material of described first cap layers is TiN, the material of described absorbed layer is Ti, the material TiN of described second cap layers.
10. the formation method of high K gate dielectric layer according to claim 3, it is characterized in that, described cap layers comprises: the first cap layers stacked gradually and absorbed layer, and the material of described first cap layers is TiN, and the material of described absorbed layer is rich titanium TiN.
The formation method of 11. high K gate dielectric layers according to claim 3 or 9 or 10, is characterized in that, also comprise after depositing cap layers: carry out high pressure annealing to described Semiconductor substrate.
The formation method of 12. high K gate dielectric layers according to claim 10, is characterized in that, the temperature of described high pressure annealing is 400 ~ 450 DEG C, and pressure is 10 ~ 20Atm, and the time is 0.8 ~ 1.2 minute, and atmosphere is O
2with the mist of Ar, wherein O
2volume ratio be 5% ~ 10%.
The formation method of 13. high K gate dielectric layers according to claim 1, is characterized in that, adopts atomic layer deposition method to deposit described hafnium layer.
14. 1 kinds of semiconductor device, is characterized in that, comprising:
Semiconductor substrate;
Form dielectric layer on the semiconductor substrate, in this dielectric layer, there is gate openings;
Hafnium layer, covers bottom and the sidewall of described gate openings, and the material of described hafnium layer is HfO
2and ZrO
2mixture.
15. semiconductor device according to claim 14, is characterized in that, described HfO
2and ZrO
2mixture in, Hf:Zr>1:1.
16. semiconductor device according to claim 14, is characterized in that, also comprise: cap layers, cover described hafnium layer.
17. semiconductor device according to claim 16, it is characterized in that, described cap layers comprises the first cap layers, absorbed layer and the second cap layers that stack gradually, described in state the first cap layers material be TiN, the material of described absorbed layer is Ti, the material TiN of described second cap layers.
18. semiconductor device according to claim 16, is characterized in that, described cap layers comprises the first cap layers and absorbed layer that stack gradually, and the material of described first cap layers is TiN, and the material of described absorbed layer is rich titanium TiN.
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Application publication date: 20160203 |