CN105304136A - Control method for memory array - Google Patents
Control method for memory array Download PDFInfo
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- CN105304136A CN105304136A CN201510821864.4A CN201510821864A CN105304136A CN 105304136 A CN105304136 A CN 105304136A CN 201510821864 A CN201510821864 A CN 201510821864A CN 105304136 A CN105304136 A CN 105304136A
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Abstract
The invention provides a control method for a memory array. The control method comprises a step of separately applying different working voltages on word lines, first control lines, second control lines and bit lines of the memory array so as to realize reading, programming and erasing of memory units, wherein a part of the bit lines are connected with a source electrode, the other part of the bit lines are connected with a drain electrode, and negative voltages are applied on first control lines and second control lines connected with unselected memory units. According to the control method for the memory array, negative voltages are applied on memory units whose word lines are not selected via the first control lines and the second control lines so as to prevent electrons to enter the unselected memory units under the action of voltage differences among the bit lines, so crosstalk to other memory units during operation of selected memory units is prevented.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of control method of memory array.
Background technology
Along with the development of memory technology, there is various types of storer, as random access memory (RAM), ROM (read-only memory) (ROM), dynamic RAM (DRAM), Erasable Programmable Read Only Memory EPROM (EPROM), Electrically Erasable Read Only Memory (EEPROM) and flash memory (Flash) etc.
Wherein, flash memory is a kind of nonvolatile memory, i.e. power-off data also can not be lost.Flash memory has the advantages such as convenient, storage density is high, good reliability because of it, is widely used in the mobile and communication apparatus such as mobile phone, computer, PDA, digital camera, flash disk.
Flash memory, as a kind of semiconductor memory, comprises memory array and peripheral circuit equally.Wherein, memory array comprises several memory cells, and several memory cells described are arranged in array, and each memory cell has control gate and floating boom, and described control gate is connected with control line, and described floating boom is for retaining electric charge.Memory cell with a line shares a wordline, and the memory cell of same row shares a bit lines.When wordline chooses a line, voltage is applied to different bit lines and effectively can choose memory cell.To other memory cells of the same row of the memory cell shared bit line chosen because wordline does not apply corresponding voltage and not selected, to other memory cells of the same a line of the memory cell common word line chosen because bit line does not apply corresponding voltage and not selected.Usually, the not selected wordline of memory cell connection and the voltage of control line are 0V.Memory array applies different operating voltage by control line, bit line and wordline, can realize the reading to memory cell, programming and erase operation.
When operating, can there is voltage difference between general bit line, electronics easily enters the floating boom of other unchecked memory cells under the effect of voltage difference, makes it transfer programming state to by erase status, thus causes crosstalk.
Therefore, how to solve while existing memory array is listed in and operates the memory cell chosen, cause the problem of crosstalk to become the current technical matters needing solution badly to other memory cells.
Summary of the invention
The object of the present invention is to provide a kind of control method of memory array, to solve while existing memory array is listed in and operates the memory cell chosen, other memory cells are caused to the problem of crosstalk.
For solving the problems of the technologies described above, the invention provides a kind of control method of memory array, the control method of described memory array comprises:
Described memory array is by applying different operating voltage respectively to realize reading to memory cell, programming and erasing to wordline, the first control line, the second control line and the bit line that source electrode connects and the bit line that is connected with drain electrode;
Wherein, the voltage that the first control line connected unchecked memory cell and the second control line apply is negative voltage.
Preferably, in the control method of described memory array, when described memory array carries out read operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage respectively; The voltage range of described first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage is respectively 0.5V ~ 5V, 0V ~ 3V, 0V ~ 6V, 0V ~ 0.5V, 0.8V ~ 3V.
Preferably, in the control method of described memory array, described first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage are respectively 2.5V, 2.5V, 4V, 0V, 2V.
Preferably, in the control method of described memory array, when described memory array carries out programming operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage respectively;
The voltage range of described 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage is respectively 1.0V ~ 2V, 5V ~ 11V, 2V ~ 6V, 2.5V ~ 6V, 0V ~ 0.6V.
Preferably, in the control method of described memory array, described 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage are respectively 1.5V, 8V, 5V, 5.5V and Vdp, wherein, described Vdp is the program voltage of fixed current, and the voltage range of described Vdp is between 0.2V to 0.6V.
Preferably, in the control method of described memory array, when described memory array carries out erase operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage respectively;
The voltage range of described 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage is respectively 5V ~ 10V ,-10V ~-5V ,-10V ~-5V, 0V ~ 0.5V, 0V ~ 0.5V.
Preferably, in the control method of described memory array, described 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage are respectively 8V ,-7V ,-7V, 0V, 0V.
Preferably, in the control method of described memory array, the voltage that the control line connected unchecked memory cell applies is all between-3V and-0.5V.
Preferably, in the control method of described memory array, described memory array comprises several and has source electrode, the memory cell of drain and gate, some the first control lines, some the second control lines, some the bit lines be parallel to each other and some and the wordline that insulate mutually vertical with described bit line;
Several memory cells described are that array is arranged, and the memory cell with a line shares a wordline, and the memory cell of same row shares a bit lines;
Every bit lines connects source electrode and the drain electrode of neighbor memory cell, and the wordline between adjacent bit lines connects the grid of described memory cell;
Described memory cell comprises the first storage unit and the second storage unit, and described first storage unit is between wordline and the source electrode of memory cell, and described second storage unit is between wordline and the drain electrode of described memory cell;
Described first storage unit comprises the first control gate and the first floating boom, and described second storage unit comprises the second control gate and the second floating boom;
Described first control gate is arranged at the top of described first floating boom, and described second control gate is arranged at the top of described second floating boom;
Described first control gate is connected with described first control line, and described second control gate is connected with described second control line;
The first control line be connected with same row of memory cells and the second control line lay respectively at the both sides of same wordline.
In the control method of memory array provided by the invention, apply negative voltage by the first control line and the unchecked memory cell of the second control pair wordline and enter unchecked memory cell under stoping the effect of the voltage difference of electronics between bit line, thus while avoiding operating the memory cell chosen, crosstalk is caused to other memory cell.
Embodiment
Embodiment 1
The invention provides a kind of control method of memory array, the control method of described memory array comprises:
Described memory array is by applying different operating voltage respectively to realize reading to memory cell, programming and erasing to wordline, the first control line, the second control line and the bit line that source electrode connects and the bit line that is connected with drain electrode;
Wherein, the voltage that the first control line connected unchecked memory cell and the second control line apply is negative voltage.
Preferably, in the control method of described memory array, when described memory array carries out read operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage respectively; The voltage range of described first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage is respectively 0.5V ~ 5V, 0V ~ 3V, 0V ~ 6V, 0V ~ 0.5V, 0.8V ~ 3V.
Preferably, in the control method of described memory array, described first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage are respectively 2.5V, 2.5V, 4V, 0V, 2V.
Preferably, in the control method of described memory array, when described memory array carries out programming operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage respectively;
The voltage range of described 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage is respectively 1.0V ~ 2V, 5V ~ 11V, 2V ~ 6V, 2.5V ~ 6V, 0V ~ 0.6V.
Preferably, in the control method of described memory array, described 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage are respectively 1.5V, 8V, 5V, 5.5V and Vdp, wherein, described Vdp is the program voltage of fixed current, and the voltage range of described Vdp is between 0.2V to 0.6V.
Preferably, in the control method of described memory array, when described memory array carries out erase operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage respectively;
The voltage range of described 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage is respectively 5V ~ 10V ,-10V ~-5V ,-10V ~-5V, 0V ~ 0.5V, 0V ~ 0.5V.
Preferably, in the control method of described memory array, described 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage are respectively 8V ,-7V ,-7V, 0V, 0V.
Preferably, in the control method of described memory array, the voltage that the control line connected unchecked memory cell applies is all between-3V and-0.5V.
Preferably, in the control method of described memory array, described memory array comprises several and has source electrode, the memory cell of drain and gate, some the first control lines, some the second control lines, some the bit lines be parallel to each other and some and the wordline that insulate mutually vertical with described bit line;
Several memory cells described are that array is arranged, and the memory cell with a line shares a wordline, and the memory cell of same row shares a bit lines;
Every bit lines connects source electrode and the drain electrode of neighbor memory cell, and the wordline between adjacent bit lines connects the grid of described memory cell;
Described memory cell comprises the first storage unit and the second storage unit, and described first storage unit is between wordline and the source electrode of memory cell, and described second storage unit is between wordline and the drain electrode of described memory cell;
Described first storage unit comprises the first control gate and the first floating boom, and described second storage unit comprises the second control gate and the second floating boom;
Described first control gate is arranged at the top of described first floating boom, and described second control gate is arranged at the top of described second floating boom;
Described first control gate is connected with described first control line, and described second control gate is connected with described second control line;
The first control line be connected with same row of memory cells and the second control line lay respectively at the both sides of same wordline.
In the control method of memory array provided by the invention, apply negative voltage by the first control line and the unchecked memory cell of the second control pair wordline and enter unchecked memory cell under stoping the effect of the voltage difference of electronics between bit line, thus while avoiding operating the memory cell chosen, crosstalk is caused to other memory cell.
Claims (7)
1. the control method of a memory array, it is characterized in that, comprising: described memory array is by applying different operating voltage respectively to realize reading to memory cell, programming and erasing to wordline, the first control line, the second control line and the bit line that source electrode connects and the bit line that is connected with drain electrode; Wherein, the voltage that the first control line connected unchecked memory cell and the second control line apply is negative voltage.
2. the control method of memory array as claimed in claim 1, it is characterized in that, when described memory array carries out read operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage respectively;
The voltage range of described first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage is respectively 0.5V ~ 5V, 0V ~ 3V, 0V ~ 6V, 0V ~ 0.5V, 0.8V ~ 3V.
3. the control method of memory array as claimed in claim 2, it is characterized in that, described first voltage, the second voltage, tertiary voltage, the 4th voltage and the 5th voltage are respectively 2.5V, 2.5V, 4V, 0V, 2V.
4. memory array as claimed in claim 1, it is characterized in that, when described memory array carries out programming operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage respectively;
The voltage range of described 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage is respectively 1.0V ~ 2V, 5V ~ 11V, 2V ~ 6V, 2.5V ~ 6V, 0V ~ 0.6V.
5. as right wants the control method of the memory array as described in 4, it is characterized in that, described 6th voltage, the 7th voltage, the 8th voltage, the 9th voltage and the tenth voltage are respectively 1.5V, 8V, 5V, 5.5V and Vdp, wherein, described Vdp is the program voltage of fixed current, and the voltage range of described Vdp is between 0.2V to 0.6V.
6. the control method of memory array as claimed in claim 1, it is characterized in that, when described memory array carries out erase operation, the wordline that the memory cell chosen connects, the first control line, the second control line, the bit line be connected with source electrode and the bit line be connected with drain electrode apply the 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage respectively;
The voltage range of described 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage is respectively 5V ~ 10V ,-10V ~-5V ,-10V ~-5V, 0V ~ 0.5V, 0V ~ 0.5V.
7. the control method of memory array as claimed in claim 6, it is characterized in that, described 11 voltage, the 12 voltage, the 13 voltage, the 14 voltage and the 15 voltage are respectively 8V ,-7V ,-7V, 0V, 0V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510821864.4A CN105304136A (en) | 2015-11-24 | 2015-11-24 | Control method for memory array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510821864.4A CN105304136A (en) | 2015-11-24 | 2015-11-24 | Control method for memory array |
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| Publication Number | Publication Date |
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| CN105304136A true CN105304136A (en) | 2016-02-03 |
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| CN201510821864.4A Pending CN105304136A (en) | 2015-11-24 | 2015-11-24 | Control method for memory array |
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- 2015-11-24 CN CN201510821864.4A patent/CN105304136A/en active Pending
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Application publication date: 20160203 |