CN105304050A - Over-current protection circuit and over-current protection method - Google Patents
Over-current protection circuit and over-current protection method Download PDFInfo
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- CN105304050A CN105304050A CN201510810936.5A CN201510810936A CN105304050A CN 105304050 A CN105304050 A CN 105304050A CN 201510810936 A CN201510810936 A CN 201510810936A CN 105304050 A CN105304050 A CN 105304050A
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Abstract
The embodiment of the invention discloses an over-current protection circuit and an over-current protection method. The over-current protection circuit comprises a power source management chip, a level shifter, a GOA circuit driven by a baseplate array row and a current detection circuit, wherein the current detection circuit comprises a current detection module, a current-to-voltage converter and a voltage comparer, a first control end of the power source management chip is connected to an input end of the level shifter, an output end of the level shifter is connected to an input end of the GOA circuit, an output end of the GOA circuit is connected to a first input end of the current detection module, an output end of the current detection module is connected to an input end of the current-to-voltage converter, an output end of the current-to-voltage converter is connected to an input end of the power source management chip, and a second control end of the power source management chip is connected to a second input end of the current detection module. By implementing the over-current protection circuit and the over-current protection method disclosed by the embodiment of the invention, a panel can be prevented from being burnt.
Description
Technical field
The present invention relates to technical field of liquid crystal display, be specifically related to a kind of current foldback circuit and over-current protection method.
Background technology
Base plate array row cutting (GateOnArray, GOA) technology, a kind of by thin film transistor (TFT) (ThinFilmTransistor, TFT) gated sweep driving circuit is produced on the technology on substrate, adopt GOA technology, the panel border of liquid crystal display (LiquidCrystalDisplay, LCD) can be reduced, reduce cost of products.The grid voltage of the every a line TFT in liquid crystal display can be provided by GOA circuit, in GOA circuit, when the grid voltage that general use level translation device (LevelShifter) produces clock control signal control TFT is opened or closes, and each clock control signal can control a line or multirow TFT.In the manufacture process of liquid crystal display, if the frame glue of liquid crystal display is not tight, easily causes between the GOA circuit in panel and occur short circuit, cause panel to burn out.
Summary of the invention
The embodiment of the present invention provides a kind of current foldback circuit and over-current protection method, and panel can be prevented to be burned.
Embodiment of the present invention first aspect; provide a kind of current foldback circuit; comprise power management chip, level translator, base plate array row cutting GOA circuit and current-sensing circuit, described current-sensing circuit comprises current detecting module, electric current to electric pressure converter and voltage comparator, wherein:
First control end of described power management chip connects the input end of described level translator, the output terminal of described level translator connects the input end of described GOA circuit, the output terminal of described GOA circuit connects the first input end of described current detecting module, the output terminal of described current detecting module connects the input end of described electric current to electric pressure converter, described electric current of stating connects described power management chip input end to the output terminal of electric pressure converter, and the second control end of described power management chip connects the second input end of described current detecting module;
Second control end of described power management chip exports control signal and controls the unlatching of described current detecting module or close, first control end of described power management chip exports the first control signal and controls described level translator and produce each bar GOA circuit that multiple clock control signal exports described GOA circuit to, when described current detecting module is opened, described current detecting module is detected the current signal of described each bar GOA circuit respectively and is enlarged into watt current signal and exports described electric current to electric pressure converter, described watt current signal is converted to effective voltage signal to electric pressure converter and exports described voltage comparator to by described electric current, when described voltage comparator judges that described effective voltage signal is greater than the reference voltage of described voltage comparator, high level signal is exported to described power management chip, stop exporting to control described power management chip, one is only had for raster data model high voltage VGH signal in described multiple clock control signal, other are raster data model low-voltage VGL signal.
In the first possible implementation of embodiment of the present invention first aspect, described current detecting module comprises the first field effect transistor T1, the second field effect transistor T2, the 3rd field effect transistor T3 and the 4th field effect transistor T4, wherein:
The output terminal of described GOA circuit connects the drain electrode of described second field effect transistor T2 and the drain electrode of described 4th field effect transistor T4, the source electrode of described second field effect transistor T2 is all connected gate drive voltage VGH with the source electrode of described first field effect transistor T1, and the source electrode of described 3rd field effect transistor T3 is all connected gate drive voltage VGL with the source electrode of described 4th field effect transistor T4;
Second control end of described power management chip exports high level signal or the low level signal grid to the grid of described first field effect transistor T1, the grid of described second field effect transistor T2, the grid of described 3rd field effect transistor T3 and described 4th field effect transistor T4, to control described first field effect transistor T1 and described second field effect transistor T2 opens simultaneously, or control described 3rd field effect transistor T and described 4th field effect transistor T4 opens simultaneously.
In conjunction with the first possible implementation of embodiment of the present invention first aspect, in the implementation that the second of embodiment of the present invention first aspect is possible, described first field effect transistor T1 and described second field effect T2 is NMOS tube, and described 3rd field effect transistor T3 and described 4th field effect T4 is PMOS.
In conjunction with the implementation that the second of embodiment of the present invention first aspect is possible, in the third possible implementation of embodiment of the present invention first aspect, the channel width-over-length ratio of described first field effect transistor T1 is K times of the channel width-over-length ratio of described second field effect transistor T2, the channel width-over-length ratio of described 3rd field effect transistor T3 is K times of the channel width-over-length ratio of described 4th field effect transistor T4, and described K is greater than 1.
In conjunction with the third possible implementation of embodiment of the present invention first aspect, in the 4th kind of possible implementation of embodiment of the present invention first aspect, described electric current comprises the first electric current to electric pressure converter C1 to electric pressure converter, described voltage comparator comprises the first voltage comparator U1, wherein:
Described first electric current is to the drain electrode of the described first field effect transistor T1 of input end connection of electric pressure converter C1, described first electric current is to the in-phase input end of the described first voltage comparator U1 of output terminal connection of electric pressure converter C1, and the output terminal of described first voltage comparator U1 connects the first input end of power management chip.
In conjunction with the 4th kind of possible implementation of embodiment of the present invention first aspect, in the 5th kind of possible implementation of embodiment of the present invention first aspect, described electric current comprises the second electric current to electric pressure converter C2 to electric pressure converter, described voltage comparator comprises the second voltage comparator U2, wherein:
Described second electric current is to the drain electrode of the described 3rd field effect transistor T1 of input end connection of electric pressure converter C2, described second electric current is to the in-phase input end of the described second voltage comparator U1 of output terminal connection of electric pressure converter C2, and the output terminal of described second voltage comparator U1 connects the second input end of power management chip.
In conjunction with the 4th kind of possible implementation of embodiment of the present invention first aspect, in the 6th kind of possible implementation of embodiment of the present invention first aspect, described first electric current comprises the first resistance R1 to electric pressure converter C1, the first end of described first resistance R1 connects the drain electrode of described first field effect transistor T1, the second end ground connection of described first resistance R1.
In conjunction with the 5th kind of possible implementation of embodiment of the present invention first aspect, in the 7th kind of possible implementation of embodiment of the present invention first aspect, described second electric current comprises the second resistance R2 to electric pressure converter C2, the first end of described second resistance R2 connects the drain electrode of described 3rd field effect transistor T3, the second end ground connection of described second resistance R2.
Embodiment of the present invention second aspect, based on the first current foldback circuit provided to any one possible implementation in the 7th kind of embodiment of the present invention first aspect or embodiment of the present invention first aspect, provides a kind of over-current protection method, comprising:
Described power management chip output described first controls signal to described level translator and produces multiple clock control signal to control described level translator, and only have one in described multiple clock control signal for VGH signal, other are VGL signal;
Described multiple clock control signal is exported to each GOA circuit of described GOA circuit by described level translator, and wherein, each clock control signal controls at least one GOA circuit, and the GOA circuit that any two clock control signals control is all not identical;
Described current-sensing circuit to detect between each GOA circuit described whether short circuit respectively;
If so, described power management chip stops exporting.
In the first possible implementation of embodiment of the present invention second aspect, described current-sensing circuit to detect between each GOA circuit described whether short circuit respectively, comprising:
Described current detecting module is detected the current signal of current GOA circuit and is enlarged into watt current signal;
Described watt current signal is converted to effective voltage signal to electric pressure converter and exports described voltage comparator to by described electric current;
When described voltage comparator judges that described effective voltage signal is greater than the reference voltage of described voltage comparator, determine short circuit between described current GOA circuit and other GOA circuits.
In the embodiment of the present invention, when current detecting module is opened, current detecting module is detected the current signal of each bar GOA circuit respectively and is enlarged into watt current signal and exports electric current to electric pressure converter, watt current signal is converted to effective voltage signal to electric pressure converter and exports voltage comparator to by electric current, when voltage comparator judges that effective voltage signal is greater than the reference voltage of voltage comparator, export high level signal to power management chip, stop exporting to control power management chip.Implement the embodiment of the present invention, when can there is short circuit between GOA circuit, control power management chip and stop exporting, panel can be prevented to be burned.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of current foldback circuit disclosed in the embodiment of the present invention;
Fig. 2 is another kind of current foldback circuit disclosed in the embodiment of the present invention;
Fig. 3 is a kind of clock work signal schematic representation disclosed in the embodiment of the present invention;
Fig. 4 is a kind of clock control signal schematic diagram disclosed in the embodiment of the present invention;
Fig. 5 is another kind of current foldback circuit disclosed in the embodiment of the present invention;
Fig. 6 is another kind of current foldback circuit disclosed in the embodiment of the present invention;
Fig. 7 is the process flow diagram of a kind of over-current protection method disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in embodiment of the present invention, the technical scheme in embodiment of the present invention is clearly and completely described.Obviously, described embodiment is a part of embodiment of the present invention, instead of whole embodiment.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all should belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of current foldback circuit and over-current protection method, and panel can be prevented to be burned.Below be described in detail respectively.
Refer to Fig. 1, Fig. 1 is a kind of current foldback circuit disclosed in the embodiment of the present invention.As shown in Figure 1; current foldback circuit described in the present embodiment; comprise power management chip 101, level translator 102, base plate array row cutting GOA circuit 103 and current-sensing circuit 104; current-sensing circuit 104 comprises current detecting module 1041, electric current to electric pressure converter 1042 and voltage comparator 1043, wherein:
First control end of power management chip 101 connects the input end of level translator 102, the output terminal of level translator 102 connects the input end of GOA circuit 103, the output terminal of GOA circuit 103 connects the first input end of current detecting module 1041, the output terminal of current detecting module 1041 connects the input end of electric current to electric pressure converter 1042, state output terminal connection power management chip 101 input end of electric current to electric pressure converter 1042, the second control end of power management chip 101 connects the second input end of current detecting module 1041;
Second control end of power management chip 101 exports control signal control current detecting module 1041 and opens or close, first control end of power management chip 101 exports the first control signal control level converter 102 and produces each bar GOA circuit that multiple clock control signal exports GOA circuit 103 to, when current detecting module 1041 is opened, current detecting module 1041 is detected the current signal of each bar GOA circuit respectively and is enlarged into watt current signal and exports electric current to electric pressure converter 1042, watt current signal is converted to effective voltage signal to electric pressure converter 1042 and exports voltage comparator 1043 to by electric current, when voltage comparator 1043 judges that effective voltage signal is greater than the reference voltage of voltage comparator 1043, high level signal is exported to power management chip 101, stop exporting to control power management chip 101, one is only had for raster data model high voltage VGH signal in multiple clock control signal, other are raster data model low-voltage VGL signal.
In the embodiment of the present invention, first control end of power management chip 101 exports the first control signal control level converter 102 (LevelShifter, LS) multiple clock control signal (CLK-OUT1 is produced, CLK-OUT12, CLK-OUT3 etc.), the multiple clock control signals produced can be exported to the base plate array row cutting (GateOnArray in panel by level translator, GOA) circuit 103, each clock control signal can control the unlatching of a GOA circuit or multirow GOA circuit or closedown (such as, each clock control signal controls unlatching or the closedown of 4 GOA circuits or 8 GOA circuits), GOA circuit 103 can comprise many GOA circuits, every a line thin film transistor (TFT) (ThinFilmTransistor in every bar GOA connection panel of LCD, TFT) grid.
In the embodiment of the present invention, second control end of power management chip 101 exports control signal control current detecting module 1041 and opens or close, control signal can comprise high level signal or low level signal, when the second control end of power management chip 101 disconnects the connection with current detecting module 1041, stream detecting module 1041 is closed, when the second control end high level signal or the low level signal of power management chip 101, current detecting module 1041 is opened.
In the embodiment of the present invention, when current detecting module 1041 is opened, current detecting module 1041 detects the current signal of a certain bar GOA circuit, if there is short circuit in this GOA circuit and another GOA circuit, namely there is short circuit in the clock signal on this GOA circuit and the clock signal on another GOA circuit, if the clock signal on this GOA circuit is raster data model high voltage VGH signal, clock signal on another GOA circuit is raster data model low-voltage VGL signal, then produce big current signal between this GOA circuit and another GOA circuit, this big current signal is enlarged into watt current signal and exports electric current to electric pressure converter 1042 by current detecting module 1041, watt current signal is converted to effective voltage signal to electric pressure converter 1042 and exports voltage comparator 1043 to by electric current, when voltage comparator 1043 judges that effective voltage signal is greater than the reference voltage of voltage comparator 1043, high level signal is exported to power management chip 101, stop exporting to control power management chip 101.Implement the embodiment of the present invention, when can there is short circuit between GOA circuit, control power management chip and stop exporting, panel can be prevented to be burned.
Optionally, as shown in Figure 2, current detecting module 1041 comprises the first field effect transistor T1, the second field effect transistor T2, the 3rd field effect transistor T3 and the 4th field effect transistor T4, wherein:
The output terminal of GOA circuit 103 connects the drain electrode of the second field effect transistor T2 and the drain electrode of the 4th field effect transistor T4, the source electrode of the second field effect transistor T2 is all connected gate drive voltage VGH with the source electrode of the first field effect transistor T1, and the source electrode of the 3rd field effect transistor T3 is all connected gate drive voltage VGL with the source electrode of the 4th field effect transistor T4;
The grid of the second control end output high level signal of power management chip 101 or the grid of low level signal to the first field effect transistor T1, the grid of the second field effect transistor T2, the grid of the 3rd field effect transistor T3 and the 4th field effect transistor T4, to control the first field effect transistor T1 and the second field effect transistor T2 opens simultaneously, or control the 3rd field effect transistor T and the 4th field effect transistor T4 and open simultaneously.
Optionally, as shown in Figure 2, the first field effect transistor T1 and the second field effect T2 is NMOS tube, and the 3rd field effect transistor T3 and the 4th field effect T4 is PMOS.
Optionally, as shown in Figure 2, the channel width-over-length ratio of the first field effect transistor T1 is K times of the channel width-over-length ratio of the second field effect transistor T2, and the channel width-over-length ratio of the 3rd field effect transistor T3 is K times of the channel width-over-length ratio of the 4th field effect transistor T4, and K is greater than 1.
In the embodiment of the present invention, due under identical source-drain electrode bias voltage, channel width-over-length ratio is larger, drain voltage is larger, the channel width-over-length ratio of the first field effect transistor T1 is K times of the channel width-over-length ratio of the second field effect transistor T2, the leakage current of the first field effect transistor T1 is K times of the leakage current of the second field effect transistor T2, the channel width-over-length ratio of the 3rd field effect transistor T3 is K times of the channel width-over-length ratio of the 4th field effect transistor T4, the leakage current of the 3rd field effect transistor T3 is K times of the leakage current of the 4th field effect transistor T4, T1, T2, T4, the channel width-over-length ratio of T4 can be set by the processing procedure of field effect transistor.Current detecting module 1041 export electric current to electric pressure converter after the current signal of a certain bar GOA circuit detected can being amplified K times, and current detecting module 1041 export electric current to electric pressure converter 1042 after the current signal of a certain bar GOA circuit of detecting can being amplified K times.Because the short-circuit current between GOA circuit is often smaller, just can detect, so current detecting module 1041 is for amplifying the GOA detected short-circuit current after needing amplification.
Optionally, electric current comprises the first electric current to electric pressure converter C1 to electric pressure converter 1042, and voltage comparator 1043 comprises the first voltage comparator U1, wherein:
First electric current connects the drain electrode of the first field effect transistor T1 to the input end of electric pressure converter C1, first electric current connects the in-phase input end of the first voltage comparator U1 to the output terminal of electric pressure converter C1, and the output terminal of the first voltage comparator U1 connects the first input end of power management chip 101.
Optionally, electric current comprises the second electric current to electric pressure converter C2 to electric pressure converter 1042, and voltage comparator 1043 comprises the second voltage comparator U2, wherein:
Second electric current is to the drain electrode of input end connection the 3rd field effect transistor T1 of electric pressure converter C2, second electric current connects the in-phase input end of the second voltage comparator U1 to the output terminal of electric pressure converter C2, and the output terminal of the second voltage comparator U1 connects the second input end of power management chip 101.
In the embodiment of the present invention, when level translator 102 works, level translator 102 produces multiple clock work signal, as shown in Figure 3, Fig. 3 is a kind of clock work signal schematic representation disclosed in the embodiment of the present invention, for example, comprise CLK-OUT1, CLK-OUT2, CLK-OUT3 and CLK-OUT4, different clock work signals exports different GOA circuits to, such as, CLK-OUT1 exports a GOA circuit to, CLK-OUT2 exports the 5th GOA circuit to, CLK-OUT3 exports the 9th GOA circuit to, CLK-OUT4 exports the 13 GOA circuit to, as can be seen from Figure 3, at dotted line place (a certain moment as shown in Figure 3), if short circuit between a GOA circuit and the 5th GOA circuit, now, VGH signal (CLK-OUT1 as shown in Figure 3) on one GOA circuit and short circuit between the VGL signal (CLK-OUT2 as shown in Figure 3) on the 5th circuit, big current is produced between one GOA circuit and the 5th GOA circuit, GOA circuit can be burnt out, thus burn out panel.
The embodiment of the present invention is burned in order to panel when preventing GOA circuit from occurring short circuit, when liquid crystal display is started shooting, level translator 102 produces multiple clock control signal, as shown in Figure 4, Fig. 4 is a kind of clock control signal schematic diagram disclosed in the embodiment of the present invention, for example, comprise CLK-OUT1, CLK-OUT2, CLK-OUT3 and CLK-OUT4, different clock control signals exports different GOA circuits to, such as, CLK-OUT1 exports a GOA circuit to, CLK-OUT2 exports the 5th GOA circuit to, CLK-OUT3 exports the 9th GOA circuit to, CLK-OUT4 exports the 13 GOA circuit to, as can be seen from Figure 4, CLK-OUT1 is only had to be VGH signal, CLK-OUT2, CLK-OUT3 and CLK-OUT4 is VGL signal.
Below for Fig. 4, the principle of current foldback circuit is set forth, specific as follows:
When the clock control signal (CLK-OUT1 as in Fig. 4) on a certain GOA circuit that current detecting module 1041 is detected is for VGH signal, when second control end of power management chip 101 exports high level signal, first field effect transistor T1 and the second field effect transistor T2 opens, if not there is not short circuit, then the drain current I of the second field effect transistor T2 with other GOA circuits (the GOA circuit that the GOA circuit exported as the CLK-OUT2 in Fig. 4, CLK-OUT3 export and the GOA circuit that CLK-OUT4 exports) in this GOA line
d2be almost 0, the drain current I of the first field effect transistor T1
d1for I
d2k doubly, I
d1also less, the first electric current to electric pressure converter C1 by I
d1be converted to effective voltage also less, effective voltage signal is less than the reference voltage VREF1 of voltage comparator U1, voltage comparator U1 output low level signal, and power management chip 101 works on; If there is short circuit, then the drain current I of the second field effect transistor T2 between this GOA line and other GOA circuits (as the GOA circuit that the CLK-OUT2 in Fig. 4 exports)
d2comparatively large, the drain current I of the first field effect transistor T1
d1for I
d2k doubly, the first electric current to electric pressure converter C1 by I
d1be converted to effective voltage also comparatively large, effective voltage signal is greater than the reference voltage VREF1 of voltage comparator U1, and voltage comparator U1 exports high level signal, and power management chip 101 stops exporting, and the GOA circuit in panel of LCD can be protected not to be burned.
When the clock control signal on a certain GOA circuit that current detecting module 1041 is detected is VGL signal (CLK-OUT2 as in Fig. 4), when second control end of power management chip 101 exports high level signal, first field effect transistor T1 and the second field effect transistor T2 opens, if not there is not short circuit with other GOA circuits (CLK-OUT1 as in Fig. 4) in this GOA line, then the drain current I of the second field effect transistor T2
d2be almost 0, the drain current I of the first field effect transistor T1
d1for I
d2k doubly, I
d1also less, the first electric current to electric pressure converter C1 by I
d1be converted to effective voltage also less, effective voltage signal is less than the reference voltage VREF1 of voltage comparator U1, voltage comparator U1 output low level signal, and power management chip 101 works on; If there is short circuit in this GOA line and other GOA circuits (CLK-OUT1 as in Fig. 4), then the drain current I of the second field effect transistor T2
d2comparatively large, the drain current I of the first field effect transistor T1
d1for I
d2k doubly, the first electric current to electric pressure converter C1 by I
d1be converted to effective voltage also comparatively large, effective voltage signal is greater than the reference voltage VREF1 of voltage comparator U1, and voltage comparator U1 exports high level signal, and power management chip 101 stops exporting, and the GOA circuit in panel of LCD can be protected not to be burned.
Optionally, as shown in Figure 5, Fig. 5 is another kind of current foldback circuit disclosed in the embodiment of the present invention; wherein; first electric current comprises the first resistance R1 to electric pressure converter C1, and the first end of the first resistance R1 connects the drain electrode of the first field effect transistor T1, the second end ground connection of the first resistance R1.
Optionally, as shown in Figure 6, Fig. 6 is another kind of current foldback circuit disclosed in the embodiment of the present invention; wherein; second electric current comprises the second resistance R2 to electric pressure converter C2, and the first end of the second resistance R2 connects the drain electrode of the 3rd field effect transistor T3, the second end ground connection of the second resistance R2.
Refer to Fig. 7, Fig. 7 is the process flow diagram of a kind of over-current protection method disclosed in the embodiment of the present invention, and as shown in Figure 7, the over-current protection method described by the embodiment of the present invention comprises the steps:
701, power management chip output first controls signal to level translator and produces multiple clock control signal with control level converter, and only have one in multiple clock control signal for VGH signal, other are VGL signal.
In the embodiment of the present invention, level translator can produce multiple clock control signal, and only have one in multiple clock control signal for VGH signal, other are VGL signal.
702, multiple clock control signal is exported to each GOA circuit of GOA circuit by level translator, and wherein, each clock control signal controls at least one GOA circuit, and the GOA circuit that any two clock control signals control is all not identical.
In the embodiment of the present invention, each clock control signal controls at least one GOA circuit, and such as, a clock control signal can control 4 GOA circuits or 8 GOA circuits, and wherein, the GOA circuit that any two clock control signals control is all not identical.
703, current-sensing circuit to detect between each GOA circuit whether short circuit respectively, if so, performs step 704, if not, continues to perform step 703.
In the embodiment of the present invention, current-sensing circuit can to detect between each GOA circuit whether short circuit respectively, and current-sensing circuit detects the electric current in each GOA circuit respectively, when the electric current in this GOA circuit exceedes preset value, determines this GOA line short.
In the embodiment that some are feasible, step 703 can comprise:
11) current detecting module is detected the current signal of current GOA circuit and is enlarged into watt current signal;
12) watt current signal is converted to effective voltage signal to electric pressure converter and exports voltage comparator to by electric current;
13), when voltage comparator judges that effective voltage signal is greater than the reference voltage of voltage comparator, short circuit between current GOA circuit and other GOA circuits is determined.
In the embodiment of the present invention, current-sensing circuit can comprise current detecting module, electric current to electric pressure converter and voltage comparator, current detecting module is detected the current signal of current GOA circuit and is enlarged into watt current signal, watt current signal is converted to effective voltage signal to electric pressure converter and exports voltage comparator to by electric current, when voltage comparator judges that effective voltage signal is greater than the reference voltage of voltage comparator, voltage comparator exports high level signal to power management chip, performs step 704.
704, power management chip stops exporting.
In the embodiment of the present invention, when power management chip receives the high level signal of voltage comparator output, power management chip stops exporting, and namely power management chip stops exporting the first control signal to level translator; When power management chip receives the high level signal of voltage comparator output, power management chip closes (shutdown), stops exporting to make power management chip.
In the embodiment of the present invention, when current detecting module is opened, current detecting module is detected the current signal of each bar GOA circuit respectively and is enlarged into watt current signal and exports electric current to electric pressure converter, watt current signal is converted to effective voltage signal to electric pressure converter and exports voltage comparator to by electric current, when voltage comparator judges that effective voltage signal is greater than the reference voltage of voltage comparator, export high level signal to power management chip, stop exporting to control power management chip.Implement the embodiment of the present invention, when can there is short circuit between GOA circuit, control power management chip and stop exporting, panel can be prevented to be burned.
A kind of current foldback circuit provided the embodiment of the present invention above and over-current protection method are described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a current foldback circuit; it is characterized in that; comprise power management chip, level translator, base plate array row cutting GOA circuit and current-sensing circuit, described current-sensing circuit comprises current detecting module, electric current to electric pressure converter and voltage comparator, wherein:
First control end of described power management chip connects the input end of described level translator, the output terminal of described level translator connects the input end of described GOA circuit, the output terminal of described GOA circuit connects the first input end of described current detecting module, the output terminal of described current detecting module connects the input end of described electric current to electric pressure converter, described electric current of stating connects described power management chip input end to the output terminal of electric pressure converter, and the second control end of described power management chip connects the second input end of described current detecting module;
Second control end of described power management chip exports control signal and controls the unlatching of described current detecting module or close, first control end of described power management chip exports the first control signal and controls described level translator and produce each bar GOA circuit that multiple clock control signal exports described GOA circuit to, when described current detecting module is opened, described current detecting module is detected the current signal of described each bar GOA circuit respectively and is enlarged into watt current signal and exports described electric current to electric pressure converter, described watt current signal is converted to effective voltage signal to electric pressure converter and exports described voltage comparator to by described electric current, when described voltage comparator judges that described effective voltage signal is greater than the reference voltage of described voltage comparator, high level signal is exported to described power management chip, stop exporting to control described power management chip, one is only had for raster data model high voltage VGH signal in described multiple clock control signal, other are raster data model low-voltage VGL signal.
2. current foldback circuit according to claim 1, is characterized in that, described current detecting module comprises the first field effect transistor T1, the second field effect transistor T2, the 3rd field effect transistor T3 and the 4th field effect transistor T4, wherein:
The output terminal of described GOA circuit connects the drain electrode of described second field effect transistor T2 and the drain electrode of described 4th field effect transistor T4, the source electrode of described second field effect transistor T2 is all connected gate drive voltage VGH with the source electrode of described first field effect transistor T1, and the source electrode of described 3rd field effect transistor T3 is all connected gate drive voltage VGL with the source electrode of described 4th field effect transistor T4;
Second control end of described power management chip exports high level signal or the low level signal grid to the grid of described first field effect transistor T1, the grid of described second field effect transistor T2, the grid of described 3rd field effect transistor T3 and described 4th field effect transistor T4, to control described first field effect transistor T1 and described second field effect transistor T2 opens simultaneously, or control described 3rd field effect transistor T and described 4th field effect transistor T4 opens simultaneously.
3. current foldback circuit according to claim 2, is characterized in that, described first field effect transistor T1 and described second field effect T2 is NMOS tube, and described 3rd field effect transistor T3 and described 4th field effect T4 is PMOS.
4. current foldback circuit according to claim 3; it is characterized in that; the channel width-over-length ratio of described first field effect transistor T1 is K times of the channel width-over-length ratio of described second field effect transistor T2; the channel width-over-length ratio of described 3rd field effect transistor T3 is K times of the channel width-over-length ratio of described 4th field effect transistor T4, and described K is greater than 1.
5. current foldback circuit according to claim 4, is characterized in that, described electric current comprises the first electric current to electric pressure converter C1 to electric pressure converter, and described voltage comparator comprises the first voltage comparator U1, wherein:
Described first electric current is to the drain electrode of the described first field effect transistor T1 of input end connection of electric pressure converter C1, described first electric current is to the in-phase input end of the described first voltage comparator U1 of output terminal connection of electric pressure converter C1, and the output terminal of described first voltage comparator U1 connects the first input end of power management chip.
6. current foldback circuit according to claim 5, is characterized in that, described electric current comprises the second electric current to electric pressure converter C2 to electric pressure converter, and described voltage comparator comprises the second voltage comparator U2, wherein:
Described second electric current is to the drain electrode of the described 3rd field effect transistor T1 of input end connection of electric pressure converter C2, described second electric current is to the in-phase input end of the described second voltage comparator U1 of output terminal connection of electric pressure converter C2, and the output terminal of described second voltage comparator U1 connects the second input end of power management chip.
7. current foldback circuit according to claim 5; it is characterized in that; described first electric current comprises the first resistance R1 to electric pressure converter C1, and the first end of described first resistance R1 connects the drain electrode of described first field effect transistor T1, the second end ground connection of described first resistance R1.
8. current foldback circuit according to claim 6; it is characterized in that; described second electric current comprises the second resistance R2 to electric pressure converter C2, and the first end of described second resistance R2 connects the drain electrode of described 3rd field effect transistor T3, the second end ground connection of described second resistance R2.
9. based on an over-current protection method for any one of claim 1 ~ 8 current foldback circuit, it is characterized in that, comprising:
Described power management chip output described first controls signal to described level translator and produces multiple clock control signal to control described level translator, and only have one in described multiple clock control signal for VGH signal, other are VGL signal;
Described multiple clock control signal is exported to each GOA circuit of described GOA circuit by described level translator, and wherein, each clock control signal controls at least one GOA circuit, and the GOA circuit that any two clock control signals control is all not identical;
Described current-sensing circuit to detect between each GOA circuit described whether short circuit respectively;
If so, described power management chip stops exporting.
10. method according to claim 9, is characterized in that, described current-sensing circuit to detect between each GOA circuit described whether short circuit respectively, comprising:
Described current detecting module is detected the current signal of current GOA circuit and is enlarged into watt current signal;
Described watt current signal is converted to effective voltage signal to electric pressure converter and exports described voltage comparator to by described electric current;
When described voltage comparator judges that described effective voltage signal is greater than the reference voltage of described voltage comparator, determine short circuit between described current GOA circuit and other GOA circuits.
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| CN201510810936.5A CN105304050B (en) | 2015-11-20 | 2015-11-20 | A kind of current foldback circuit and over-current protection method |
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| CN201510810936.5A CN105304050B (en) | 2015-11-20 | 2015-11-20 | A kind of current foldback circuit and over-current protection method |
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