CN105304050B - A kind of current foldback circuit and over-current protection method - Google Patents
A kind of current foldback circuit and over-current protection method Download PDFInfo
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- CN105304050B CN105304050B CN201510810936.5A CN201510810936A CN105304050B CN 105304050 B CN105304050 B CN 105304050B CN 201510810936 A CN201510810936 A CN 201510810936A CN 105304050 B CN105304050 B CN 105304050B
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Abstract
The embodiment of the invention discloses a kind of current foldback circuit and over-current protection method; the current foldback circuit includes power management chip, level translator, base plate array row driving GOA circuits and current-sensing circuit; current-sensing circuit includes current detecting module, electric current to electric pressure converter and voltage comparator, wherein：First control end of power management chip connects the input of level translator, the output end of level translator connects the input of GOA circuits, the output end of GOA circuits connects the first input end of current detecting module, the output end of current detecting module connects electric current to the input of electric pressure converter, the output end for stating electric current to electric pressure converter connects power management chip input, and the second control end of power management chip connects the second input of current detecting module.Implement the embodiment of the present invention, panel can be prevented to be burned.
Description
Technical field
The present invention relates to technical field of liquid crystal display, and in particular to a kind of current foldback circuit and over-current protection method.
Background technology
Base plate array row driving (Gate On Array, GOA) technology is a kind of by thin film transistor (TFT) (Thin Film
Transistor, TFT) gated sweep drive circuit be produced on technology on substrate, using GOA technologies, liquid crystal can be reduced
The panel border of display (Liquid Crystal Display, LCD), reduces product cost.It is each in liquid crystal display
Row TFT grid voltage can be provided by GOA circuits, in GOA circuits, general to use level translation device (Level
Shifter when the grid voltage for) producing clock control signal control TFT is turned on and off, and each clock control signal can be with
Control a line or multirow TFT.In the manufacturing process of liquid crystal display, if the frame glue of liquid crystal display is not tight, easily cause
Occur short circuit between GOA circuits in panel, cause panel to burn out.
The content of the invention
The embodiment of the present invention provides a kind of current foldback circuit and over-current protection method, panel can be prevented to be burned.
There is provided a kind of current foldback circuit, including power management chip, level conversion for first aspect of the embodiment of the present invention
Device, base plate array row driving GOA circuits and current-sensing circuit, the current-sensing circuit include current detecting module, electric current
To electric pressure converter and voltage comparator, wherein：
First control end of the power management chip connects the input of the level translator, the level translator
Output end connect the inputs of the GOA circuits, the output end of the GOA circuits connects the first of the current detecting module
Input, the output end of the current detecting module connects the electric current to the input of electric pressure converter, and the electric current of stating is arrived
The output end of electric pressure converter connects the power management chip input, the second control end connection of the power management chip
Second input of the current detecting module；
Second control end output control signal of the power management chip controls the current detecting module to open or close
Close, the first control end of the power management chip exports the first control signal and controls the level translator to produce multiple clocks
Control signal is exported to each bar GOA circuits of the GOA circuits, when the current detecting module is opened, the current sense
Module detects the current signal of each bar GOA circuits and is enlarged into effective current signal output to the electric current to voltage respectively
The effective current signal is converted to effective voltage signal output to the voltage by converter, the electric current to electric pressure converter
Comparator, when the voltage comparator judges that the effective voltage signal is more than the reference voltage of the voltage comparator, to institute
State power management chip output high level signal, to control the power management chip to stop exporting, the multiple clock control
It is raster data model high voltage VGH signals to only have one in signal, and other are raster data model low-voltage VGL signals.
In the first possible implementation of first aspect of the embodiment of the present invention, the current detecting module includes the
One FET T1, the second FET T2, the 3rd FET T3 and the 4th FET T4, wherein：
The output end of the GOA circuits connects the drain electrode of the second FET T2 with the 4th FET T4's
Drain electrode, the source electrode of the source electrode of the second FET T2 and the first FET T1 is all connected with gate drive voltage VGH,
The source electrode of the 3rd FET T3 is all connected with gate drive voltage VGL with the source electrode of the 4th FET T4；
Second control end of the power management chip exports high level signal or low level signal to described first effect
Should pipe T1 grid, the grid of the second FET T2, the grid of the 3rd FET T3 and the 4th effect
Should pipe T4 grid, to control the first FET T1 and the second FET T2 to open simultaneously, or control is described
3rd FET T and the 4th FET T4 are opened simultaneously.
With reference to the first possible implementation of first aspect of the embodiment of the present invention, in first aspect of the embodiment of the present invention
Second of possible implementation in, the first FET T1 and the second field-effect T2 are NMOS tube, described
3rd FET T3 and the 4th field-effect T4 is PMOS.
With reference to second of possible implementation of first aspect of the embodiment of the present invention, in first aspect of the embodiment of the present invention
The third possible implementation in, the channel width-over-length ratio of the first FET T1 is the second FET T2
K times of channel width-over-length ratio, the channel width-over-length ratio of the 3rd FET T3 is the wide length of raceway groove of the 4th FET T4
K times of ratio, the K is more than 1.
With reference to the third possible implementation of first aspect of the embodiment of the present invention, in first aspect of the embodiment of the present invention
The 4th kind of possible implementation in, the electric current to electric pressure converter include the first electric current to electric pressure converter C1, it is described
Voltage comparator includes first voltage comparator U1, wherein：
First electric current to electric pressure converter C1 input connect the drain electrode of the first FET T1, and described the
One electric current to electric pressure converter C1 output end connect the in-phase input end of the first voltage comparator U1, the first voltage
Comparator U1 output end connects the first input end of power management chip.
With reference to the 4th kind of possible implementation of first aspect of the embodiment of the present invention, in first aspect of the embodiment of the present invention
The 5th kind of possible implementation in, the electric current to electric pressure converter include the second electric current to electric pressure converter C2, it is described
Voltage comparator includes second voltage comparator U2, wherein：
Second electric current to electric pressure converter C2 input connect the drain electrode of the 3rd FET T1, and described the
Two electric currents to electric pressure converter C2 output end connect the in-phase input end of the second voltage comparator U1, the second voltage
Comparator U1 output end connects the second input of power management chip.
With reference to the 4th kind of possible implementation of first aspect of the embodiment of the present invention, in first aspect of the embodiment of the present invention
The 6th kind of possible implementation in, first electric current to electric pressure converter C1 includes first resistor R1, first electricity
The first end for hindering R1 connects the drain electrode of the first FET T1, the second end ground connection of the first resistor R1.
With reference to the 5th kind of possible implementation of first aspect of the embodiment of the present invention, in first aspect of the embodiment of the present invention
The 7th kind of possible implementation in, second electric current to electric pressure converter C2 includes second resistance R2, second electricity
The first end for hindering R2 connects the drain electrode of the 3rd FET T3, the second end ground connection of the second resistance R2.
Second aspect of the embodiment of the present invention, based on first aspect of the embodiment of the present invention or first aspect of the embodiment of the present invention
To the current foldback circuit that any possible implementation in the 7th kind is provided, there is provided a kind of overcurrent protection side for the first
Method, including：
The power management chip exports first control signal to the level translator to control the level to turn
Parallel operation, which is produced in multiple clock control signals, the multiple clock control signal, only has one for VGH signals, and other are VGL
Signal；
The level translator exports the multiple clock control signal to each GOA circuit of the GOA circuits, its
In, each clock control signal controls at least one GOA circuits, and the GOA circuits of any two clock control signal control are not
It is identical；
The current-sensing circuit detect respectively between each described GOA circuit whether short circuit；
If so, the power management chip stops output.
In the first possible implementation of second aspect of the embodiment of the present invention, the current-sensing circuit is examined respectively
It is whether short-circuit between each GOA circuit described in surveying, including：
The current detecting module detects the current signal of current GOA circuits and is enlarged into effective current signal；
The effective current signal is converted to effective voltage signal output to the electricity by the electric current to electric pressure converter
Press comparator；
When the voltage comparator judges that the effective voltage signal is more than the reference voltage of the voltage comparator, it is determined that
It is short-circuit between the current GOA circuits and other GOA circuits.
In the embodiment of the present invention, when current detecting module is opened, current detecting module detects each bar GOA circuits respectively
Current signal is simultaneously enlarged into effective current signal output to electric current to electric pressure converter, and electric current to electric pressure converter is by effective current
Signal is converted to effective voltage signal output to voltage comparator, when voltage comparator judges that effective voltage signal is more than voltage ratio
Compared with device reference voltage when, to power management chip export high level signal, with control power management chip stop output.Implement
The embodiment of the present invention, when can occur short-circuit between GOA circuits, control power management chip stops output, can prevent face
Plate is burned.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of current foldback circuit disclosed in the embodiment of the present invention；
Fig. 2 is another current foldback circuit disclosed in the embodiment of the present invention；
Fig. 3 is a kind of clock work signal schematic representation disclosed in the embodiment of the present invention；
Fig. 4 is a kind of clock control signal schematic diagram disclosed in the embodiment of the present invention；
Fig. 5 is another current foldback circuit disclosed in the embodiment of the present invention；
Fig. 6 is another current foldback circuit disclosed in the embodiment of the present invention；
Fig. 7 is a kind of flow chart of over-current protection method disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in embodiment of the present invention, the technical scheme in embodiment of the present invention is carried out clear
Chu, it is fully described by.Obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiment party
Formula.Based on the embodiment in the present invention, those of ordinary skill in the art are obtained on the premise of creative work is not made
The every other embodiment obtained, should all belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of current foldback circuit and over-current protection method, panel can be prevented to be burned.With
It is lower to be described in detail respectively.
Referring to Fig. 1, Fig. 1 is a kind of current foldback circuit disclosed in the embodiment of the present invention.As shown in figure 1, the present embodiment
Described in current foldback circuit, including power management chip 101, level translator 102, base plate array row driving GOA lines
Road 103 and current-sensing circuit 104, current-sensing circuit 104 include current detecting module 1041, electric current to electric pressure converter
1042 and voltage comparator 1043, wherein：
First control end of power management chip 101 connects the input of level translator 102, level translator 102
The input of output end connection GOA circuits 103, the first input of the output end connection current detecting module 1041 of GOA circuits 103
End, the output end of current detecting module 1041 connects electric current to the input of electric pressure converter 1042, states electric current to voltage conversion
The output end connection input of power management chip 101 of device 1042, the second control end connection electric current of power management chip 101 is detectd
Survey the second input of module 1041；
Second control end output control signal control electric current detecting module 1041 of power management chip 101 is opened or closed
Close, the first control end of power management chip 101 exports clock when the first control signal control level translator 102 produces multiple
Signal output processed to GOA circuits 103 each bar GOA circuits, when current detecting module 1041 is opened, current detecting module 1041
The current signal of each bar GOA circuits is detected respectively and is enlarged into effective current signal output to electric current to electric pressure converter 1042,
Effective current signal is converted to effective voltage signal output to voltage comparator 1043, voltage by electric current to electric pressure converter 1042
It is defeated to power management chip 101 when comparator 1043 judges that effective voltage signal is more than the reference voltage of voltage comparator 1043
Go out high level signal, be that grid drives to control power management chip 101 to stop to only have one in output, multiple clock control signals
Dynamic high voltage VGH signals, other are raster data model low-voltage VGL signals.
In the embodiment of the present invention, the first control end of power management chip 101 exports the first control signal control level and turned
Parallel operation 102 (Level Shifter, LS) produces multiple clock control signals (CLK-OUT1, CLK-OUT12, CLK-OUT3 etc.),
Level translator can export multiple clock control signals of generation base plate array row driving (the Gate On to panel
Array, GOA) circuit 103, each clock control signal can control unlatching or the pass of a GOA circuit or multirow GOA circuits
(for example, each clock control signal controls being turned on and off for 4 GOA circuits or 8 GOA circuits) is closed, GOA circuits 103 can
With including a plurality of GOA circuits, per a line thin film transistor (TFT) (Thin Film in every GOA connection panel of LCD
Transistor, TFT) grid.
In the embodiment of the present invention, the second control end output control signal control electric current detecting mould of power management chip 101
Block 1041 is turned on and off, and control signal can include high level signal or low level signal, when the of power management chip 101
When two control ends disconnect the connection with current detecting module 1041, stream detecting module 1041 is closed, when power management chip 101
When the second control end high level signal or low level signal, current detecting module 1041 is opened.
In the embodiment of the present invention, when current detecting module 1041 is opened, current detecting module 1041 detects a certain bar GOA
The current signal of circuit, if the GOA circuits and another GOA circuit occur in that clock signal on short circuit, i.e. the GOA circuits and
Clock signal on another GOA circuit occurs in that short circuit, if the clock signal on the GOA circuits is raster data model high voltage
Clock signal on VGH signals, another GOA circuit is raster data model low-voltage VGL signals, then the GOA circuits and another
High current signal is produced between GOA circuits, it is defeated that the high current signal is enlarged into effective current signal by current detecting module 1041
Go out to electric current to electric pressure converter 1042, effective current signal is converted to effective voltage signal by electric current to electric pressure converter 1042
Output is to voltage comparator 1043, when voltage comparator 1043 judges that effective voltage signal is more than the reference of voltage comparator 1043
During voltage, high level signal is exported to power management chip 101, to control power management chip 101 to stop output.Implement this hair
Bright embodiment, when can occur short-circuit between GOA circuits, control power management chip stops output, can prevent panel quilt
Burn out.
Optionally, as shown in Fig. 2 current detecting module 1041 includes the first FET T1, the second FET T2, the
Three FET T3 and the 4th FET T4, wherein：
The output end of GOA circuits 103 connects the second FET T2 drain electrode and the 4th FET T4 drain electrode, second
FET T2 source electrode and the first FET T1 source electrode are all connected with gate drive voltage VGH, the 3rd FET T3's
Source electrode and the 4th FET T4 source electrode are all connected with gate drive voltage VGL；
Second control end of power management chip 101 exports high level signal or low level signal to the first FET T1
Grid, the second FET T2 grid, the 3rd FET T3 grid and the 4th FET T4 grid, to control
First FET T1 and the second FET T2 are opened simultaneously, or control the 3rd FET T and the 4th FET T4 same
Shi Kaiqi.
Optionally, as shown in Fig. 2 the first FET T1 and the second field-effect T2 are NMOS tube, the 3rd FET
T3 and the 4th field-effect T4 is PMOS.
Optionally, as shown in Fig. 2 the first FET T1 channel width-over-length ratio is the second FET T2 wide length of raceway groove
K times of ratio, the 3rd FET T3 channel width-over-length ratio is K times of the 4th FET T4 channel width-over-length ratio, and K is more than 1.
In the embodiment of the present invention, because under identical source-drain electrode bias, channel width-over-length ratio is bigger, and drain voltage is bigger, the
One FET T1 channel width-over-length ratio is K times of the second FET T2 channel width-over-length ratio, the first FET T1 leakage
Electric current is K times of the second FET T2 leakage current, and the 3rd FET T3 channel width-over-length ratio is the 4th FET T4
K times of channel width-over-length ratio, the 3rd FET T3 leakage current is K times of the 4th FET T4 leakage current, T1, T2,
T4, T4 channel width-over-length ratio can be set by the processing procedure of FET.Current detecting module 1041 can be by detecting
The current signals of a certain bar GOA circuits, which amplifies, to be exported after K times to electric current to electric pressure converter, and current detecting module 1041 can be by
The current signal of a certain bar GOA circuits of detecting amplifies to be exported to electric current to electric pressure converter 1042 after K times.Due to GOA circuits
Between short circuit current flow it is often smaller, it is necessary to can just be detected after amplifying, so current detecting module 1041 is used to detect
The GOA short circuit current flows measured are amplified.
Optionally, electric current includes the first electric current to electric pressure converter C1, voltage comparator 1043 to electric pressure converter 1042
Including first voltage comparator U1, wherein：
First electric current to electric pressure converter C1 input connect the first FET T1 drain electrode, the first electric current to voltage
Converter C1 output end connection first voltage comparator U1 in-phase input end, first voltage comparator U1 output end connection
The first input end of power management chip 101.
Optionally, electric current includes the second electric current to electric pressure converter C2, voltage comparator 1043 to electric pressure converter 1042
Including second voltage comparator U2, wherein：
Second electric current to electric pressure converter C2 input connect the 3rd FET T1 drain electrode, the second electric current to voltage
Converter C2 output end connection second voltage comparator U1 in-phase input end, second voltage comparator U1 output end connection
Second input of power management chip 101.
In the embodiment of the present invention, when level translator 102 works, level translator 102 produces multiple clock work signals,
As shown in figure 3, Fig. 3 is a kind of clock work signal schematic representation disclosed in the embodiment of the present invention, for example, including CLK-
OUT1, CLK-OUT2, CLK-OUT3 and CLK-OUT4, different clock work signal outputs to different GOA circuits, for example,
CLK-OUT1 is exported to the first GOA circuits, and CLK-OUT2 is exported to the 5th GOA circuits, and CLK-OUT3 is exported to the 9th GOA lines
Road, CLK-OUT4 is exported to the 13rd GOA circuits, from figure 3, it can be seen that at dotted line (a certain moment as shown in Figure 3),
If short-circuit between the first GOA circuits and the 5th GOA circuits, now, VGH signals on the first GOA circuits (as shown in Figure 3
CLK-OUT1 it is short-circuit between the VGL signals (CLK-OUT2 as shown in Figure 3)) and on the 5th circuit, the first GOA circuits and the 5th
High current is produced between GOA circuits, GOA circuits can be burnt out, so as to burn out panel.
The embodiment of the present invention is in order to prevent that panel is burned during the appearance short circuit of GOA circuits, when liquid crystal display is started shooting, electricity
Flat turn parallel operation 102 produces multiple clock control signals, as shown in figure 4, Fig. 4 is a kind of clock control disclosed in the embodiment of the present invention
Signal schematic representation, for example, including CLK-OUT1, CLK-OUT2, CLK-OUT3 and CLK-OUT4, different clock control letters
Number output to different GOA circuits, for example, CLK-OUT1 is exported to the first GOA circuits, CLK-OUT2 is exported to the 5th GOA lines
Road, CLK-OUT3 is exported to the 9th GOA circuits, and CLK-OUT4 is exported to the 13rd GOA circuits, figure 4, it is seen that only
CLK-OUT1 is VGH signals, and CLK-OUT2, CLK-OUT3 and CLK-OUT4 are VGL signals.
Below by taking Fig. 4 as an example, the principle to current foldback circuit is illustrated, specific as follows：
Clock control signal (the CLK- in such as Fig. 4 on a certain GOA circuits that current detecting module 1041 is detected
OUT1) be VGH signals when, power management chip 101 the second control end output high level signal when, the first FET T1 and
Second FET T2 is opened, if the GOA lines not with other GOA circuits (the GOA circuits of the CLK-OUT2 outputs in such as Fig. 4,
The GOA circuits of CLK-OUT3 outputs and the GOA circuits of CLK-OUT4 outputs) there is short circuit, then the second FET T2 drain electrode
Electric current ID2Almost 0, the first FET T1 drain current ID1For ID2K times, ID1Also smaller, the first electric current to voltage turns
Parallel operation C1 is by ID1Be converted to that effective voltage is also smaller, effective voltage signal is less than voltage comparator U1 reference voltage VREF1, electricity
Comparator U1 output low level signals are pressed, power management chip 101 works on；If the GOA lines and other GOA circuits (such as Fig. 4
In CLK-OUT2 outputs GOA circuits) between there is short circuit, then the second FET T2 drain current ID2It is larger, first
FET T1 drain current ID1For ID2K times, the first electric current to electric pressure converter C1 is by ID1Be converted to effective voltage also compared with
Greatly, effective voltage signal is more than voltage comparator U1 reference voltage VREF1, voltage comparator U1 output high level signals, electricity
Source control chip 101 stops output, and the GOA circuits in panel of LCD can be protected not to be burned.
When the clock control signal on a certain GOA circuits that current detecting module 1041 is detected is VGL signals (in such as Fig. 4
CLK-OUT2) when, during the second control end output high level signal of power management chip 101, the first FET T1 and the
Two FET T2 are opened, if the GOA lines short circuit, second do not occur with other GOA circuits (CLK-OUT1 in such as Fig. 4)
Effect pipe T2 drain current ID2Almost 0, the first FET T1 drain current ID1For ID2K times, ID1Also it is smaller, the
One electric current is to electric pressure converter C1 by ID1Be converted to that effective voltage is also smaller, effective voltage signal is less than voltage comparator U1 ginseng
Voltage VREF1 is examined, voltage comparator U1 output low level signals, power management chip 101 works on；If the GOA lines and its
There is short circuit by GOA circuits (CLK-OUT1 in such as Fig. 4) in him, then the second FET T2 drain current ID2It is larger, first
Effect pipe T1 drain current ID1For ID2K times, the first electric current to electric pressure converter C1 is by ID1Be converted to effective voltage also compared with
Greatly, effective voltage signal is more than voltage comparator U1 reference voltage VREF1, voltage comparator U1 output high level signals, electricity
Source control chip 101 stops output, and the GOA circuits in panel of LCD can be protected not to be burned.
Optionally, as shown in figure 5, Fig. 5 is another current foldback circuit disclosed in the embodiment of the present invention, wherein, first
Electric current includes first resistor R1 to electric pressure converter C1, and first resistor R1 first end connects the first FET T1 drain electrode,
First resistor R1 the second end ground connection.
Optionally, as shown in fig. 6, Fig. 6 is another current foldback circuit disclosed in the embodiment of the present invention, wherein, second
Electric current includes second resistance R2 to electric pressure converter C2, and second resistance R2 first end connects the 3rd FET T3 drain electrode,
Second resistance R2 the second end ground connection.
Referring to Fig. 7, Fig. 7 is a kind of flow chart of over-current protection method disclosed in the embodiment of the present invention, as shown in fig. 7,
Over-current protection method described by the embodiment of the present invention comprises the following steps：
701, it is multiple to control level translator to produce to level translator that power management chip exports the first control signal
It is VGH signals to only have one in clock control signal, multiple clock control signals, and other are VGL signals.
In the embodiment of the present invention, level translator can be produced in multiple clock control signals, multiple clock control signals
Only one is VGH signals, and other are VGL signals.
702, level translator exports multiple clock control signals to each GOA circuit of GOA circuits, wherein, each
Clock control signal controls at least one GOA circuits, and the GOA circuits of any two clock control signal control are differed.
In the embodiment of the present invention, each clock control signal controls at least one GOA circuits, for example, a clock control
Signal can control 4 GOA circuits or 8 GOA circuits, wherein, the GOA circuits of any two clock control signal control are not
It is identical.
703, current-sensing circuit detect respectively between each GOA circuit whether short circuit, if so, perform step 704, if
It is no, continue executing with step 703.
In the embodiment of the present invention, current-sensing circuit can detect respectively between each GOA circuit whether short circuit, electric current detects
Slowdown monitoring circuit detects the electric current in each GOA circuit respectively, when the electric current in the GOA circuits exceedes preset value, determines the GOA
Line short.
In some feasible embodiments, step 703 can include：
11) current detecting module detects the current signal of current GOA circuits and is enlarged into effective current signal；
12) effective current signal is converted to effective voltage signal output to voltage comparator by electric current to electric pressure converter；
13) when voltage comparator judges that effective voltage signal is more than the reference voltage of voltage comparator, it is determined that current GOA lines
It is short-circuit between road and other GOA circuits.
In the embodiment of the present invention, current-sensing circuit can include current detecting module, electric current to electric pressure converter and electricity
Comparator is pressed, current detecting module detects the current signal of current GOA circuits and is enlarged into effective current signal, electric current to voltage
Effective current signal is converted to effective voltage signal output to voltage comparator by converter, when voltage comparator judges effective electricity
When pressure signal is more than the reference voltage of voltage comparator, voltage comparator exports high level signal to power management chip, performs
Step 704.
704, power management chip stops output.
In the embodiment of the present invention, when power management chip receives the high level signal of voltage comparator output, power supply
Managing chip stops output, i.e. power management chip and stops exporting the first control signal to level translator；When power management core
When piece receives the high level signal of voltage comparator output, power management chip closes (shut down), so that power management
Chip stops output.
In the embodiment of the present invention, when current detecting module is opened, current detecting module detects each bar GOA circuits respectively
Current signal is simultaneously enlarged into effective current signal output to electric current to electric pressure converter, and electric current to electric pressure converter is by effective current
Signal is converted to effective voltage signal output to voltage comparator, when voltage comparator judges that effective voltage signal is more than voltage ratio
Compared with device reference voltage when, to power management chip export high level signal, with control power management chip stop output.Implement
The embodiment of the present invention, when can occur short-circuit between GOA circuits, control power management chip stops output, can prevent face
Plate is burned.
A kind of current foldback circuit and over-current protection method provided above the embodiment of the present invention has carried out detailed Jie
Continue, specific case used herein is set forth to the principle and embodiment of the present invention, the explanation of above example is only
It is the method and its core concept for being used to help understand the present invention；Simultaneously for those of ordinary skill in the art, according to this hair
Bright thought, be will change in specific embodiments and applications, in summary, and this specification content should not be managed
Solve as limitation of the present invention.
Claims (10)
1. a kind of current foldback circuit, it is characterised in that including power management chip, level translator, the driving of base plate array row
GOA circuits and current-sensing circuit, the current-sensing circuit include current detecting module, electric current to electric pressure converter and voltage
Comparator, wherein：
First control end of the power management chip connects the input of the level translator, the level translator it is defeated
Go out the input of the end connection GOA circuits, the output end of the GOA circuits connects the first input of the current detecting module
End, the output end of the current detecting module connects the electric current to the input of electric pressure converter, and the electric current to voltage turns
The output end of parallel operation connects the power management chip input, and the second control end of the power management chip connects the electricity
Flow the second input of detecting module；
Second control end output control signal of the power management chip controls the current detecting module to be turned on and off, institute
The first control end for stating power management chip exports the multiple clock controls of the first control signal control level translator generation
Signal output to the GOA circuits each bar GOA circuits, when the current detecting module is opened, the current detecting module
The current signal of each bar GOA circuits is detected respectively and is enlarged into effective current signal output to the electric current to voltage conversion
Device, the electric current to electric pressure converter by the effective current signal be converted to effective voltage signal output to the voltage ratio compared with
Device, when the voltage comparator judges that the effective voltage signal is more than the reference voltage of the voltage comparator, to the electricity
Source control chip exports high level signal, to control the power management chip to stop exporting, the multiple clock control signal
In only one be raster data model high voltage VGH signals, other are raster data model low-voltage VGL signals.
2. current foldback circuit according to claim 1, it is characterised in that the current detecting module includes first effect
Should pipe T1, the second FET T2, the 3rd FET T3 and the 4th FET T4, wherein：
The output end of the GOA circuits connects the drain electrode of the second FET T2 and the leakage of the 4th FET T4
Pole, the source electrode of the source electrode of the second FET T2 and the first FET T1 is all connected with gate drive voltage VGH, institute
The source electrode of the source electrode and the 4th FET T4 of stating the 3rd FET T3 is all connected with gate drive voltage VGL；
Second control end of the power management chip exports high level signal or low level signal to first FET
T1 grid, the grid of the second FET T2, the grid and the 4th FET of the 3rd FET T3
T4 grid, to control the first FET T1 and the second FET T2 to open simultaneously, or control the described 3rd
FET T and the 4th FET T4 are opened simultaneously.
3. current foldback circuit according to claim 2, it is characterised in that the first FET T1 and described second
Field-effect T2 is NMOS tube, and the 3rd FET T3 and the 4th field-effect T4 are PMOS.
4. current foldback circuit according to claim 3, it is characterised in that the wide length of raceway groove of the first FET T1
Than K times of channel width-over-length ratio that is the second FET T2, the channel width-over-length ratio of the 3rd FET T3 is described
K times of 4th FET T4 channel width-over-length ratio, the K is more than 1.
5. current foldback circuit according to claim 4, it is characterised in that the electric current to electric pressure converter includes first
Electric current is to electric pressure converter C1, and the voltage comparator includes first voltage comparator U1, wherein：
First electric current to electric pressure converter C1 input connect the drain electrode of the first FET T1, first electricity
The output end for flowing to electric pressure converter C1 connects the in-phase input end of the first voltage comparator U1, and the first voltage compares
Device U1 output end connects the first input end of power management chip.
6. current foldback circuit according to claim 5, it is characterised in that the electric current to electric pressure converter includes second
Electric current is to electric pressure converter C2, and the voltage comparator includes second voltage comparator U2, wherein：
Second electric current to electric pressure converter C2 input connect the drain electrode of the 3rd FET T1, second electricity
The output end for flowing to electric pressure converter C2 connects the in-phase input end of the second voltage comparator U1, and the second voltage compares
Device U1 output end connects the second input of power management chip.
7. current foldback circuit according to claim 5, it is characterised in that first electric current to electric pressure converter C1 bags
The first end for including first resistor R1, the first resistor R1 connects the drain electrode of the first FET T1, the first resistor
R1 the second end ground connection.
8. current foldback circuit according to claim 6, it is characterised in that second electric current to electric pressure converter C2 bags
The first end for including second resistance R2, the second resistance R2 connects the drain electrode of the 3rd FET T3, the second resistance
R2 the second end ground connection.
9. a kind of over-current protection method based on any one of claim 1~8 current foldback circuit, it is characterised in that including：
The power management chip exports first control signal to the level translator to control the level translator
Produce in multiple clock control signals, the multiple clock control signal and only have one for VGH signals, other are VGL signals；
The level translator exports the multiple clock control signal to each GOA circuit of the GOA circuits, wherein,
Each clock control signal controls at least one GOA circuits, the GOA circuits of any two clock control signal control not phase
Together；
The current-sensing circuit detect respectively between each described GOA circuit whether short circuit；
If so, the power management chip stops output.
10. method according to claim 9, it is characterised in that the current-sensing circuit detects each described GOA respectively
It is whether short-circuit between circuit, including：
The current detecting module detects the current signal of current GOA circuits and is enlarged into effective current signal；
The effective current signal is converted to effective voltage signal output to the voltage ratio by the electric current to electric pressure converter
Compared with device；
When the voltage comparator judges that the effective voltage signal is more than the reference voltage of the voltage comparator, it is determined that described
It is currently short-circuit between GOA circuits and other GOA circuits.
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| CN201510810936.5A CN105304050B (en) | 2015-11-20 | 2015-11-20 | A kind of current foldback circuit and over-current protection method |
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| CN201510810936.5A CN105304050B (en) | 2015-11-20 | 2015-11-20 | A kind of current foldback circuit and over-current protection method |
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