CN105293421A - Micro-electromechanical sensing device packaging structure and manufacturing process - Google Patents

Micro-electromechanical sensing device packaging structure and manufacturing process Download PDF

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CN105293421A
CN105293421A CN201410240872.5A CN201410240872A CN105293421A CN 105293421 A CN105293421 A CN 105293421A CN 201410240872 A CN201410240872 A CN 201410240872A CN 105293421 A CN105293421 A CN 105293421A
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chip
substrate
sense die
electrically connected
junction point
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李硕源
康成国
李敬燮
林秉俊
金�洙
金熙嬿
李胜茂
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN201810105495.2A priority Critical patent/CN108689382A/en
Priority to CN201410240872.5A priority patent/CN105293421A/en
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Abstract

The invention relates to a micro-electromechanical sensing device packaging structure and a manufacturing process, wherein the packaging structure comprises: the chip comprises a substrate, a chip, a first sensing die, a second sensing die and an encapsulation. The chip is disposed on the first surface of the substrate. The first sensing die is electrically connected with the chip. The second sensing die is stacked on the first surface of the chip, and the second sensing die is electrically connected with the chip. An encapsulant encapsulates the first surface of the substrate, a portion of the first surface of the chip, and the first sense die, wherein the encapsulant forms a gap to expose the second sense die. The packaging structure can reduce the packaging size and improve the electrical characteristics.

Description

微机电感测装置封装结构及制造工艺Micro-electromechanical sensing device packaging structure and manufacturing process

技术领域technical field

本发明涉及一种微机电感测装置封装结构及制造工艺。The invention relates to a package structure and a manufacturing process of a micro-electromechanical sensing device.

背景技术Background technique

在常规封装结构中,关于感测模块的封装,通常利用预先开模(pre-mold)设计,依据客制化的设计,于衬底上形成封胶,再进行后续封装制程。一般来说,常规预先开模设计的封装结构,其封装尺寸较大,成本也较高。In the conventional packaging structure, regarding the packaging of the sensing module, a pre-mold design is usually used. According to the customized design, a sealant is formed on the substrate, and then a subsequent packaging process is performed. Generally speaking, the conventional pre-molded package design has a large package size and high cost.

发明内容Contents of the invention

本揭露的一方面涉及一种微机电感测装置封装结构。在一实施例中,所述封装结构包括:衬底、芯片、第一感测裸片、第二感测裸片及封胶。所述衬底具有第一表面。所述芯片设置于所述衬底的所述第一表面,所述芯片具有第一表面。所述第一感测裸片与所述芯片电性连接。所述第二感测裸片堆叠于所述芯片的所述第一表面,且所述第二感测裸片与所述芯片电性连接。封胶包覆所述衬底的所述第一表面、所述芯片的部分第一表面及所述第一感测裸片,其中所述封胶形成缺口,以显露出所述第二感测裸片。One aspect of the present disclosure relates to a package structure of a MEMS sensing device. In one embodiment, the packaging structure includes: a substrate, a chip, a first sensing die, a second sensing die, and an encapsulant. The substrate has a first surface. The chip is disposed on the first surface of the substrate, and the chip has a first surface. The first sensing die is electrically connected to the chip. The second sensing die is stacked on the first surface of the chip, and the second sensing die is electrically connected to the chip. The encapsulant covers the first surface of the substrate, part of the first surface of the chip and the first sensing die, wherein the encapsulant forms a gap to expose the second sensing die.

所述封装结构的所述第二感测裸片堆叠于所述芯片的所述第一表面,故可降低封装尺寸,且对于具有所述封装结构的整体感测模块来说,还可进一步缩小其整体的体积,使得整体机构设计上可具有较大弹性。另外,所述第一感测裸片及所述第二感测裸片均直接电性连接所述芯片,使得电气路径缩短,以提升电气特性。The second sensing die of the packaging structure is stacked on the first surface of the chip, so the packaging size can be reduced, and for the overall sensing module with the packaging structure, it can be further reduced Its overall volume enables greater flexibility in overall mechanism design. In addition, both the first sensing die and the second sensing die are directly electrically connected to the chip, so that the electrical path is shortened to improve electrical characteristics.

本揭露的另一方面涉及一种微机电感测装置的制造工艺。在一实施例中,所述制造工艺包括以下步骤:(a)提供衬底,所述衬底具有第一表面;(b)设置芯片于所述衬底的所述第一表面,所述芯片具有第一表面;(c)设置第一感测裸片于所述芯片或所述衬底上;(d)电性连接所述芯片与所述衬底,及电性连接所述芯片与所述第一感测裸片;(e)注入封胶以包覆所述衬底的所述第一表面、所述芯片的部分第一表面及所述第一感测裸片,其中所述封胶形成缺口;(f)堆叠第二感测裸片于所述芯片的所述第一表面,且设置于所述缺口内;及(g)电性连接所述第二感测裸片与所述芯片。Another aspect of the disclosure relates to a manufacturing process of a MEMS sensing device. In one embodiment, the manufacturing process includes the following steps: (a) providing a substrate, the substrate has a first surface; (b) disposing a chip on the first surface of the substrate, the chip having a first surface; (c) setting a first sensing die on the chip or the substrate; (d) electrically connecting the chip to the substrate, and electrically connecting the chip to the substrate the first sensing die; (e) injecting encapsulant to cover the first surface of the substrate, part of the first surface of the chip and the first sensing die, wherein the encapsulation glue forming a gap; (f) stacking a second sensing die on the first surface of the chip and being disposed in the gap; and (g) electrically connecting the second sensing die to the first surface of the chip said chip.

利用本发明制造工艺,不须利用常规预先开模设计,无须预先开模及客制化的相关成本,故可降低成本。Utilizing the manufacturing process of the present invention, there is no need to use the conventional pre-molding design, and the related costs of pre-molding and customization are not required, so the cost can be reduced.

附图说明Description of drawings

图1显示本发明封装结构的一实施例的剖视示意图;FIG. 1 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

图2显示本发明封装结构的一实施例的剖视示意图;FIG. 2 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

图3显示本发明封装结构的一实施例的剖视示意图;FIG. 3 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

图4显示本发明封装结构的一实施例的剖视示意图;FIG. 4 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

图5显示本发明封装结构的一实施例的剖视示意图;5 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

图6显示本发明封装结构的一实施例的剖视示意图;6 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

图7A显示本发明封装结构的一实施例的剖视示意图;FIG. 7A shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

图7B显示本发明图7A的封装结构的上视示意图;FIG. 7B shows a schematic top view of the package structure of FIG. 7A of the present invention;

图8A至图8G显示本发明图1的封装结构的制造工艺的一实施例的示意图;8A to 8G are schematic diagrams showing an embodiment of the manufacturing process of the packaging structure of FIG. 1 of the present invention;

图9A至图9C显示本发明图7A封装结构的制造工艺的一实施例的示意图;9A to 9C are schematic diagrams showing an embodiment of the manufacturing process of the package structure of FIG. 7A of the present invention;

图10显示本发明的制造工艺的模具的一实施例的示意图;Fig. 10 shows the schematic diagram of an embodiment of the mold of manufacturing process of the present invention;

图11A至图11C显示本发明一封装结构的制造工艺的一实施例的示意图;及11A to 11C are schematic diagrams showing an embodiment of a manufacturing process of a packaging structure of the present invention; and

图12A至图12D显示本发明一封装结构的制造工艺的一实施例的示意图。12A to 12D are schematic diagrams showing an embodiment of a manufacturing process of a packaging structure of the present invention.

具体实施方式detailed description

参考图1,显示本发明封装结构的一实施例的剖视示意图。所述封装结构10包括:衬底11、芯片12、第一感测裸片13、第二感测裸片14、封胶15及凝胶(gel)19。Referring to FIG. 1 , a schematic cross-sectional view of an embodiment of the packaging structure of the present invention is shown. The packaging structure 10 includes: a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 14 , a sealant 15 and a gel 19 .

所述衬底11具有第一表面111。所述衬底11可为BT材质覆晶衬底、玻璃衬底、陶瓷衬底、铜箔衬底或是导线架(leadframe)。The substrate 11 has a first surface 111 . The substrate 11 can be a flip-chip substrate made of BT material, a glass substrate, a ceramic substrate, a copper foil substrate or a leadframe.

所述芯片12设置于所述衬底11的所述第一表面111,且与所述衬底11电性连接,所述芯片12具有第一表面121,所述芯片12例如是专用集成电路(Application-SpecificIntegratedCircuit,ASIC)。在一实施例中,所述芯片12的至少一第二导电接点123通过至少一第二导线17而电性连接于所述衬底11,所述至少一第二导电接点123设置于所述芯片12的所述第一表面121。The chip 12 is arranged on the first surface 111 of the substrate 11 and is electrically connected to the substrate 11. The chip 12 has a first surface 121. The chip 12 is, for example, an ASIC ( Application-Specific Integrated Circuit, ASIC). In one embodiment, at least one second conductive contact 123 of the chip 12 is electrically connected to the substrate 11 through at least one second wire 17, and the at least one second conductive contact 123 is disposed on the chip. The first surface 121 of 12.

所述第一感测裸片13设置于所述衬底11的所述第一表面111,且所述第一感测裸片13与所述芯片12电性连接。所述第一感测裸片13通过粘胶层(adhesivelayer,未绘示)而设置在所述衬底11的所述第一表面111。在一实施例中,利用至少一第一导线16电性连接所述第一感测裸片13与所述芯片12的至少一第一导电接点122,所述至少一第一导电接点122设置于所述芯片12的所述第一表面121。即,所述第一感测裸片13与所述芯片12直接电性连接,未再经由其它裸片等元件。并且,利用第一盖体21,覆盖于部分所述第一感测裸片13上,以保护所述第一感测裸片13。所述第一盖体21的材质可为硅(Si)。The first sensing die 13 is disposed on the first surface 111 of the substrate 11 , and the first sensing die 13 is electrically connected to the chip 12 . The first sensing die 13 is disposed on the first surface 111 of the substrate 11 through an adhesive layer (not shown). In one embodiment, at least one first conductive contact 122 of the first sensing die 13 and the chip 12 is electrically connected by at least one first wire 16, and the at least one first conductive contact 122 is disposed on The first surface 121 of the chip 12 . That is, the first sensing die 13 is directly electrically connected to the chip 12 without going through other dies and other components. Moreover, the first cover 21 is used to cover part of the first sensing die 13 to protect the first sensing die 13 . The material of the first cover 21 may be silicon (Si).

所述第二感测裸片14堆叠于所述芯片12的所述第一表面121,且所述第二感测裸片14与所述芯片12电性连接。在一实施例中,利用至少一第三导线18电性连接所述第二感测裸片14与所述芯片12的至少一第三导电接点124,所述至少一第三导电接点124设置于所述芯片12的所述第一表面121。即,所述第二感测裸片14与所述芯片12直接电性连接,未再经由其它裸片等元件。The second sensing die 14 is stacked on the first surface 121 of the chip 12 , and the second sensing die 14 is electrically connected to the chip 12 . In one embodiment, at least one third conductive contact 124 of the second sensing die 14 and the chip 12 is electrically connected by at least one third wire 18, and the at least one third conductive contact 124 is disposed on The first surface 121 of the chip 12 . That is, the second sensing die 14 is directly electrically connected to the chip 12 without going through other dies or other components.

所述封胶15包覆所述衬底11的所述第一表面111、所述芯片12的部分第一表面121及所述第一感测裸片13,其中所述封胶15形成缺口151,以显露出所述芯片12的所述第一表面121的一部分与所述第二感测裸片14。The sealant 15 covers the first surface 111 of the substrate 11 , part of the first surface 121 of the chip 12 and the first sensing die 13 , wherein the sealant 15 forms a gap 151 , to expose a part of the first surface 121 of the chip 12 and the second sensing die 14 .

所述凝胶19包覆所述至少一第三导线18及所述芯片12的所述至少一第三导电接点124,所以可以避免所述芯片12与所述第二传感器14的电性连接因显露于所述封胶15的所述缺口151而受损害。此外,由于所述凝胶15仅包覆部分所述芯片12,而非完整包覆所述芯片12,因此可以有效减少成本。所述凝胶19的材质例如可为环氧树脂(epoxy)或是硅凝胶(siliconegel)。The gel 19 covers the at least one third wire 18 and the at least one third conductive contact 124 of the chip 12, so that the electrical connection between the chip 12 and the second sensor 14 can be avoided due to The gap 151 exposed in the sealant 15 is damaged. In addition, because the gel 15 only covers part of the chip 12 instead of completely covering the chip 12 , the cost can be effectively reduced. The material of the gel 19 can be, for example, epoxy or silicone gel.

在一实施例中,所述封装结构10可应用于车辆的胎压监测系统(TierPressureMonitoringSystem,TPMS),所述第一感测裸片13可为加速度传感器(Accelerometersensor),且所述第二感测裸片14可为压力传感器(Pressuresensor)。所述第二感测裸片14用以感测轮胎的压力,因此不封装于封胶15内。所述第一感测裸片13用以感测车辆是否移动,并通过所述芯片12来决定所述第二感测裸片14是否进行感测轮胎的压力,如果车辆开动,所述第二感测裸片14方感测轮胎的压力,以节省电源。In one embodiment, the packaging structure 10 can be applied to a tire pressure monitoring system (Tier Pressure Monitoring System, TPMS) of a vehicle, the first sensing die 13 can be an acceleration sensor (Accelerometer sensor), and the second sensing The die 14 can be a pressure sensor. The second sensing die 14 is used for sensing the pressure of the tire, so it is not encapsulated in the encapsulant 15 . The first sensing die 13 is used to sense whether the vehicle is moving, and the chip 12 is used to determine whether the second sensing die 14 senses tire pressure. If the vehicle is running, the second The sensing die 14 senses the tire pressure to save power.

所述封装结构10的所述第二感测裸片14堆叠于所述芯片12的所述第一表面121,故可降低封装尺寸,且对于具有所述封装结构10的整体感测模块来说,还可进一步缩小其整体体积,使得整体机构设计上可具有较大弹性。另外,所述第一感测裸片13及所述第二感测裸片14均直接电性连接所述芯片12,使得电气路径缩短,以提升电气特性。The second sensing die 14 of the package structure 10 is stacked on the first surface 121 of the chip 12, so the package size can be reduced, and for the overall sensing module with the package structure 10 , and its overall volume can be further reduced, so that the overall mechanism design can have greater flexibility. In addition, both the first sensing die 13 and the second sensing die 14 are directly electrically connected to the chip 12 , so that the electrical path is shortened to improve electrical characteristics.

图2显示本发明封装结构的一实施例的剖视示意图。相较于图1的封装结构10,在图2的实施例中相同的元件予以相同元件编号。本发明封装结构20包括:衬底11、芯片12、第一感测裸片13、第二感测裸片14、封胶15、凝胶19与遮盖22。FIG. 2 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 2 are given the same component numbers. The packaging structure 20 of the present invention includes: a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 14 , a sealant 15 , a gel 19 and a cover 22 .

所述遮盖22覆盖于所述封胶15上及所述第二感测裸片14上方,以进一步保护所述第二感测裸片14。所述遮盖22具有孔洞(hole)以使置于所述缺口151的所述第二感测裸片14可以检测到外在环境,例如:气压、温度或湿度等。The cover 22 covers the encapsulant 15 and the second sensing die 14 to further protect the second sensing die 14 . The cover 22 has holes so that the second sensing die 14 placed in the gap 151 can detect the external environment, such as air pressure, temperature or humidity.

图3显示本发明封装结构的一实施例的剖视示意图。相较于图1的封装结构10,在图3的实施例中相同的元件予以相同元件编号。本发明封装结构30包括:衬底11、芯片12、第一感测裸片13、第二感测裸片14、封胶15与凝胶31。FIG. 3 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 3 are given the same component numbers. The packaging structure 30 of the present invention includes: a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 14 , a sealant 15 and a gel 31 .

所述凝胶31大致上填满所述缺口151,以完整包覆所述第二感测裸片14与所述第三导线18。所述凝胶31的上表面大致与所述封胶15的上表面齐平,另一实施例中,所述粘胶31的上表面可低于与所述封胶15的上表面。The gel 31 substantially fills the gap 151 to completely cover the second sensing die 14 and the third wire 18 . The upper surface of the gel 31 is substantially flush with the upper surface of the sealant 15 . In another embodiment, the upper surface of the glue 31 may be lower than the upper surface of the sealant 15 .

因凝胶31的特性与封胶15的特性不同,其硬度较封胶的硬度小,例如是硅凝胶(siliconegel),故可包覆所述第二感测裸片14与第三导线18,以避免所述芯片12与所述第二传感器14的电性连接因显露于所述封胶15的所述缺口151而受损害,且不影响所述第二感测裸片14的感测特性与第三导线18的电性连接。Because the properties of the gel 31 are different from those of the sealant 15, and its hardness is lower than that of the sealant, such as silicone gel, it can cover the second sensing die 14 and the third wire 18. In order to prevent the electrical connection between the chip 12 and the second sensor 14 from being damaged due to the gap 151 exposed in the encapsulant 15, and not affect the sensing of the second sensing die 14 The characteristic is electrically connected to the third wire 18 .

图4显示本发明封装结构的一实施例的剖视示意图。相较于图1的封装结构10,在图4的实施例中相同的元件予以相同元件编号。本发明封装结构40包括:衬底11、芯片12、第一感测裸片13、第二感测裸片42、封胶15、第二盖体41与凝胶43。FIG. 4 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 4 are given the same component numbers. The packaging structure 40 of the present invention includes: a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 42 , a sealant 15 , a second cover 41 and a gel 43 .

所述第二盖体41覆盖于部分所述第二感测裸片42上,以进一步保护所述第二感测裸片42。并且,凝胶43包覆所述至少一第三导线18及所述至少一第三导电接点124,以保护所述第三导线18及所述至少一第三导电接点124的电性连接,且凝胶43的高度约与所述第二盖体41的高度相当。The second cover 41 covers part of the second sensing die 42 to further protect the second sensing die 42 . Moreover, the gel 43 covers the at least one third wire 18 and the at least one third conductive contact 124 to protect the electrical connection between the third wire 18 and the at least one third conductive contact 124, and The height of the gel 43 is approximately equal to the height of the second cover 41 .

图5显示本发明封装结构的一实施例的剖视示意图。相较于图1的封装结构10,在图5的实施例中相同的元件予以相同元件编号。本发明封装结构50包括:衬底11、芯片52、第一感测裸片53、第二感测裸片14、封胶15及凝胶19。FIG. 5 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 5 are given the same component numbers. The packaging structure 50 of the present invention includes: a substrate 11 , a chip 52 , a first sensing die 53 , a second sensing die 14 , a sealant 15 and a gel 19 .

本发明封装结构50的所述第一感测裸片53与所述第二感测裸片14皆设置于所述所述芯片52的所述第一表面521,且所述第一感测裸片53通过所述第一导线16直接与所述芯片52电性连接,所述第二感测裸片14通过所述第三导线18直接与所述芯片52电性连接。Both the first sensing die 53 and the second sensing die 14 of the package structure 50 of the present invention are disposed on the first surface 521 of the chip 52 , and the first sensing die The chip 53 is directly electrically connected to the chip 52 through the first wire 16 , and the second sensing die 14 is directly electrically connected to the chip 52 through the third wire 18 .

图6显示本发明封装结构的一实施例的剖视示意图。相较于图1的封装结构10,在图6的实施例中相同的元件予以相同元件编号。本发明封装结构60包括:衬底61、芯片12、第一感测裸片63、第二感测裸片14、封胶15与凝胶19。FIG. 6 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 6 are given the same component numbers. The packaging structure 60 of the present invention includes: a substrate 61 , a chip 12 , a first sensing die 63 , a second sensing die 14 , a sealant 15 and a gel 19 .

本发明封装结构60的第一感测裸片63设置于衬底61的所述第一表面611,且第一感测裸片63与所述衬底61电性连接,如图6所示,第一感测裸片63透过第一导线16与衬底61电性连接,因此第一感测裸片63的感测讯号可以经由衬底61与第二导线17传送到芯片12,因此,本实施例的所述衬底61较佳地为有机衬底或陶瓷衬底。The first sensing die 63 of the package structure 60 of the present invention is disposed on the first surface 611 of the substrate 61, and the first sensing die 63 is electrically connected to the substrate 61, as shown in FIG. 6 , The first sensing die 63 is electrically connected to the substrate 61 through the first wire 16, so the sensing signal of the first sensing die 63 can be transmitted to the chip 12 through the substrate 61 and the second wire 17, therefore, The substrate 61 in this embodiment is preferably an organic substrate or a ceramic substrate.

图7A显示本发明封装结构的一实施例的剖视示意图,图7B显示本发明图7A的封装结构的上视示意图,其中图7B不包括图7A的封胶15及凝胶19。配合参考图7A及图7B,相较于图1的封装结构10,在图7A及7B的实施例中相同的元件予以相同元件编号。本发明封装结构70包括衬底11、芯片12、第一感测裸片13、第二感测裸片14、封胶15、凝胶19与封闭屏障71。7A shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention, and FIG. 7B shows a schematic top view of the packaging structure of FIG. 7A of the present invention, wherein FIG. 7B does not include the sealant 15 and the gel 19 of FIG. 7A. With reference to FIGS. 7A and 7B , compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIGS. 7A and 7B are numbered the same. The packaging structure 70 of the present invention includes a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 14 , a sealant 15 , a gel 19 and a sealing barrier 71 .

所述封闭屏障71设置于所述芯片12的所述第一表面121,且设置于所述第二感测裸片14及所述至少一第三导电接点124的周围,即设置于第二导电接点123与第三导电接点124之间,以及第二感测裸片14与第一导电接点122之间。所述封闭屏障(Dam)71可为环形或方形等,材料可为环氧树脂(epoxy)。利用所述封闭屏障71,可防止封胶15溢胶到所述至少一第三导电接点124,以保护第二感测裸片14与芯片12之间的电性连接。The sealing barrier 71 is disposed on the first surface 121 of the chip 12, and is disposed around the second sensing die 14 and the at least one third conductive contact 124, that is, disposed on the second conductive contact 124. Between the contact 123 and the third conductive contact 124 , and between the second sensing die 14 and the first conductive contact 122 . The sealing barrier (Dam) 71 can be circular or square, etc., and the material can be epoxy resin (epoxy). Utilizing the sealing barrier 71 can prevent the sealant 15 from overflowing to the at least one third conductive contact 124 to protect the electrical connection between the second sensing die 14 and the chip 12 .

图8A至图8G显示本发明图1的封装结构的制造工艺的一实施例的示意图。8A to 8G are schematic diagrams showing an embodiment of the manufacturing process of the package structure shown in FIG. 1 of the present invention.

参考图8A,提供衬底11,所述衬底11具有第一表面111。接着,设置芯片12于所述衬底11的所述第一表面111,所述芯片12具有第一表面121、第一导电接点122、第二导电接点123及至少一第三导电接点124。Referring to FIG. 8A , a substrate 11 having a first surface 111 is provided. Next, a chip 12 is disposed on the first surface 111 of the substrate 11 , the chip 12 has a first surface 121 , a first conductive contact 122 , a second conductive contact 123 and at least one third conductive contact 124 .

参考图8B,设置第一感测裸片13于所述衬底11的所述第一表面111,再设置第一盖体21以覆盖于部分所述第一感测裸片13上,保护所述第一感测裸片13。Referring to FIG. 8B , the first sensing die 13 is set on the first surface 111 of the substrate 11, and the first cover 21 is set to cover part of the first sensing die 13 to protect the first sensing die 13. The first sensing die 13 is described.

参考图8C,电性连接所述芯片12与所述衬底11,及电性连接所述芯片12与所述第一感测裸片13。在一实施例中,利用至少一第一导线16电性连接所述第一感测裸片13与所述芯片12的至少一第一导电接点122,及利用至少一第二导线17电性连接所述衬底11与所述芯片12的至少一第二导电接点123。芯片。Referring to FIG. 8C , the chip 12 is electrically connected to the substrate 11 , and the chip 12 is electrically connected to the first sensing die 13 . In one embodiment, at least one first conductive contact 122 of the first sensing die 13 and the chip 12 is electrically connected by at least one first wire 16 , and is electrically connected by at least one second wire 17 At least one second conductive contact 123 between the substrate 11 and the chip 12 . chip.

参考图8D,利用模具26及保护膜(film)27设置于所述芯片12的第一表面121,且与所述衬底11形成空间28。所述模具26具有相对应突出形状,且所述模具26的所述下表面261包括凹陷区262。所述保护膜27设置于所述模具26的下表面261,以避免模具26损害所述芯片12的第一表面121。Referring to FIG. 8D , a mold 26 and a protective film (film) 27 are provided on the first surface 121 of the chip 12 to form a space 28 with the substrate 11 . The mold 26 has a corresponding protruding shape, and the lower surface 261 of the mold 26 includes a recessed area 262 . The protection film 27 is disposed on the lower surface 261 of the mold 26 to prevent the mold 26 from damaging the first surface 121 of the chip 12 .

参考图8E,注入封胶15于所述空间28内,以包覆所述衬底11的所述第一表面111、所述芯片12的部分第一表面121及所述第一感测裸片13,由于模具26及保护膜27设置于所述芯片12的第一表面121,因所述模具26相对应突出形状,所述封胶15形成缺口151以显露所述芯片12的所述第一表面121。对封胶15进行烘烤使其交联。由于模具26具有凹陷区262,以容纳受挤压的部分所述保护膜27,使得所述保护膜27不会因受挤压而部分突出,造成所述保护膜27无法平整压附于所述芯片12的所述第一表面121,以确保封胶15不会溢胶至所述保护膜27下及所述芯片12的第一表面121之间。且所述保护膜27还可覆盖至少一第三导电接点124,使封胶15不会包覆至少一第三导电接点124。Referring to FIG. 8E , the encapsulant 15 is injected into the space 28 to cover the first surface 111 of the substrate 11 , part of the first surface 121 of the chip 12 and the first sensing die. 13. Since the mold 26 and the protective film 27 are disposed on the first surface 121 of the chip 12, and because the mold 26 corresponds to a protruding shape, the sealant 15 forms a gap 151 to expose the first surface 121 of the chip 12. Surface 121. The sealant 15 is baked to make it cross-linked. Because the mold 26 has a recessed area 262 to accommodate the extruded part of the protective film 27, so that the protective film 27 will not partially protrude due to extrusion, causing the protective film 27 to be unable to be flattened and attached to the The first surface 121 of the chip 12 is used to ensure that the sealant 15 does not overflow under the protection film 27 and between the first surface 121 of the chip 12 . Moreover, the protection film 27 can also cover at least one third conductive contact 124 so that the sealant 15 does not cover the at least one third conductive contact 124 .

参考图8F,堆叠第二感测裸片14于所述芯片12的所述第一表面121,且设置于所述缺口151内。Referring to FIG. 8F , the second sensing die 14 is stacked on the first surface 121 of the chip 12 and disposed in the gap 151 .

参考图8G,电性连接所述第二感测裸片14与所述芯片12。在一实施例中,利用至少一第三导线电性18连接所述第二感测裸片14与所述芯片12的至少一第三导电接点124。Referring to FIG. 8G , the second sensing die 14 is electrically connected to the chip 12 . In one embodiment, at least one third conductive contact 124 of the second sensing die 14 and the chip 12 is electrically connected by at least one third wire 18 .

本发明制造工艺另包括设置凝胶19的步骤,以凝胶19包覆所述至少一第三导线18及所述至少一第三导电接点124,如图1所示。The manufacturing process of the present invention further includes a step of disposing a gel 19 , covering the at least one third wire 18 and the at least one third conductive contact 124 with the gel 19 , as shown in FIG. 1 .

利用本发明制造工艺,不须利用常规预先开模技术,无须预先开模及客制化的相关成本,故可降低成本。并且,因凝胶19的硬化温度较封胶15的硬化温度低,先注入封胶15且硬化后再设置凝胶19及硬化,可提高封装结构产品的可靠度。Utilizing the manufacturing process of the present invention, it is not necessary to use the conventional pre-molding technology, and the related costs of pre-molding and customization are not required, so the cost can be reduced. Moreover, because the curing temperature of the gel 19 is lower than that of the sealant 15, the sealant 15 is injected and hardened first, and then the gel 19 is installed and hardened, which can improve the reliability of the packaging structure product.

图9A至图9C显示本发明图7A封装结构的制造工艺的一实施例的示意图,请配合参考图8A至图8B,在一实施例中,制作图7A的封装结构70中的提供衬底11、设置芯片12及设置第一感测裸片13的步骤,与图8A至图8B的步骤相同,不再叙述。9A to 9C show a schematic diagram of an embodiment of the manufacturing process of the packaging structure shown in FIG. 7A of the present invention. Please refer to FIGS. 8A to 8B. In one embodiment, the substrate 11 in the packaging structure 70 of FIG. 7A is manufactured. 1. The steps of disposing the chip 12 and disposing the first sensing die 13 are the same as those in FIG. 8A to FIG. 8B , and will not be described again.

参考图9A,设置封闭屏障71于芯片12的所述第一表面121上,且在所述至少一第三导电接点124周围外。接着,利用至少一第一导线16电性连接所述第一感测裸片13与所述芯片12的至少一第一导电接点122,及利用至少一第二导线17电性连接所述衬底11与所述芯片12的至少一第二导电接点123。Referring to FIG. 9A , a sealing barrier 71 is disposed on the first surface 121 of the chip 12 and outside the periphery of the at least one third conductive contact 124 . Next, use at least one first wire 16 to electrically connect the first sensing die 13 and at least one first conductive contact 122 of the chip 12, and use at least one second wire 17 to electrically connect the substrate 11 and at least one second conductive contact 123 of the chip 12 .

参考图9B,利用模具76设置于所述封闭屏障71上,且抵顶所述封闭屏障71。模具76与所述衬底11形成空间77,且模具76抵顶所述封闭屏障71。Referring to FIG. 9B , a mold 76 is used to set on the closure barrier 71 and abut against the closure barrier 71 . The mold 76 forms a space 77 with the substrate 11 , and the mold 76 abuts against the sealing barrier 71 .

参考图9C,注入所述封胶15于所述空间77内,由于模具76抵顶所述封闭屏障71,封胶15不会溢胶至所述模具76的下表面761与所述芯片12的第一表面121之间,故封胶15不会包覆至少一第三导电接点124而影响芯片12的电性连接。相较于图8D,因设置所述封闭屏障71,故不需要图8D的所述保护膜27。Referring to FIG. 9C , the sealant 15 is injected into the space 77. Since the mold 76 is against the sealing barrier 71, the sealant 15 will not overflow to the lower surface 761 of the mold 76 and the chip 12. Between the first surfaces 121 , the encapsulant 15 will not cover the at least one third conductive contact 124 and affect the electrical connection of the chip 12 . Compared with FIG. 8D , the protective film 27 in FIG. 8D is unnecessary due to the provision of the sealing barrier 71 .

请配合参考图8F至图8G,在一实施例中,后续制作图7的封装结构70的设置第二感测裸片14及电性连接第二感测裸片14与芯片12的步骤,与图8F至图8G的步骤相同,不再叙述。Please refer to FIG. 8F to FIG. 8G . In one embodiment, the subsequent manufacturing of the package structure 70 in FIG. The steps in FIG. 8F to FIG. 8G are the same and will not be described again.

图10显示本发明的制造工艺的模具36的一实施例的示意图,所述模具36具有主体361、至少一突出柱362及至少一缓冲材料363。所述主体361另具有至少一孔洞364以容置至少一突出柱362,缓冲材料363设置于突出柱362的底部。缓冲材料363可为O形环(O-ring)所述突出柱362的相对应突出形状用以形成如图1的缺口151。保护膜37包覆所述主体361与所述突出柱362。FIG. 10 shows a schematic diagram of an embodiment of a mold 36 in the manufacturing process of the present invention. The mold 36 has a main body 361 , at least one protruding post 362 and at least one cushioning material 363 . The main body 361 further has at least one hole 364 for accommodating at least one protruding post 362 , and the cushioning material 363 is disposed at the bottom of the protruding post 362 . The buffer material 363 can be an O-ring (O-ring) corresponding to the protruding shape of the protruding post 362 to form the notch 151 as shown in FIG. 1 . The protective film 37 covers the main body 361 and the protruding posts 362 .

由于所述突出柱362与所述主体361并非一体成型,其为可上下活动的装置,及缓冲材料363设置于突出柱362的底部,且所述缓冲材料363具有热阻性与弹性,即当芯片12具有高度差异时,可活动的突出柱362及具有弹性的缓冲材料363可以补偿芯片12的高度差异,避免所述突出柱362抵压芯片12时造成芯片12产生裂缝(crack)的情形,以提高产品良率。Since the protruding column 362 and the main body 361 are not integrally formed, it is a device that can move up and down, and the buffer material 363 is arranged at the bottom of the protruding column 362, and the buffer material 363 has thermal resistance and elasticity, that is, when When the chip 12 has a height difference, the movable protruding column 362 and the elastic buffer material 363 can compensate the height difference of the chip 12, and avoid cracks (cracks) in the chip 12 when the protruding column 362 is pressed against the chip 12. To improve product yield.

图11A至图11C显示本发明一封装结构的制造工艺的一实施例的示意图,请配合参考图8A至图8B,在一实施例中,制作所述封装结构中的提供衬底11、设置芯片12及设置第一感测裸片13的步骤,与图8A至图8B的步骤相同,不再叙述。11A to 11C show a schematic diagram of an embodiment of a manufacturing process of a packaging structure of the present invention. Please refer to FIGS. 8A to 8B. In one embodiment, the substrate 11 and the chip are provided in the packaging structure. 12 and the steps of setting the first sensing die 13 are the same as the steps in FIG. 8A to FIG. 8B , and will not be described again.

参考图11A,设置中空盒101于所述芯片12的所述第一表面121。所述中空盒101呈倒U形,其开口朝下,且设置于所述至少一第三导电接点124周围外。Referring to FIG. 11A , a hollow box 101 is disposed on the first surface 121 of the chip 12 . The hollow box 101 is in an inverted U shape with an opening facing downwards, and is disposed outside the periphery of the at least one third conductive contact 124 .

所述中空盒101定义中空的空间,且所述中空盒的材料可为金属、塑化物或碳化物等材质。The hollow box 101 defines a hollow space, and the material of the hollow box may be metal, plastic or carbide.

参考图11B,注入封胶25以包覆所述衬底11的所述第一表面111、所述芯片12的部分第一表面121、所述第一感测裸片13及所述中空盒101。由于所述中空盒101定义所述中空的空间,使得封胶15不会流至所述芯片12的所述中空盒101内的部分所述第一表面121。且因所述至少一第三导电接点124在所述中空盒101内,使封胶15不会包覆所述至少一第三导电接点124。相较于图8D及图9B,因设置所述中空盒101,故不需要图8D的相对应突出形状的模具26及保护膜27,也不需要图9B的封闭屏障71。另外,于其它实施例中(未绘示),所述中空盒101还可设置于所述衬底上或是任何需要形成一空间以容纳感测裸片之处,相较于使用特制模具制作出相对应的空间以容纳感测裸片较为弹性。Referring to FIG. 11B , the encapsulant 25 is injected to cover the first surface 111 of the substrate 11 , part of the first surface 121 of the chip 12 , the first sensing die 13 and the hollow box 101 . Since the hollow box 101 defines the hollow space, the encapsulant 15 will not flow to the part of the first surface 121 of the chip 12 inside the hollow box 101 . And because the at least one third conductive contact 124 is inside the hollow box 101 , the sealant 15 will not cover the at least one third conductive contact 124 . Compared with FIG. 8D and FIG. 9B , since the hollow box 101 is provided, the mold 26 and protective film 27 of corresponding protruding shape in FIG. 8D are not needed, nor is the sealing barrier 71 in FIG. 9B required. In addition, in other embodiments (not shown), the hollow box 101 can also be disposed on the substrate or any place where a space needs to be formed to accommodate the sensing die, compared to using a special mold to make It is more flexible to create a corresponding space to accommodate the sensing die.

参考图11C,研磨部分封胶25及部分中空盒101,使所述中空盒101成为环状侧壁102。在所述环状侧壁102内则形成缺口251。Referring to FIG. 11C , grinding part of the sealant 25 and part of the hollow box 101 makes the hollow box 101 a ring-shaped side wall 102 . A notch 251 is formed in the annular sidewall 102 .

请配合参考图8F至图8G,在一实施例中,后续在所述缺口251内设置第二感测裸片14及电性连接第二感测裸片14与芯片12的步骤,即环状侧壁102环绕第二感测裸片14,此步骤与图8F至图8G的步骤相同,不再叙述。Please refer to FIG. 8F to FIG. 8G . In one embodiment, the step of setting the second sensing die 14 in the gap 251 and electrically connecting the second sensing die 14 and the chip 12 is followed, that is, the annular The sidewall 102 surrounds the second sensing die 14 , and this step is the same as that shown in FIG. 8F to FIG. 8G , and will not be described again.

图12A至图12D显示本发明一封装结构的制造工艺的一实施例的示意图,请配合参考图8A至图8B,在一实施例中,制作所述封装结构中的提供衬底11、设置芯片12及设置第一感测裸片13的步骤,与图8A至图8B的步骤相同,不再叙述。12A to 12D show a schematic diagram of an embodiment of a manufacturing process of a packaging structure of the present invention. Please refer to FIGS. 8A to 8B. In one embodiment, the substrate 11 and the chip are provided in the packaging structure. 12 and the steps of setting the first sensing die 13 are the same as the steps in FIG. 8A to FIG. 8B , and will not be described again.

参考图12A,堆叠第二感测裸片14于所述芯片12的所述第一表面121。接着,电性连接所述第二感测裸片14与所述芯片12。在一实施例中,利用至少一第三导线电性18连接所述第二感测裸片14与所述芯片12的至少一第三导电接点124。Referring to FIG. 12A , a second sensing die 14 is stacked on the first surface 121 of the chip 12 . Next, electrically connect the second sensing die 14 and the chip 12 . In one embodiment, at least one third conductive contact 124 of the second sensing die 14 and the chip 12 is electrically connected by at least one third wire 18 .

参考图12B,设置中空盒103于所述芯片12的所述第一表面121。所述中空盒103呈倒U形,其开口朝下,且设置于所述第二感测裸片14及所述至少一第三导电接点124周围外。即,所述中空盒103罩于所述第二感测裸片14及所述至少一第三导电接点124外。所述中空盒103定义中空的空间,且所述第二感测裸片14及所述至少一第三导电接点124于所述中空的空间内。Referring to FIG. 12B , a hollow box 103 is disposed on the first surface 121 of the chip 12 . The hollow box 103 is in an inverted U shape with its opening facing downwards, and is disposed outside the periphery of the second sensing die 14 and the at least one third conductive contact 124 . That is, the hollow box 103 covers the second sensing die 14 and the at least one third conductive contact 124 . The hollow box 103 defines a hollow space, and the second sensing die 14 and the at least one third conductive contact 124 are in the hollow space.

参考图12C,注入封胶45以包覆所述衬底11的所述第一表面111、所述芯片12的部分第一表面121、所述第一感测裸片13及所述中空盒103。由于所述中空盒103定义所述中空的空间,使得封胶15不会流至所述芯片12的所述中空盒103内的部分所述第一表面121。且因所述第二感测裸片14及所述至少一第三导电接点124在所述中空盒103内,使封胶45不会包覆所述第二感测裸片14及所述至少一第三导电接点124。Referring to FIG. 12C , the encapsulant 45 is injected to cover the first surface 111 of the substrate 11 , part of the first surface 121 of the chip 12 , the first sensing die 13 and the hollow box 103 . Since the hollow box 103 defines the hollow space, the encapsulant 15 will not flow to the part of the first surface 121 of the chip 12 inside the hollow box 103 . And because the second sensing die 14 and the at least one third conductive contact 124 are inside the hollow box 103, the sealant 45 will not cover the second sensing die 14 and the at least one third conductive contact 124. A third conductive contact 124 .

参考图12D,研磨部分封胶45及部分中空盒103,使所述中空盒103成为环形侧壁104。在所述环形侧壁104内则形成缺口451。所述第二感测裸片14及所述至少一第三导电接点124在所述缺口451内。Referring to FIG. 12D , part of the sealant 45 and part of the hollow box 103 are ground to make the hollow box 103 into an annular side wall 104 . A notch 451 is formed in the annular sidewall 104 . The second sensing die 14 and the at least one third conductive contact 124 are in the gap 451 .

上述实施例仅为说明本发明的原理及其功效,而非用以限制本发明。因此,所属领域的技术人员对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如后述的权利要求书所列。The above-mentioned embodiments are only for illustrating the principles and effects of the present invention, but are not intended to limit the present invention. Therefore, those skilled in the art can modify and change the above embodiments without departing from the spirit of the present invention. The scope of rights of the present invention should be listed in the following claims.

Claims (15)

1. an encapsulating structure, it comprises:
Substrate, it has first surface;
Chip, it is arranged at the described first surface of described substrate, and described chip has first surface;
First sense die, itself and described chip are electrically connected;
Second sense die, it is stacked in the described first surface of described chip, and described second sense die and described chip are electrically connected; And
Sealing, the described first surface of its coated described substrate, the part first surface of described chip and described first sense die, wherein said sealing forms breach, to manifest described second sense die.
2. encapsulating structure according to claim 1,
It separately comprises at least one first wire and at least one first conductive junction point, described at least one first conductive junction point is arranged at the described first surface of described chip, and described at least one first wire is electrically connected described at least one first conductive junction point of described first sense die and described chip.
3. encapsulating structure according to claim 1,
It separately comprises at least one second wire and at least one second conductive junction point, described at least one second conductive junction point is arranged at the described first surface of described chip, and described at least one second wire is electrically connected described at least one second conductive junction point of described substrate and described chip.
4. encapsulating structure according to claim 1,
It separately comprises at least one privates and at least one 3rd conductive junction point, described at least one 3rd conductive junction point is arranged at the described first surface of described chip, and described at least one privates is electrically connected described at least one 3rd conductive junction point of described second sense die and described chip.
5. encapsulating structure according to claim 4,
It separately comprises gel, coated described at least one privates and described at least one 3rd conductive junction point.
6. encapsulating structure according to claim 5,
Coated described second sense die of wherein said gel.
7. encapsulating structure according to claim 1,
It separately comprises confinement barrier, is arranged at around described second sense die.
8. encapsulating structure according to claim 1,
It separately comprises annular sidewall around the second sense die, and described annular sidewall is arranged at the described first surface of described chip.
9. a manufacturing process for micro electronmechanical sensing apparatus, it comprises the following steps:
A () provides substrate, described substrate has first surface;
B () arranges chip in the described first surface of described substrate, described chip has first surface;
C () arranges the first sense die on described chip or described substrate;
D () is electrically connected described chip and described substrate, and be electrically connected described chip and described first sense die;
E () injects sealing with the part first surface of the described first surface of coated described substrate, described chip and described first sense die, wherein said sealing forms breach;
F () stacking second sense die in the described first surface of described chip, and is arranged in described breach; And
G () is electrically connected described second sense die and described chip.
10. manufacturing process according to claim 9,
Wherein in step (d), utilize at least one first wire to be electrically connected at least one first conductive junction point of described first sense die and described chip, and utilize at least one second wire to be electrically connected at least one second conductive junction point of described substrate and described chip.
11. manufacturing process according to claim 9,
Wherein in step (e); mould and diaphragm and described substrate is utilized to form space; to inject described sealing in described space; described diaphragm is arranged at the lower surface of described mould; and the described lower surface of described mould comprises depressed area, to hold the described diaphragm of extruded part.
12. manufacturing process according to claim 9,
Wherein in step (g), at least one privates is utilized to be electrically connected at least one 3rd conductive junction point of described second sense die and described chip.
13. manufacturing process according to claim 12,
It separately comprises the step arranging gel, with the coated described at least one privates of gel and described at least one 3rd conductive junction point.
14. manufacturing process according to claim 9,
Wherein in step (e); mould and diaphragm and described substrate is utilized to form space; to inject described sealing in described space; described mould comprises main body, at least one outstanding post and at least one padded coaming; described main body separately has at least one hole with accommodating described at least one outstanding post; padded coaming is arranged at the bottom of outstanding post, the corresponding outstanding shape of described outstanding post in order to form described breach, the coated described main body of described diaphragm and described outstanding post.
15. manufacturing process according to claim 9,
Wherein in step (e), separately comprise the following steps:
(e1) arrange hollow box in the described first surface of described chip, described hollow box is inverted U-shaped, and it is opening down, the space of described hollow box definition hollow;
(e2) sealing is injected with the part first surface of the described first surface of coated described substrate, described chip, described first sense die and described hollow box; And
(e3) means of abrasion sealing and part hollow box, makes described hollow box become annular sidewall, in described annular sidewall, then forms described breach.
CN201410240872.5A 2014-05-30 2014-05-30 Micro-electromechanical sensing device packaging structure and manufacturing process Pending CN105293421A (en)

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