CN105293421A - Micro-electromechanical sensing device packaging structure and manufacturing process - Google Patents

Abstract

The invention relates to a micro-electromechanical sensing device packaging structure and a manufacturing process, wherein the packaging structure comprises: the chip comprises a substrate, a chip, a first sensing die, a second sensing die and an encapsulation. The chip is disposed on the first surface of the substrate. The first sensing die is electrically connected with the chip. The second sensing die is stacked on the first surface of the chip, and the second sensing die is electrically connected with the chip. An encapsulant encapsulates the first surface of the substrate, a portion of the first surface of the chip, and the first sense die, wherein the encapsulant forms a gap to expose the second sense die. The packaging structure can reduce the packaging size and improve the electrical characteristics.

Description

Micro-electromechanical sensing device packaging structure and manufacturing process

technical field

The invention relates to a package structure and a manufacturing process of a micro-electromechanical sensing device.

Background technique

In the conventional packaging structure, regarding the packaging of the sensing module, a pre-mold design is usually used. According to the customized design, a sealant is formed on the substrate, and then a subsequent packaging process is performed. Generally speaking, the conventional pre-molded package design has a large package size and high cost.

Contents of the invention

One aspect of the present disclosure relates to a package structure of a MEMS sensing device. In one embodiment, the packaging structure includes: a substrate, a chip, a first sensing die, a second sensing die, and an encapsulant. The substrate has a first surface. The chip is disposed on the first surface of the substrate, and the chip has a first surface. The first sensing die is electrically connected to the chip. The second sensing die is stacked on the first surface of the chip, and the second sensing die is electrically connected to the chip. The encapsulant covers the first surface of the substrate, part of the first surface of the chip and the first sensing die, wherein the encapsulant forms a gap to expose the second sensing die.

The second sensing die of the packaging structure is stacked on the first surface of the chip, so the packaging size can be reduced, and for the overall sensing module with the packaging structure, it can be further reduced Its overall volume enables greater flexibility in overall mechanism design. In addition, both the first sensing die and the second sensing die are directly electrically connected to the chip, so that the electrical path is shortened to improve electrical characteristics.

Another aspect of the disclosure relates to a manufacturing process of a MEMS sensing device. In one embodiment, the manufacturing process includes the following steps: (a) providing a substrate, the substrate has a first surface; (b) disposing a chip on the first surface of the substrate, the chip having a first surface; (c) setting a first sensing die on the chip or the substrate; (d) electrically connecting the chip to the substrate, and electrically connecting the chip to the substrate the first sensing die; (e) injecting encapsulant to cover the first surface of the substrate, part of the first surface of the chip and the first sensing die, wherein the encapsulation glue forming a gap; (f) stacking a second sensing die on the first surface of the chip and being disposed in the gap; and (g) electrically connecting the second sensing die to the first surface of the chip said chip.

Utilizing the manufacturing process of the present invention, there is no need to use the conventional pre-molding design, and the related costs of pre-molding and customization are not required, so the cost can be reduced.

Description of drawings

FIG. 1 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

FIG. 2 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

FIG. 3 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

FIG. 4 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

5 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

6 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

FIG. 7A shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention;

FIG. 7B shows a schematic top view of the package structure of FIG. 7A of the present invention;

8A to 8G are schematic diagrams showing an embodiment of the manufacturing process of the packaging structure of FIG. 1 of the present invention;

9A to 9C are schematic diagrams showing an embodiment of the manufacturing process of the package structure of FIG. 7A of the present invention;

Fig. 10 shows the schematic diagram of an embodiment of the mold of manufacturing process of the present invention;

11A to 11C are schematic diagrams showing an embodiment of a manufacturing process of a packaging structure of the present invention; and

12A to 12D are schematic diagrams showing an embodiment of a manufacturing process of a packaging structure of the present invention.

detailed description

Referring to FIG. 1 , a schematic cross-sectional view of an embodiment of the packaging structure of the present invention is shown. The packaging structure 10 includes: a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 14 , a sealant 15 and a gel 19 .

The substrate 11 has a first surface 111 . The substrate 11 can be a flip-chip substrate made of BT material, a glass substrate, a ceramic substrate, a copper foil substrate or a leadframe.

The chip 12 is arranged on the first surface 111 of the substrate 11 and is electrically connected to the substrate 11. The chip 12 has a first surface 121. The chip 12 is, for example, an ASIC ( Application-Specific Integrated Circuit, ASIC). In one embodiment, at least one second conductive contact 123 of the chip 12 is electrically connected to the substrate 11 through at least one second wire 17, and the at least one second conductive contact 123 is disposed on the chip. The first surface 121 of 12.

The first sensing die 13 is disposed on the first surface 111 of the substrate 11 , and the first sensing die 13 is electrically connected to the chip 12 . The first sensing die 13 is disposed on the first surface 111 of the substrate 11 through an adhesive layer (not shown). In one embodiment, at least one first conductive contact 122 of the first sensing die 13 and the chip 12 is electrically connected by at least one first wire 16, and the at least one first conductive contact 122 is disposed on The first surface 121 of the chip 12 . That is, the first sensing die 13 is directly electrically connected to the chip 12 without going through other dies and other components. Moreover, the first cover 21 is used to cover part of the first sensing die 13 to protect the first sensing die 13 . The material of the first cover 21 may be silicon (Si).

The second sensing die 14 is stacked on the first surface 121 of the chip 12 , and the second sensing die 14 is electrically connected to the chip 12 . In one embodiment, at least one third conductive contact 124 of the second sensing die 14 and the chip 12 is electrically connected by at least one third wire 18, and the at least one third conductive contact 124 is disposed on The first surface 121 of the chip 12 . That is, the second sensing die 14 is directly electrically connected to the chip 12 without going through other dies or other components.

The sealant 15 covers the first surface 111 of the substrate 11 , part of the first surface 121 of the chip 12 and the first sensing die 13 , wherein the sealant 15 forms a gap 151 , to expose a part of the first surface 121 of the chip 12 and the second sensing die 14 .

The gel 19 covers the at least one third wire 18 and the at least one third conductive contact 124 of the chip 12, so that the electrical connection between the chip 12 and the second sensor 14 can be avoided due to The gap 151 exposed in the sealant 15 is damaged. In addition, because the gel 15 only covers part of the chip 12 instead of completely covering the chip 12 , the cost can be effectively reduced. The material of the gel 19 can be, for example, epoxy or silicone gel.

In one embodiment, the packaging structure 10 can be applied to a tire pressure monitoring system (Tier Pressure Monitoring System, TPMS) of a vehicle, the first sensing die 13 can be an acceleration sensor (Accelerometer sensor), and the second sensing The die 14 can be a pressure sensor. The second sensing die 14 is used for sensing the pressure of the tire, so it is not encapsulated in the encapsulant 15 . The first sensing die 13 is used to sense whether the vehicle is moving, and the chip 12 is used to determine whether the second sensing die 14 senses tire pressure. If the vehicle is running, the second The sensing die 14 senses the tire pressure to save power.

The second sensing die 14 of the package structure 10 is stacked on the first surface 121 of the chip 12, so the package size can be reduced, and for the overall sensing module with the package structure 10 , and its overall volume can be further reduced, so that the overall mechanism design can have greater flexibility. In addition, both the first sensing die 13 and the second sensing die 14 are directly electrically connected to the chip 12 , so that the electrical path is shortened to improve electrical characteristics.

FIG. 2 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 2 are given the same component numbers. The packaging structure 20 of the present invention includes: a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 14 , a sealant 15 , a gel 19 and a cover 22 .

The cover 22 covers the encapsulant 15 and the second sensing die 14 to further protect the second sensing die 14 . The cover 22 has holes so that the second sensing die 14 placed in the gap 151 can detect the external environment, such as air pressure, temperature or humidity.

FIG. 3 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 3 are given the same component numbers. The packaging structure 30 of the present invention includes: a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 14 , a sealant 15 and a gel 31 .

The gel 31 substantially fills the gap 151 to completely cover the second sensing die 14 and the third wire 18 . The upper surface of the gel 31 is substantially flush with the upper surface of the sealant 15 . In another embodiment, the upper surface of the glue 31 may be lower than the upper surface of the sealant 15 .

Because the properties of the gel 31 are different from those of the sealant 15, and its hardness is lower than that of the sealant, such as silicone gel, it can cover the second sensing die 14 and the third wire 18. In order to prevent the electrical connection between the chip 12 and the second sensor 14 from being damaged due to the gap 151 exposed in the encapsulant 15, and not affect the sensing of the second sensing die 14 The characteristic is electrically connected to the third wire 18 .

FIG. 4 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 4 are given the same component numbers. The packaging structure 40 of the present invention includes: a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 42 , a sealant 15 , a second cover 41 and a gel 43 .

The second cover 41 covers part of the second sensing die 42 to further protect the second sensing die 42 . Moreover, the gel 43 covers the at least one third wire 18 and the at least one third conductive contact 124 to protect the electrical connection between the third wire 18 and the at least one third conductive contact 124, and The height of the gel 43 is approximately equal to the height of the second cover 41 .

FIG. 5 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 5 are given the same component numbers. The packaging structure 50 of the present invention includes: a substrate 11 , a chip 52 , a first sensing die 53 , a second sensing die 14 , a sealant 15 and a gel 19 .

Both the first sensing die 53 and the second sensing die 14 of the package structure 50 of the present invention are disposed on the first surface 521 of the chip 52 , and the first sensing die The chip 53 is directly electrically connected to the chip 52 through the first wire 16 , and the second sensing die 14 is directly electrically connected to the chip 52 through the third wire 18 .

FIG. 6 shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. Compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIG. 6 are given the same component numbers. The packaging structure 60 of the present invention includes: a substrate 61 , a chip 12 , a first sensing die 63 , a second sensing die 14 , a sealant 15 and a gel 19 .

The first sensing die 63 of the package structure 60 of the present invention is disposed on the first surface 611 of the substrate 61, and the first sensing die 63 is electrically connected to the substrate 61, as shown in FIG. 6 , The first sensing die 63 is electrically connected to the substrate 61 through the first wire 16, so the sensing signal of the first sensing die 63 can be transmitted to the chip 12 through the substrate 61 and the second wire 17, therefore, The substrate 61 in this embodiment is preferably an organic substrate or a ceramic substrate.

7A shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention, and FIG. 7B shows a schematic top view of the packaging structure of FIG. 7A of the present invention, wherein FIG. 7B does not include the sealant 15 and the gel 19 of FIG. 7A. With reference to FIGS. 7A and 7B , compared with the package structure 10 of FIG. 1 , the same components in the embodiment of FIGS. 7A and 7B are numbered the same. The packaging structure 70 of the present invention includes a substrate 11 , a chip 12 , a first sensing die 13 , a second sensing die 14 , a sealant 15 , a gel 19 and a sealing barrier 71 .

The sealing barrier 71 is disposed on the first surface 121 of the chip 12, and is disposed around the second sensing die 14 and the at least one third conductive contact 124, that is, disposed on the second conductive contact 124. Between the contact 123 and the third conductive contact 124 , and between the second sensing die 14 and the first conductive contact 122 . The sealing barrier (Dam) 71 can be circular or square, etc., and the material can be epoxy resin (epoxy). Utilizing the sealing barrier 71 can prevent the sealant 15 from overflowing to the at least one third conductive contact 124 to protect the electrical connection between the second sensing die 14 and the chip 12 .

8A to 8G are schematic diagrams showing an embodiment of the manufacturing process of the package structure shown in FIG. 1 of the present invention.

Referring to FIG. 8A , a substrate 11 having a first surface 111 is provided. Next, a chip 12 is disposed on the first surface 111 of the substrate 11 , the chip 12 has a first surface 121 , a first conductive contact 122 , a second conductive contact 123 and at least one third conductive contact 124 .

Referring to FIG. 8B , the first sensing die 13 is set on the first surface 111 of the substrate 11, and the first cover 21 is set to cover part of the first sensing die 13 to protect the first sensing die 13. The first sensing die 13 is described.

Referring to FIG. 8C , the chip 12 is electrically connected to the substrate 11 , and the chip 12 is electrically connected to the first sensing die 13 . In one embodiment, at least one first conductive contact 122 of the first sensing die 13 and the chip 12 is electrically connected by at least one first wire 16 , and is electrically connected by at least one second wire 17 At least one second conductive contact 123 between the substrate 11 and the chip 12 . chip.

Referring to FIG. 8D , a mold 26 and a protective film (film) 27 are provided on the first surface 121 of the chip 12 to form a space 28 with the substrate 11 . The mold 26 has a corresponding protruding shape, and the lower surface 261 of the mold 26 includes a recessed area 262 . The protection film 27 is disposed on the lower surface 261 of the mold 26 to prevent the mold 26 from damaging the first surface 121 of the chip 12 .

Referring to FIG. 8E , the encapsulant 15 is injected into the space 28 to cover the first surface 111 of the substrate 11 , part of the first surface 121 of the chip 12 and the first sensing die. 13. Since the mold 26 and the protective film 27 are disposed on the first surface 121 of the chip 12, and because the mold 26 corresponds to a protruding shape, the sealant 15 forms a gap 151 to expose the first surface 121 of the chip 12. Surface 121. The sealant 15 is baked to make it cross-linked. Because the mold 26 has a recessed area 262 to accommodate the extruded part of the protective film 27, so that the protective film 27 will not partially protrude due to extrusion, causing the protective film 27 to be unable to be flattened and attached to the The first surface 121 of the chip 12 is used to ensure that the sealant 15 does not overflow under the protection film 27 and between the first surface 121 of the chip 12 . Moreover, the protection film 27 can also cover at least one third conductive contact 124 so that the sealant 15 does not cover the at least one third conductive contact 124 .

Referring to FIG. 8F , the second sensing die 14 is stacked on the first surface 121 of the chip 12 and disposed in the gap 151 .

Referring to FIG. 8G , the second sensing die 14 is electrically connected to the chip 12 . In one embodiment, at least one third conductive contact 124 of the second sensing die 14 and the chip 12 is electrically connected by at least one third wire 18 .

The manufacturing process of the present invention further includes a step of disposing a gel 19 , covering the at least one third wire 18 and the at least one third conductive contact 124 with the gel 19 , as shown in FIG. 1 .

Utilizing the manufacturing process of the present invention, it is not necessary to use the conventional pre-molding technology, and the related costs of pre-molding and customization are not required, so the cost can be reduced. Moreover, because the curing temperature of the gel 19 is lower than that of the sealant 15, the sealant 15 is injected and hardened first, and then the gel 19 is installed and hardened, which can improve the reliability of the packaging structure product.

9A to 9C show a schematic diagram of an embodiment of the manufacturing process of the packaging structure shown in FIG. 7A of the present invention. Please refer to FIGS. 8A to 8B. In one embodiment, the substrate 11 in the packaging structure 70 of FIG. 7A is manufactured. 1. The steps of disposing the chip 12 and disposing the first sensing die 13 are the same as those in FIG. 8A to FIG. 8B , and will not be described again.

Referring to FIG. 9A , a sealing barrier 71 is disposed on the first surface 121 of the chip 12 and outside the periphery of the at least one third conductive contact 124 . Next, use at least one first wire 16 to electrically connect the first sensing die 13 and at least one first conductive contact 122 of the chip 12, and use at least one second wire 17 to electrically connect the substrate 11 and at least one second conductive contact 123 of the chip 12 .

Referring to FIG. 9B , a mold 76 is used to set on the closure barrier 71 and abut against the closure barrier 71 . The mold 76 forms a space 77 with the substrate 11 , and the mold 76 abuts against the sealing barrier 71 .

Referring to FIG. 9C , the sealant 15 is injected into the space 77. Since the mold 76 is against the sealing barrier 71, the sealant 15 will not overflow to the lower surface 761 of the mold 76 and the chip 12. Between the first surfaces 121 , the encapsulant 15 will not cover the at least one third conductive contact 124 and affect the electrical connection of the chip 12 . Compared with FIG. 8D , the protective film 27 in FIG. 8D is unnecessary due to the provision of the sealing barrier 71 .

Please refer to FIG. 8F to FIG. 8G . In one embodiment, the subsequent manufacturing of the package structure 70 in FIG. The steps in FIG. 8F to FIG. 8G are the same and will not be described again.

FIG. 10 shows a schematic diagram of an embodiment of a mold 36 in the manufacturing process of the present invention. The mold 36 has a main body 361 , at least one protruding post 362 and at least one cushioning material 363 . The main body 361 further has at least one hole 364 for accommodating at least one protruding post 362 , and the cushioning material 363 is disposed at the bottom of the protruding post 362 . The buffer material 363 can be an O-ring (O-ring) corresponding to the protruding shape of the protruding post 362 to form the notch 151 as shown in FIG. 1 . The protective film 37 covers the main body 361 and the protruding posts 362 .

Since the protruding column 362 and the main body 361 are not integrally formed, it is a device that can move up and down, and the buffer material 363 is arranged at the bottom of the protruding column 362, and the buffer material 363 has thermal resistance and elasticity, that is, when When the chip 12 has a height difference, the movable protruding column 362 and the elastic buffer material 363 can compensate the height difference of the chip 12, and avoid cracks (cracks) in the chip 12 when the protruding column 362 is pressed against the chip 12. To improve product yield.

11A to 11C show a schematic diagram of an embodiment of a manufacturing process of a packaging structure of the present invention. Please refer to FIGS. 8A to 8B. In one embodiment, the substrate 11 and the chip are provided in the packaging structure. 12 and the steps of setting the first sensing die 13 are the same as the steps in FIG. 8A to FIG. 8B , and will not be described again.

Referring to FIG. 11A , a hollow box 101 is disposed on the first surface 121 of the chip 12 . The hollow box 101 is in an inverted U shape with an opening facing downwards, and is disposed outside the periphery of the at least one third conductive contact 124 .

The hollow box 101 defines a hollow space, and the material of the hollow box may be metal, plastic or carbide.

Referring to FIG. 11B , the encapsulant 25 is injected to cover the first surface 111 of the substrate 11 , part of the first surface 121 of the chip 12 , the first sensing die 13 and the hollow box 101 . Since the hollow box 101 defines the hollow space, the encapsulant 15 will not flow to the part of the first surface 121 of the chip 12 inside the hollow box 101 . And because the at least one third conductive contact 124 is inside the hollow box 101 , the sealant 15 will not cover the at least one third conductive contact 124 . Compared with FIG. 8D and FIG. 9B , since the hollow box 101 is provided, the mold 26 and protective film 27 of corresponding protruding shape in FIG. 8D are not needed, nor is the sealing barrier 71 in FIG. 9B required. In addition, in other embodiments (not shown), the hollow box 101 can also be disposed on the substrate or any place where a space needs to be formed to accommodate the sensing die, compared to using a special mold to make It is more flexible to create a corresponding space to accommodate the sensing die.

Referring to FIG. 11C , grinding part of the sealant 25 and part of the hollow box 101 makes the hollow box 101 a ring-shaped side wall 102 . A notch 251 is formed in the annular sidewall 102 .

Please refer to FIG. 8F to FIG. 8G . In one embodiment, the step of setting the second sensing die 14 in the gap 251 and electrically connecting the second sensing die 14 and the chip 12 is followed, that is, the annular The sidewall 102 surrounds the second sensing die 14 , and this step is the same as that shown in FIG. 8F to FIG. 8G , and will not be described again.

12A to 12D show a schematic diagram of an embodiment of a manufacturing process of a packaging structure of the present invention. Please refer to FIGS. 8A to 8B. In one embodiment, the substrate 11 and the chip are provided in the packaging structure. 12 and the steps of setting the first sensing die 13 are the same as the steps in FIG. 8A to FIG. 8B , and will not be described again.

Referring to FIG. 12A , a second sensing die 14 is stacked on the first surface 121 of the chip 12 . Next, electrically connect the second sensing die 14 and the chip 12 . In one embodiment, at least one third conductive contact 124 of the second sensing die 14 and the chip 12 is electrically connected by at least one third wire 18 .

Referring to FIG. 12B , a hollow box 103 is disposed on the first surface 121 of the chip 12 . The hollow box 103 is in an inverted U shape with its opening facing downwards, and is disposed outside the periphery of the second sensing die 14 and the at least one third conductive contact 124 . That is, the hollow box 103 covers the second sensing die 14 and the at least one third conductive contact 124 . The hollow box 103 defines a hollow space, and the second sensing die 14 and the at least one third conductive contact 124 are in the hollow space.

Referring to FIG. 12C , the encapsulant 45 is injected to cover the first surface 111 of the substrate 11 , part of the first surface 121 of the chip 12 , the first sensing die 13 and the hollow box 103 . Since the hollow box 103 defines the hollow space, the encapsulant 15 will not flow to the part of the first surface 121 of the chip 12 inside the hollow box 103 . And because the second sensing die 14 and the at least one third conductive contact 124 are inside the hollow box 103, the sealant 45 will not cover the second sensing die 14 and the at least one third conductive contact 124. A third conductive contact 124 .

Referring to FIG. 12D , part of the sealant 45 and part of the hollow box 103 are ground to make the hollow box 103 into an annular side wall 104 . A notch 451 is formed in the annular sidewall 104 . The second sensing die 14 and the at least one third conductive contact 124 are in the gap 451 .

The above-mentioned embodiments are only for illustrating the principles and effects of the present invention, but are not intended to limit the present invention. Therefore, those skilled in the art can modify and change the above embodiments without departing from the spirit of the present invention. The scope of rights of the present invention should be listed in the following claims.

Claims (15)

1. an encapsulating structure, it comprises:

Substrate, it has first surface;

Chip, it is arranged at the described first surface of described substrate, and described chip has first surface;

First sense die, itself and described chip are electrically connected;

Second sense die, it is stacked in the described first surface of described chip, and described second sense die and described chip are electrically connected; And

Sealing, the described first surface of its coated described substrate, the part first surface of described chip and described first sense die, wherein said sealing forms breach, to manifest described second sense die.

2. encapsulating structure according to claim 1,

It separately comprises at least one first wire and at least one first conductive junction point, described at least one first conductive junction point is arranged at the described first surface of described chip, and described at least one first wire is electrically connected described at least one first conductive junction point of described first sense die and described chip.

3. encapsulating structure according to claim 1,

It separately comprises at least one second wire and at least one second conductive junction point, described at least one second conductive junction point is arranged at the described first surface of described chip, and described at least one second wire is electrically connected described at least one second conductive junction point of described substrate and described chip.

4. encapsulating structure according to claim 1,

It separately comprises at least one privates and at least one 3rd conductive junction point, described at least one 3rd conductive junction point is arranged at the described first surface of described chip, and described at least one privates is electrically connected described at least one 3rd conductive junction point of described second sense die and described chip.

5. encapsulating structure according to claim 4,

It separately comprises gel, coated described at least one privates and described at least one 3rd conductive junction point.

6. encapsulating structure according to claim 5,

Coated described second sense die of wherein said gel.

7. encapsulating structure according to claim 1,

It separately comprises confinement barrier, is arranged at around described second sense die.

8. encapsulating structure according to claim 1,

It separately comprises annular sidewall around the second sense die, and described annular sidewall is arranged at the described first surface of described chip.

9. a manufacturing process for micro electronmechanical sensing apparatus, it comprises the following steps:

A () provides substrate, described substrate has first surface;

B () arranges chip in the described first surface of described substrate, described chip has first surface;

C () arranges the first sense die on described chip or described substrate;

D () is electrically connected described chip and described substrate, and be electrically connected described chip and described first sense die;

E () injects sealing with the part first surface of the described first surface of coated described substrate, described chip and described first sense die, wherein said sealing forms breach;

F () stacking second sense die in the described first surface of described chip, and is arranged in described breach; And

G () is electrically connected described second sense die and described chip.

10. manufacturing process according to claim 9,

Wherein in step (d), utilize at least one first wire to be electrically connected at least one first conductive junction point of described first sense die and described chip, and utilize at least one second wire to be electrically connected at least one second conductive junction point of described substrate and described chip.

11. manufacturing process according to claim 9,

Wherein in step (e); mould and diaphragm and described substrate is utilized to form space; to inject described sealing in described space; described diaphragm is arranged at the lower surface of described mould; and the described lower surface of described mould comprises depressed area, to hold the described diaphragm of extruded part.

12. manufacturing process according to claim 9,

Wherein in step (g), at least one privates is utilized to be electrically connected at least one 3rd conductive junction point of described second sense die and described chip.

13. manufacturing process according to claim 12,

It separately comprises the step arranging gel, with the coated described at least one privates of gel and described at least one 3rd conductive junction point.

14. manufacturing process according to claim 9,

Wherein in step (e); mould and diaphragm and described substrate is utilized to form space; to inject described sealing in described space; described mould comprises main body, at least one outstanding post and at least one padded coaming; described main body separately has at least one hole with accommodating described at least one outstanding post; padded coaming is arranged at the bottom of outstanding post, the corresponding outstanding shape of described outstanding post in order to form described breach, the coated described main body of described diaphragm and described outstanding post.

15. manufacturing process according to claim 9,

Wherein in step (e), separately comprise the following steps:

(e1) arrange hollow box in the described first surface of described chip, described hollow box is inverted U-shaped, and it is opening down, the space of described hollow box definition hollow;

(e2) sealing is injected with the part first surface of the described first surface of coated described substrate, described chip, described first sense die and described hollow box; And

(e3) means of abrasion sealing and part hollow box, makes described hollow box become annular sidewall, in described annular sidewall, then forms described breach.