CN105293421A - Packaging structure and manufacturing process of micro electro mechanical system sensing device - Google Patents
Packaging structure and manufacturing process of micro electro mechanical system sensing device Download PDFInfo
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- CN105293421A CN105293421A CN201410240872.5A CN201410240872A CN105293421A CN 105293421 A CN105293421 A CN 105293421A CN 201410240872 A CN201410240872 A CN 201410240872A CN 105293421 A CN105293421 A CN 105293421A
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Abstract
The invention relates to a packaging structure and a manufacturing process of a micro electro mechanical system sensing device. The packaging structure comprises a substrate, a chip, a first sensing bare chip, a second sensing bare chip and a sealing compound. The chip is arranged on a first surface of the substrate. The first sensing bare chip is electrically connected with the chip. The second sensing bare chip is stacked on the first surface of the chip, and the second sensing bare chip is electrically connected with the chip. The sealing compound coats the first surface of the substrate, a part of the first surface of the chip and the first sensing bare chip, wherein the sealing compound forms a notch to expose the second sensing bare chip. The packaging structure can reduce the package size and improve the electrical characteristics.
Description
Technical field
The present invention relates to a kind of micro electronmechanical sensing apparatus encapsulating structure and manufacturing process.
Background technology
In conventional encapsulating structure, about the encapsulation of sensing module, usually utilize die sinking in advance (pre-mold) to design, according to customized design, on substrate, form sealing, then carry out follow-up encapsulation procedure.In general, the encapsulating structure of the conventional design of die sinking in advance, its package dimension is comparatively large, and cost is also higher.
Summary of the invention
This exposure relate in one aspect to a kind of micro electronmechanical sensing apparatus encapsulating structure.In one embodiment, described encapsulating structure comprises: substrate, chip, the first sense die, the second sense die and sealing.Described substrate has first surface.Described chip is arranged at the described first surface of described substrate, and described chip has first surface.Described first sense die and described chip are electrically connected.Described second sense die is stacked in the described first surface of described chip, and described second sense die and described chip are electrically connected.The described first surface of substrate described in sealant covers, the part first surface of described chip and described first sense die, wherein said sealing forms breach, to manifest described second sense die.
Described second sense die of described encapsulating structure is stacked in the described first surface of described chip, therefore can package dimension be reduced, and for having the overall sensing module of described encapsulating structure, the volume of its entirety also can be reduced further, integrated model is designed and can have larger elasticity.In addition, described first sense die and described second sense die are all directly electrically connected described chip, electrical path are shortened, to promote electrical characteristic.
The another aspect of this exposure relates to a kind of manufacturing process of micro electronmechanical sensing apparatus.In one embodiment, described manufacturing process comprises the following steps: (a) provides substrate, and described substrate has first surface; B () arranges chip in the described first surface of described substrate, described chip has first surface; C () arranges the first sense die on described chip or described substrate; D () is electrically connected described chip and described substrate, and be electrically connected described chip and described first sense die; E () injects sealing with the part first surface of the described first surface of coated described substrate, described chip and described first sense die, wherein said sealing forms breach; F () stacking second sense die in the described first surface of described chip, and is arranged in described breach; And (g) is electrically connected described second sense die and described chip.
Utilize manufacturing process of the present invention, routine die sinking in advance must do not utilized to design, need not die sinking in advance and customized relevant cost, therefore can reduce costs.
Accompanying drawing explanation
Fig. 1 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention;
Fig. 2 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention;
Fig. 3 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention;
Fig. 4 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention;
Fig. 5 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention;
Fig. 6 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention;
Fig. 7 A shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention;
Fig. 7 B shows the upper schematic diagram of the encapsulating structure of Fig. 7 A of the present invention;
Fig. 8 A to Fig. 8 G shows the schematic diagram of an embodiment of the manufacturing process of the encapsulating structure of Fig. 1 of the present invention;
Fig. 9 A to Fig. 9 C shows the schematic diagram of an embodiment of the manufacturing process of Fig. 7 A encapsulating structure of the present invention;
Figure 10 shows the schematic diagram of an embodiment of the mould of manufacturing process of the present invention;
Figure 11 A to Figure 11 C shows the schematic diagram of an embodiment of the manufacturing process of the present invention one encapsulating structure; And
Figure 12 A to Figure 12 D shows the schematic diagram of an embodiment of the manufacturing process of the present invention one encapsulating structure.
Detailed description of the invention
With reference to figure 1, show the cross-sectional schematic of an embodiment of encapsulating structure of the present invention.Described encapsulating structure 10 comprises: substrate 11, chip 12, first sense die 13, second sense die 14, sealing 15 and gel (gel) 19.
Described substrate 11 has first surface 111.Described substrate 11 can be BT material and covers brilliant substrate, glass substrate, ceramic substrate, Copper Foil substrate or lead frame (leadframe).
Described chip 12 is arranged at the described first surface 111 of described substrate 11, and be electrically connected with described substrate 11, described chip 12 has first surface 121, and described chip 12 is such as special IC (Application-SpecificIntegratedCircuit, ASIC).In one embodiment, at least one second conductive junction point 123 of described chip 12 is electrically connected at described substrate 11 by least one second wire 17, and described at least one second conductive junction point 123 is arranged at the described first surface 121 of described chip 12.
Described first sense die 13 is arranged at the described first surface 111 of described substrate 11, and described first sense die 13 is electrically connected with described chip 12.Described first sense die 13 is arranged on the described first surface 111 of described substrate 11 by adhesive-layer (adhesivelayer does not illustrate).In one embodiment, utilize at least one first wire 16 to be electrically connected at least one first conductive junction point 122 of described first sense die 13 and described chip 12, described at least one first conductive junction point 122 is arranged at the described first surface 121 of described chip 12.That is, described first sense die 13 is directly electrically connected, not again via elements such as other nude films with described chip 12.Further, utilize the first lid 21, be covered on described first sense die 13 of part, to protect described first sense die 13.The material of described first lid 21 can be silicon (Si).
Described second sense die 14 is stacked in the described first surface 121 of described chip 12, and described second sense die 14 is electrically connected with described chip 12.In one embodiment, utilize at least one privates 18 to be electrically connected at least one 3rd conductive junction point 124 of described second sense die 14 and described chip 12, described at least one 3rd conductive junction point 124 is arranged at the described first surface 121 of described chip 12.That is, described second sense die 14 is directly electrically connected, not again via elements such as other nude films with described chip 12.
The coated described first surface 111 of described substrate 11 of described sealing 15, the part first surface 121 of described chip 12 and described first sense die 13, wherein said sealing 15 forms breach 151, to manifest a part for the described first surface 121 of described chip 12 and described second sense die 14.
Described at least one 3rd conductive junction point 124 of the coated described at least one privates 18 of described gel 19 and described chip 12, so can avoid the electric connection of described chip 12 and described second sensor 14 undermined because being revealed in the described breach 151 of described sealing 15.In addition, due to described gel 15 only chip 12 described in covered section, but not complete coated described chip 12, therefore effectively can reduce cost.The material of described gel 19 such as can be epoxy resin (epoxy) or Silica hydrogel (siliconegel).
In one embodiment, described encapsulating structure 10 can be applicable to the tire pressure monitoring system (TierPressureMonitoringSystem of vehicle, TPMS), described first sense die 13 can be acceleration transducer (Accelerometersensor), and described second sense die 14 can be pressure sensor (Pressuresensor).Described second sense die 14, in order to sense the pressure of tire, is not therefore packaged in sealing 15.Whether described first sense die 13 moves in order to senses vehicle, and decide by described chip 12 pressure whether described second sense die 14 carries out sensing tire, if vehicle take-offs, the pressure of described second sense die 14 side sensing tire, to save power supply.
Described second sense die 14 of described encapsulating structure 10 is stacked in the described first surface 121 of described chip 12, therefore can package dimension be reduced, and for having the overall sensing module of described encapsulating structure 10, also can reduce its overall volume further, integrated model be designed and can have larger elasticity.In addition, described first sense die 13 and described second sense die 14 are all directly electrically connected described chip 12, electrical path are shortened, to promote electrical characteristic.
Fig. 2 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention.Compared to the encapsulating structure 10 of Fig. 1, element identical in the embodiment of fig. 2 gives similar elements numbering.Encapsulating structure 20 of the present invention comprises: substrate 11, chip 12, first sense die 13, second sense die 14, sealing 15, gel 19 and covering 22.
Described covering 22 is covered in described sealing 15 and above described second sense die 14, to protect described second sense die 14 further.Described covering 22 has hole (hole) can detect external environment to make described second sense die 14 being placed in described breach 151, such as: air pressure, temperature or humidity etc.
Fig. 3 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention.Compared to the encapsulating structure 10 of Fig. 1, element identical in the embodiments of figure 3 gives similar elements numbering.Encapsulating structure 30 of the present invention comprises: substrate 11, chip 12, first sense die 13, second sense die 14, sealing 15 and gel 31.
Described gel 31 fills up described breach 151 haply, with complete coated described second sense die 14 and described privates 18.The upper surface of described gel 31 roughly with the upper surface flush of described sealing 15, in another embodiment, the upper surface of described viscose glue 31 can lower than the upper surface with described sealing 15.
Because the characteristic of gel 31 is different from the characteristic of sealing 15, its hardness is little compared with the hardness of sealing, such as Silica hydrogel (siliconegel), therefore can coated described second sense die 14 and privates 18, to avoid the electric connection of described chip 12 and described second sensor 14 undermined because being revealed in the described breach 151 of described sealing 15, and do not affect the described sensed characteristic of the second sense die 14 and the electric connection of privates 18.
Fig. 4 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention.Compared to the encapsulating structure 10 of Fig. 1, element identical in the fig. 4 embodiment gives similar elements numbering.Encapsulating structure 40 of the present invention comprises: substrate 11, chip 12, first sense die 13, second sense die 42, sealing 15, second lid 41 and gel 43.
Described second lid 41 is covered on described second sense die 42 of part, to protect described second sense die 42 further.And; the coated described at least one privates 18 of gel 43 and described at least one 3rd conductive junction point 124; to protect the electric connection of described privates 18 and described at least one 3rd conductive junction point 124, and the height of gel 43 is about suitable with the height of described second lid 41.
Fig. 5 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention.Compared to the encapsulating structure 10 of Fig. 1, element identical in the 5 embodiment of figure 5 gives similar elements numbering.Encapsulating structure 50 of the present invention comprises: substrate 11, chip 52, first sense die 53, second sense die 14, sealing 15 and gel 19.
Described first sense die 53 and described second sense die 14 of encapsulating structure 50 of the present invention are all arranged at the described first surface 521 of described chip 52, and described first sense die 53 is directly electrically connected with described chip 52 by described first wire 16, described second sense die 14 is directly electrically connected with described chip 52 by described privates 18.
Fig. 6 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention.Compared to the encapsulating structure 10 of Fig. 1, element identical in the embodiment in fig 6 gives similar elements numbering.Encapsulating structure 60 of the present invention comprises: substrate 61, chip 12, first sense die 63, second sense die 14, sealing 15 and gel 19.
First sense die 63 of encapsulating structure 60 of the present invention is arranged at the described first surface 611 of substrate 61, and the first sense die 63 is electrically connected with described substrate 61, as shown in Figure 6, first sense die 63 is electrically connected with substrate 61 through the first wire 16, therefore the sensing signal of the first sense die 63 can be sent to chip 12 via substrate 61 and the second wire 17, therefore, the described substrate 61 of the present embodiment is preferably RF magnetron sputtering or ceramic substrate.
Fig. 7 A shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention, and Fig. 7 B shows the upper schematic diagram of the encapsulating structure of Fig. 7 A of the present invention, and wherein Fig. 7 B does not comprise sealing 15 and the gel 19 of Fig. 7 A.Coordinate with reference to figure 7A and Fig. 7 B, compared to the encapsulating structure 10 of Fig. 1, element identical in the embodiment of Fig. 7 A and 7B gives similar elements numbering.Encapsulating structure 70 of the present invention comprises substrate 11, chip 12, first sense die 13, second sense die 14, sealing 15, gel 19 and confinement barrier 71.
Described confinement barrier 71 is arranged at the described first surface 121 of described chip 12, and be arranged at described second sense die 14 and described at least one 3rd conductive junction point 124 around, namely be arranged between the second conductive junction point 123 and the 3rd conductive junction point 124, and between the second sense die 14 and the first conductive junction point 122.Described confinement barrier (Dam) 71 can be annular or square etc., and material can be epoxy resin (epoxy).Utilize described confinement barrier 71, can prevent sealing 15 from overflowing glue to described at least one 3rd conductive junction point 124, to protect the electric connection between the second sense die 14 and chip 12.
Fig. 8 A to Fig. 8 G shows the schematic diagram of an embodiment of the manufacturing process of the encapsulating structure of Fig. 1 of the present invention.
With reference to figure 8A, provide substrate 11, described substrate 11 has first surface 111.Then, arrange chip 12 in the described first surface 111 of described substrate 11, described chip 12 has first surface 121, first conductive junction point 122, second conductive junction point 123 and at least one 3rd conductive junction point 124.
With reference to figure 8B, the first sense die 13 is set in the described first surface 111 of described substrate 11, then the first lid 21 is set to be covered on described first sense die 13 of part, protect described first sense die 13.
With reference to figure 8C, be electrically connected described chip 12 and described substrate 11, and be electrically connected described chip 12 and described first sense die 13.In one embodiment, utilize at least one first wire 16 to be electrically connected at least one first conductive junction point 122 of described first sense die 13 and described chip 12, and utilize at least one second wire 17 to be electrically connected at least one second conductive junction point 123 of described substrate 11 and described chip 12.Chip.
With reference to figure 8D, utilize mould 26 and diaphragm (film) 27 to be arranged at the first surface 121 of described chip 12, and form space 28 with described substrate 11.Described mould 26 has corresponding outstanding shape, and the described lower surface 261 of described mould 26 comprises depressed area 262.Described diaphragm 27 is arranged at the lower surface 261 of described mould 26, with the first surface 121 avoiding mould 26 to damage described chip 12.
With reference to figure 8E; inject sealing 15 in described space 28; with the coated described first surface 111 of described substrate 11, the part first surface 121 of described chip 12 and described first sense die 13; because mould 26 and diaphragm 27 are arranged at the first surface 121 of described chip 12; because of the corresponding outstanding shape of described mould 26, described sealing 15 forms breach 151 to appear the described first surface 121 of described chip 12.Carrying out baking to sealing 15 makes it be cross-linked.Because mould 26 has depressed area 262; to hold the described diaphragm 27 of extruded part; described diaphragm 27 part can not be given prominence to because being squeezed; cause described diaphragm 27 smoothly cannot be attached to the described first surface 121 of described chip 12, with guarantee sealing 15 can not overflow glue to described diaphragm 27 times and described chip 12 first surface 121 between.And described diaphragm 27 also can cover at least one 3rd conductive junction point 124, make sealing 15 can not coated at least one 3rd conductive junction point 124.
With reference to figure 8F, stacking second sense die 14 in the described first surface 121 of described chip 12, and is arranged in described breach 151.
With reference to figure 8G, be electrically connected described second sense die 14 and described chip 12.In one embodiment, at least one privates electrical 18 is utilized to connect at least one 3rd conductive junction point 124 of described second sense die 14 and described chip 12.
Manufacturing process of the present invention separately comprises the step arranging gel 19, with the coated described at least one privates 18 of gel 19 and described at least one 3rd conductive junction point 124, as shown in Figure 1.
Utilize manufacturing process of the present invention, must not utilize routine open molding techniques in advance, need not die sinking in advance and customized relevant cost, therefore can reduce costs.Further, because the hardening temperature of gel 19 is low compared with the hardening temperature of sealing 15, first inject sealing 15 and gel 19 and sclerosis are set after sclerosis again, the reliability of encapsulating structure product can be improved.
Fig. 9 A to Fig. 9 C shows the schematic diagram of an embodiment of the manufacturing process of Fig. 7 A encapsulating structure of the present invention, please coordinate with reference to figure 8A to Fig. 8 B, in one embodiment, substrate 11 being provided, chip 12 is set and the step of the first sense die 13 is set in the encapsulating structure 70 of construction drawing 7A, identical with the step of Fig. 8 A to Fig. 8 B, no longer describe.
With reference to figure 9A, confinement barrier 71 is set on the described first surface 121 of chip 12, and around described at least one 3rd conductive junction point 124 outside.Then, utilize at least one first wire 16 to be electrically connected at least one first conductive junction point 122 of described first sense die 13 and described chip 12, and utilize at least one second wire 17 to be electrically connected at least one second conductive junction point 123 of described substrate 11 and described chip 12.
With reference to figure 9B, utilize mould 76 to be arranged on described confinement barrier 71, and support described confinement barrier 71.Mould 76 and described substrate 11 form space 77, and described confinement barrier 71 supported by mould 76.
With reference to figure 9C, inject described sealing 15 in described space 77, because described confinement barrier 71 supported by mould 76, sealing 15 can not overflow glue between the lower surface 761 of described mould 76 and the first surface 121 of described chip 12, therefore sealing 15 can not coated at least one 3rd conductive junction point 124 and affect the electric connection of chip 12.Compared to Fig. 8 D, because arranging described confinement barrier 71, therefore do not need the described diaphragm 27 of Fig. 8 D.
Please coordinate with reference to figure 8F to Fig. 8 G, in one embodiment, the step that the second sense die 14 and electric connection second sense die 14 and chip 12 are set of the encapsulating structure 70 of follow-up construction drawing 7, identical with the step of Fig. 8 F to Fig. 8 G, no longer describe.
Figure 10 shows the schematic diagram of an embodiment of the mould 36 of manufacturing process of the present invention, and described mould 36 has main body 361, at least one outstanding post 362 and at least one padded coaming 363.Described main body 361 separately has at least one hole 364 with accommodating at least one outstanding post 362, and padded coaming 363 is arranged at the bottom of outstanding post 362.Padded coaming 363 can be the corresponding outstanding shape of the described outstanding post 362 of O shape ring (O-ring) in order to form the breach 151 as Fig. 1.The coated described main body 361 of diaphragm 37 and described outstanding post 362.
Because described outstanding post 362 is not one-body molded with described main body 361, it is device movable up and down, and padded coaming 363 is arranged at the bottom of outstanding post 362, and described padded coaming 363 has thermal resistance and elasticity, namely when chip 12 has difference in height, mobilizable outstanding post 362 and there is flexible padded coaming 363 can the difference in height of compensation chips 12, chip 12 is caused to produce the situation of crack (crack), to improve product yield when avoiding described outstanding post 362 to compress chip 12.
Figure 11 A to Figure 11 C shows the schematic diagram of an embodiment of the manufacturing process of the present invention one encapsulating structure, please coordinate with reference to figure 8A to Fig. 8 B, in one embodiment, make substrate 11 being provided, chip 12 is set and the step of the first sense die 13 is set in described encapsulating structure, identical with the step of Fig. 8 A to Fig. 8 B, no longer describe.
With reference to figure 11A, hollow box 101 is set in the described first surface 121 of described chip 12.Described hollow box 101 is in inverted U-shaped, and it is opening down, and is arranged at outside around described at least one 3rd conductive junction point 124.
Described hollow box 101 defines the space of hollow, and the material of described hollow box can be the materials such as metal, resinifying agent or carbide.
With reference to figure 11B, inject sealing 25 with the part first surface 121 of the described first surface 111 of coated described substrate 11, described chip 12, described first sense die 13 and described hollow box 101.Because described hollow box 101 defines the space of described hollow, make sealing 15 can not flow to the described first surface 121 of part in the described hollow box 101 of described chip 12.And because described at least one 3rd conductive junction point 124 is in described hollow box 101, make sealing 15 can not coated described at least one 3rd conductive junction point 124.Compared to Fig. 8 D and Fig. 9 B, because arranging described hollow box 101, therefore not needing mould 26 and the diaphragm 27 of the corresponding outstanding shape of Fig. 8 D, not needing the confinement barrier 71 of Fig. 9 B yet.In addition, (do not illustrate) in other embodiment, described hollow box 101 also can be arranged on described substrate or any formation one space that needs is to hold sense die part, produces corresponding space to hold sense die comparatively elasticity compared to use special die.
With reference to figure 11C, means of abrasion sealing 25 and part hollow box 101, make described hollow box 101 become annular sidewall 102.Breach 251 is then formed in described annular sidewall 102.
Please coordinate with reference to figure 8F to Fig. 8 G, in one embodiment, the follow-up step second sense die 14 being set in described breach 251 and being electrically connected the second sense die 14 and chip 12, namely annular sidewall 102 is around the second sense die 14, this step is identical with the step of Fig. 8 F to Fig. 8 G, no longer describes.
Figure 12 A to Figure 12 D shows the schematic diagram of an embodiment of the manufacturing process of the present invention one encapsulating structure, please coordinate with reference to figure 8A to Fig. 8 B, in one embodiment, make substrate 11 being provided, chip 12 is set and the step of the first sense die 13 is set in described encapsulating structure, identical with the step of Fig. 8 A to Fig. 8 B, no longer describe.
With reference to figure 12A, stacking second sense die 14 is in the described first surface 121 of described chip 12.Then, described second sense die 14 and described chip 12 is electrically connected.In one embodiment, at least one privates electrical 18 is utilized to connect at least one 3rd conductive junction point 124 of described second sense die 14 and described chip 12.
With reference to figure 12B, hollow box 103 is set in the described first surface 121 of described chip 12.Described hollow box 103 is in inverted U-shaped, and it is opening down, and is arranged at outside around described second sense die 14 and described at least one 3rd conductive junction point 124.That is, described hollow box 103 covers in outside described second sense die 14 and described at least one 3rd conductive junction point 124.Described hollow box 103 defines the space of hollow, and described second sense die 14 and described at least one 3rd conductive junction point 124 are in the space of described hollow.
With reference to figure 12C, inject sealing 45 with the part first surface 121 of the described first surface 111 of coated described substrate 11, described chip 12, described first sense die 13 and described hollow box 103.Because described hollow box 103 defines the space of described hollow, make sealing 15 can not flow to the described first surface 121 of part in the described hollow box 103 of described chip 12.And because described second sense die 14 and described at least one 3rd conductive junction point 124 are in described hollow box 103, make sealing 45 can not coated described second sense die 14 and described at least one 3rd conductive junction point 124.
With reference to figure 12D, means of abrasion sealing 45 and part hollow box 103, make described hollow box 103 become annular sidewall 104.Breach 451 is then formed in described annular sidewall 104.Described second sense die 14 and described at least one 3rd conductive junction point 124 are in described breach 451.
Above-described embodiment is only and principle of the present invention and effect thereof is described, and is not used to limit the present invention.Therefore, those skilled in the art modifies to above-described embodiment and changes still not de-spirit of the present invention.Interest field of the present invention should listed by claims described later.
Claims (15)
1. an encapsulating structure, it comprises:
Substrate, it has first surface;
Chip, it is arranged at the described first surface of described substrate, and described chip has first surface;
First sense die, itself and described chip are electrically connected;
Second sense die, it is stacked in the described first surface of described chip, and described second sense die and described chip are electrically connected; And
Sealing, the described first surface of its coated described substrate, the part first surface of described chip and described first sense die, wherein said sealing forms breach, to manifest described second sense die.
2. encapsulating structure according to claim 1,
It separately comprises at least one first wire and at least one first conductive junction point, described at least one first conductive junction point is arranged at the described first surface of described chip, and described at least one first wire is electrically connected described at least one first conductive junction point of described first sense die and described chip.
3. encapsulating structure according to claim 1,
It separately comprises at least one second wire and at least one second conductive junction point, described at least one second conductive junction point is arranged at the described first surface of described chip, and described at least one second wire is electrically connected described at least one second conductive junction point of described substrate and described chip.
4. encapsulating structure according to claim 1,
It separately comprises at least one privates and at least one 3rd conductive junction point, described at least one 3rd conductive junction point is arranged at the described first surface of described chip, and described at least one privates is electrically connected described at least one 3rd conductive junction point of described second sense die and described chip.
5. encapsulating structure according to claim 4,
It separately comprises gel, coated described at least one privates and described at least one 3rd conductive junction point.
6. encapsulating structure according to claim 5,
Coated described second sense die of wherein said gel.
7. encapsulating structure according to claim 1,
It separately comprises confinement barrier, is arranged at around described second sense die.
8. encapsulating structure according to claim 1,
It separately comprises annular sidewall around the second sense die, and described annular sidewall is arranged at the described first surface of described chip.
9. a manufacturing process for micro electronmechanical sensing apparatus, it comprises the following steps:
A () provides substrate, described substrate has first surface;
B () arranges chip in the described first surface of described substrate, described chip has first surface;
C () arranges the first sense die on described chip or described substrate;
D () is electrically connected described chip and described substrate, and be electrically connected described chip and described first sense die;
E () injects sealing with the part first surface of the described first surface of coated described substrate, described chip and described first sense die, wherein said sealing forms breach;
F () stacking second sense die in the described first surface of described chip, and is arranged in described breach; And
G () is electrically connected described second sense die and described chip.
10. manufacturing process according to claim 9,
Wherein in step (d), utilize at least one first wire to be electrically connected at least one first conductive junction point of described first sense die and described chip, and utilize at least one second wire to be electrically connected at least one second conductive junction point of described substrate and described chip.
11. manufacturing process according to claim 9,
Wherein in step (e); mould and diaphragm and described substrate is utilized to form space; to inject described sealing in described space; described diaphragm is arranged at the lower surface of described mould; and the described lower surface of described mould comprises depressed area, to hold the described diaphragm of extruded part.
12. manufacturing process according to claim 9,
Wherein in step (g), at least one privates is utilized to be electrically connected at least one 3rd conductive junction point of described second sense die and described chip.
13. manufacturing process according to claim 12,
It separately comprises the step arranging gel, with the coated described at least one privates of gel and described at least one 3rd conductive junction point.
14. manufacturing process according to claim 9,
Wherein in step (e); mould and diaphragm and described substrate is utilized to form space; to inject described sealing in described space; described mould comprises main body, at least one outstanding post and at least one padded coaming; described main body separately has at least one hole with accommodating described at least one outstanding post; padded coaming is arranged at the bottom of outstanding post, the corresponding outstanding shape of described outstanding post in order to form described breach, the coated described main body of described diaphragm and described outstanding post.
15. manufacturing process according to claim 9,
Wherein in step (e), separately comprise the following steps:
(e1) arrange hollow box in the described first surface of described chip, described hollow box is inverted U-shaped, and it is opening down, the space of described hollow box definition hollow;
(e2) sealing is injected with the part first surface of the described first surface of coated described substrate, described chip, described first sense die and described hollow box; And
(e3) means of abrasion sealing and part hollow box, makes described hollow box become annular sidewall, in described annular sidewall, then forms described breach.
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| CN201410240872.5A CN105293421A (en) | 2014-05-30 | 2014-05-30 | Packaging structure and manufacturing process of micro electro mechanical system sensing device |
| CN201810105495.2A CN108689382A (en) | 2014-05-30 | 2014-05-30 | Micro electronmechanical sensing device further encapsulating structure and manufacturing process |
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| CN112014027A (en) * | 2019-05-28 | 2020-12-01 | 合肥杰发科技有限公司 | Multi-device packaging structure and manufacturing method thereof |
| CN112014026A (en) * | 2019-05-28 | 2020-12-01 | 合肥杰发科技有限公司 | Pressure sensor and manufacturing method thereof |
| CN112014000A (en) * | 2019-05-28 | 2020-12-01 | 合肥杰发科技有限公司 | Multi-device packaging structure and manufacturing method thereof |
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