CN105264609A

CN105264609A - Data storage control method and apparatus

Info

Publication number: CN105264609A
Application number: CN201380002801.5A
Authority: CN
Inventors: 潘顺成; 徐君
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2013-12-03
Filing date: 2013-12-03
Publication date: 2016-01-20
Anticipated expiration: 2033-12-03
Also published as: CN105264609B; WO2015081488A1

Abstract

A data storage control method and apparatus. The implementation of the method comprises: monitoring whether a read-write operation is performed on banks of a phase change memory; pre-filling 1 for a cell (CELL) in a bank on which a read-write operation is not performed, the phase change memory being provided with two more banks; and when it is required to write data into the phase change memory, if a target address segment at which data is to be written is pre-filled with 1 and a current value of a target CELL in the target address segment is different from the data to be written, modifying the target CELL into 0. When read-write operations are performed on some banks of a phase change memory, a controller can perform a Preset operation on a bank on which a read-write operation is not performed, and a Preset command only needs an address bus and a control bus and does not need a data bus, and therefore, the read-write operation can fully concur with a read-write operation of another bank, so that the read-write concurrency speed can be increased, the delay of a normal read-write operation can be reduced, and the read-write performance of a PCM system can be improved.

Description

Data storage control method and apparatus

A kind of data storage control method, and device

Technical field

It is related to a kind of data storage control method, and device the present invention relates to technical field of data storage , Te Do.Background technology

Storage medium, PCM (phase change memory, phase transition storage）Just as follow-on nonvolatile storage（None Violate memory) start popularization, DRAM (Dynamic Random Access Memory, dynamic random access memory) and NAND Flash (flash memories will be substituted）, the memory mechanism as a new generation.PCM is using chalcogenide in the huge conductivity difference of crystalline state and amorphous state come data storage.

Chalcogenide is presently mainly GST (Glutathione S-transferase, glutathione sulfydryl transferase）Material, GST materials have higher resistivity under amorphous state.Because this state typically occurs in RESET (resets）After operation, we are typically called RESET state, the CELL (units in RESET operation）Temperature rise to slightly above melting temperature, then suddenly to GST quenching be cooled to.The speed of cooling is most important for the formation of amorphous layer.

Under crystalline state, GST materials have relatively low resistivity.Because this state typically occurs in SET (set）After operation, we are typically called SET state, in SET operation, and the temperature of material rises above crystallization temperature and but is below melting temperature, and then Slow slow cool downs cause crystal grain formation flood.

During actual PCM write operations, usually control electric current writes 1 (SET), writes 0 to realize

( RESET ).From the above, it can be seen that PCM in SET operation, it is necessary to Slow slow cool downs, it is therefore desirable to the low current of long period；And RESET operation, then need the high current of short time.Therefore, because itself the characteristics of, write Cha Do Jian 0/RESET and the Shi for writing 1/SET larger：It is write the 0/RESET times 2 ~ 5 times typically to write the 1/SET times.

The implementation process for writing 1/SET operations is as follows：Due to each CELL (units of PCM）Individual difference, the parameter such as required size of current has differences.The present 1/SET that writes is operated, usually iterative.First trial carries out SET operation with smaller current, and then whether retaking of a year or grade resistance value meets preset value.Electric current is gradually increased if not meeting, until retaking of a year or grade resistance value meets preset value.

At present, the method for lifting PCM writing rates, can be as follows：Write in advance before formal write operation 0/RESET, formal write operation only needs to write 1/SET, shortens the formal write operation time.The program is specific as follows：When PCM is idle, pre-filled 1, when then writing data again, it is only necessary to enter row write 0 to data 0 and operate is carried out to PCM blocks, it is to avoid time-consuming writes 1 operation, can lift writing speed.I.e.：For a region, pre-filled 1 (PRESET) first is carried out to the region chosen, then according to the data to be write, it would be desirable to which the bit for writing 0 (RESET) enters row write 0 (RESET).

Above scheme, pre-filled to the progress of the PCM pages to be carried out when PCM is idle, when carrying out pre-filled, if read/write requests, the read/write requests response time will be longer, therefore PCM system write performances are still relatively low.The content of the invention

The embodiments of the invention provide a kind of data storage control method, and device, for lifting read/write concurrency, the delay of normal write operation is reduced, PCM system write performance is lifted.

On the one hand the embodiment of the present invention provides a kind of data storage control method, including：

Whether each memory heap bank in monitoring phase transition storage has read-write operation, to the unit CELL pre-filled 1 in the memory heap bank without read-write operation;The phase transition storage has two or more memory heap bank;

When needing to write data in the phase transition storage, if desired the destination address section pre-filled 1 of the data write, and the target CELL currencys in the destination address section need write-in data different from described, then it is 0 to change the target CELL.

With reference to the implementation of one side, in the first possible implementation, methods described, in addition to：If the destination address section of the data for needing to write pre-filled 1, and it is 1 to be currently needed for the data of write-in, then disconnects write operation loop, skip unit CELL filling.

With reference to the implementation of one side, in second of possible implementation, the unit CELL pre-filled 1 in the described couple of memory heap bank without read-write operation includes：

The former data of the unit CELL in the memory heap bank without read-write operation are read first, if former data are 1, write operation loop are disconnected, if former data are 0, write 1.

With reference to the first possible implementation of one side, in the third possible implementation, also include during the unit CELL pre-filled 1 in the memory heap bank without read-write operation：

If monitoring, the pre-filled 1 memory heap bank of carrying out in the phase transition storage has read-write operation, suspends pre-filled 1 operation to the memory heap bank, until the reading of the memory heap bank Write operation terminates.

With reference to the implementation of one side, one side the first, second or the third possible implementation, in the 4th kind of possible implementation, if monitoring, two or more memory heap bank do not have the unit CELL pre-filled 1 in read-write operation, the described couple of memory heap bank without read-write operation to include：

By queue length priority principle, there is no the unit CELL pre-filled 1 in the longer memory heap bank of read-write operation queue length to described two or more than two memory heap bank.

The aspect of the embodiment of the present invention two provides a kind of data recording control apparatus, including：

Whether monitoring unit, each memory heap bank for monitoring in phase transition storage has read-write operation；The phase transition storage has two or more memory heap bank;

Fills unit, for the unit CELL pre-filled 1 in the memory heap bank without read-write operation that is monitored to the monitoring unit;

Write control unit, for when needing to write data in the phase transition storage, if desired the destination address section of the data write is by the fills unit pre-filled 1, and the target CELL currencys in the destination address section need write-in data different from described, then it is 0 to change the target CELL.

With reference to the implementation of two aspects, in the first possible implementation, it is described to write control unit, if being additionally operable to the destination address section pre-filled 1 of the data for needing to write, and it is 1 to be currently needed for the data of write-in, write operation loop is then disconnected, unit CELL filling is skipped.

With reference to the implementation of two aspects, in second of possible implementation, the fills unit, former data for reading the unit CELL in the memory heap bank without read-write operation that the monitoring unit is monitored first, if former data are 1, write operation loop is then disconnected, if former data are 0,1 is write.

With reference to the implementation of two aspects, in the third possible implementation, the fills unit, it is additionally operable to during the fills unit is to the unit CELL pre-filled 1 in the memory heap bank without read-write operation, if the monitoring unit monitors that the pre-filled 1 memory heap bank of carrying out in the phase transition storage has read-write operation, then suspend pre-filled 1 operation to the memory heap bank, until the read-write operation of the memory heap bank terminates.

With reference to the implementation of two aspects, two aspect the first, second or the third possible implementation, in the 4th kind of possible implementation, the fills unit, if monitoring that two or more memory heap bank do not have read-write operation for the monitoring unit, queue length priority principle is then pressed, to institute Stating two or more memory heap bank does not have unit CELL pre-filled 1 in the longer memory heap bank of read-write operation queue length.

The aspect of the embodiment of the present invention three provides a kind of phase transition storage, including：Two or more are using the memory heap bank of phase change memory medium, bit line selecting switch, detection amplifier, write driver；The detection amplifier is connected with bit line selecting switch, and the write driver is connected with bit line selecting switch, the control circuit；

The control circuit is connected with the bit line selecting switch, the detection amplifier and the write driver；

Detect that amplifier and the write driver determine whether each memory heap bank has read-write operation described in the control circuit monitoring, and send enabled instruction to bit line selecting switch, indicating that the bit line selecting switch is chosen needs pre-filled unit CELL in the memory heap bank without read-write operation, unit CELL write-in 1 of the write driver to choosing, implements pre-filled；The write driver is after write operation instruction is received, and the target CELL currencys that the destination address section if desired write is had been filled with 1, and destination address section need write-in data different from described, then it is 0 to change the target CELL.

With reference to the implementation of one side, in the first possible implementation, it is described to send enabled instruction to bit line selecting switch, indicating that the bit line selecting switch is chosen needs pre-filled unit CELL in the memory heap bank without read-write operation, the write driver to choose unit CELL write-in 1, implement it is pre-filled including：

The control circuit reads the former data of the unit CELL in the memory heap bank without read-write operation by the detection amplifier, if former data are 1, then control disconnects write operation loop, if former data are 0, the control circuit indicates that write driver needs pre-filled unit CELL write-ins 1 to described.

With reference to the implementation of one side, the possible implementation of the first of one side, in second of possible implementation, the control circuit is additionally operable to read the data for needing to write, and determine whether current data is 1, if 1 does not then send write instruction to the write driver, that skips unit CELL writes 1 operation, if 0, write instruction then is sent to the write driver, it is 0 the write driver is changed the target CELL.

As can be seen from the above technical solutions, the embodiment of the present invention has advantages below：When PCM some memory heaps（When bank) having read-write operation, controller can be to the memory heap without read-write operation（bank ) Preset operations are carried out, Preset orders only need to address bus and controlling bus, it is not necessary to data/address bus, therefore can accomplish and other memory heaps（Bank) read-write operation is completely concurrent.So as to lift read-write concurrency, the delay of normal write operation is reduced, PCM system write performance is lifted.Brief description of the drawings

Technical scheme in order to illustrate the embodiments of the present invention more clearly, the accompanying drawing used required in being described below to embodiment, which makees cylinder, to be introduced, apparently, drawings in the following description are only some embodiments of the present invention, for one of ordinary skill in the art, without having to pay creative labor, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is present invention method schematic flow sheet；

Fig. 2 is apparatus structure schematic diagram of the embodiment of the present invention；

Fig. 3 is phase change memory structure schematic diagram of the embodiment of the present invention；

Fig. 4 is PCM structural representations of the embodiment of the present invention；

Fig. 5 is the pre-filled control circuit structural representation of the embodiment of the present invention；

Fig. 6 is present invention method schematic flow sheet；

Fig. 7 is present invention method schematic flow sheet；

Fig. 8 is the pre-filled control circuit structural representation of the embodiment of the present invention；

Fig. 9 is terminal structure schematic diagram of the embodiment of the present invention.Embodiment

In order that the object, technical solutions and advantages of the present invention are clearer, below in conjunction with accompanying drawing, the present invention is described in further detail, it is clear that described embodiment is only embodiment of the invention a part of, rather than whole embodiments.Based on the embodiment in the present invention, all other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made belongs to the scope of protection of the invention.

The embodiments of the invention provide a kind of data storage control method, as shown in figure 1, including：

101 :Monitor each memory heap in phase transition storage（Bank) whether there is read-write operation；Above-mentioned phase transition storage has two or more memory heaps（bank );

102:To the memory heap without read-write operation（Bank the unit in)（CELL) pre-filled 1;In step 102, pre-filled 1 scheme can be to the above-mentioned memory heap without read-write operation (bank) all CELL are carried out pre-fill 1 and operated, i.e. write-in 1 is operated, the CELL that former data can also be selected to be 0 is revised as 1, the CELL that former data are 1 is without processing, the operation to CELL can so be reduced, it is specific as follows so as to save power consumption and extend CELL life-span：It is above-mentioned to the memory heap without read-write operation（Bank the unit CELL pre-filled 1 in) includes：The above-mentioned memory heap without read-write operation is read first（Bank the former data of the unit CELL in), if former data are 1, disconnect write operation loop, if former data are 0, write 1.

In the implementation procedure of above-mentioned steps 102, it is possible to occur to above-mentioned memory heap（Bank read-write operation), so needs to suspend pre-filled operation, it is to avoid read-write operation postpones, and the embodiments of the invention provide specific solution is as follows：To the memory heap without read-write operation（Bank also include during the unit CELL pre-filled 1 in)：

If monitoring the memory heap for carrying out pre-filled 1 in above-mentioned phase transition storage（Bank) there is read-write operation, then suspend to above-mentioned memory heap（Bank pre-filled 1 operation), until above-mentioned memory heap（Bank read-write operation) terminates.

In addition, multiple memory heaps may be monitored in a step 101（Bank) without read-write operation, memory heap can be arbitrarily selected in this case（Bank pre-filled operation) is carried out, following manner can also be preferably used and carry out pre-filled operation：If monitoring two or more memory heaps（Bank it is above-mentioned to the memory heap without read-write operation) without read-write operation（Bank the unit CELL pre-filled 1 in) includes：By queue length priority principle, to above-mentioned two or more than two memory heaps（Bank) without the longer memory heap of read-write operation queue length（Bank the unit CELL pre-filled 1 in).

103:When needing to write data in above-mentioned phase transition storage, if desired the destination address section pre-filled 1 of the data write, and the target CELL currencys in above-mentioned destination address section need write-in data different from above-mentioned, then it is 0 to change above-mentioned target CELL.

The embodiment of the present invention, when PCM some memory heaps（When bank) having read-write operation, controller can be to the memory heap without read-write operation（Bank Preset operations) are carried out, Preset orders only need to address bus and controlling bus, it is not necessary to data/address bus, therefore can accomplish and other memory heaps（Bank) read-write operation is completely concurrent.So as to lift read-write concurrency, the delay of normal write operation, lifting are reduced

PCM system write performance.

It is understood that in step 103, if the data that write target CELL are 1, write operation may not necessarily be performed, the embodiments of the invention provide specific implementation in this case is as follows： Further, if in step 103, the above method, in addition to：If the destination address section of the data of above-mentioned needs write-in pre-filled 1, and it is 1 to be currently needed for the data of write-in, then disconnects write operation loop, skip unit CELL filling.

In the embodiment above, the institutional framework of PCM storage mediums, can be based on row (OK）Two-stage skew is offset between bias internal and row and is used as bank (heap of bar shaped, i.e. memory heap（Bank equalization problem)) is write solve PCM, while eliminating the associated overhead such as mapping table and its inquiry.

Based on preceding description, in embodiments of the present invention, PCM memory cell is a two-dimentional matrix structure, is divided according to row and column (row), and each column includes multiple memory cell again（Each CELL storages lbit).Present invention incorporates RAM (Random Access Memory, random access memory）The institutional framework of chip, proposes the bank (heaps of bar shaped）Between concurrent operations scheme, improve system write operation speed.RAM-as there is multiple bank (such as current DDR3 (Double Data Rate 3, octuple rate DRAM）Chip typically has 8 bank), with hoist capacity and property an ancient type of spoon.

In embodiments of the present invention, in PCM sides, special PRESET control circuits can be provided.When some bank have read-write operation, controller side can carry out PRESET operations to the bank without read-write operation, the PRESET orders of controller only need to address bus and controlling bus, it is not necessary to data/address bus, therefore can accomplish completely concurrent with other Bank read-write operations.And when some Bank is during PRESET, if the read/write operation of the bank, PRESET operations can be suspended, wait continuation PRESET operations after the completion of read/write operation.

The embodiment of the present invention additionally provides a kind of data recording control apparatus, as shown in Fig. 2 including：Monitoring unit 201, for monitoring each memory heap in phase transition storage（Bank) whether there is read-write operation；Above-mentioned phase transition storage has two or more memory heaps（bank );

Fills unit 202, for the unit CELL pre-filled 1 in the memory heap (bank) without read-write operation that is monitored to above-mentioned monitoring unit 201;

Control unit 203 is write, for when needing to write data in above-mentioned phase transition storage, the target CELL currencys if desired write to need write-in data different from above-mentioned, then it is 0 to change above-mentioned target CELL.

The embodiment of the present invention, when PCM some memory heaps（When bank) having read-write operation, controller can be to the memory heap without read-write operation（Bank Preset operations) are carried out, Preset orders only need to address Bus and controlling bus, it is not necessary to data/address bus, therefore can accomplish and other memory heaps（Bank) read-write operation is completely concurrent.So as to lift read-write concurrency, the delay of normal write operation is reduced, PCM system write performance is lifted.

In embodiments of the present invention, if the data that write target CELL are 1, write operation may not necessarily be performed, the embodiments of the invention provide specific implementation in this case is as follows：Further, it is above-mentioned to write control unit 203, if being additionally operable to the destination address section pre-filled 1, and it is 1 to be currently needed for the data of write-in, then disconnects write operation loop, skip unit CELL filling of the data of above-mentioned needs write-in.

In embodiments of the present invention, pre-filled 1 scheme can be carried out pre-fill 1 to above-mentioned memory heap (bank) all CELL without read-write operation to operate, i.e. write-in 1 is operated, the CELL that former data can also be selected to be 0 is revised as 1, the CELL that former data are 1 is without processing, the operation to CELL can be so reduced, so that save power consumption and extend CELL life-span, it is specific as follows：Further, above-mentioned fills unit 202, former data for reading the unit CELL in the memory heap (bank) without read-write operation that above-mentioned monitoring unit 201 is monitored first, if former data are 1, then disconnect write operation loop, if former data are 0,1 is write.

In embodiments of the present invention, it is possible to occur to above-mentioned memory heap（Bank read-write operation), so needs to suspend pre-filled operation, it is to avoid read-write operation postpones, and the embodiments of the invention provide specific solution is as follows：Further, above-mentioned fills unit 202, is additionally operable in above-mentioned 202 pairs of memory heaps without read-write operation of fills unit（Bank during the unit CELL pre-filled 1 in), if above-mentioned monitoring unit 201 monitors the memory heap for carrying out pre-filled 1 in above-mentioned phase transition storage（Bank) there is read-write operation, then suspend to above-mentioned memory heap（Bank pre-filled 1 operation), until above-mentioned memory heap（Bank read-write operation) terminates.

In embodiments of the present invention, multiple memory heaps may be monitored（Bank) without read-write operation, memory heap can be arbitrarily selected in this case（Bank pre-filled operation) is carried out, following manner can also be preferably used and carry out pre-filled operation：Further, above-mentioned fills unit 202, if monitoring two or more memory heaps for above-mentioned monitoring unit 201（Bank) without read-write operation, then by the preferential former shellfish of queue length ' J, to above-mentioned two or more than two memory heaps（Bank) without the longer memory heap of read-write operation queue length（Bank the unit CELL pre-filled 1 in).

The embodiment of the present invention additionally provides a kind of phase transition storage, as shown in figure 3, including：Two or more use the memory heap of phase change memory medium（Bank) 301, bit line selecting switch 302, detection amplification Device 303, write driver 304;Above-mentioned detection amplifier 303 is connected with bit line selecting switch 302, and above-mentioned write driver 304 is connected with bit line selecting switch 302, and above-mentioned bit line selecting switch 302 is connected with above-mentioned detection amplifier 303 and above-mentioned write driver 304, in addition to：Control circuit 305;

Above-mentioned control circuit 305 is connected with above-mentioned bit line selecting switch 302, above-mentioned detection amplifier 303 and above-mentioned write driver 304；

Above-mentioned control circuit 305 monitors above-mentioned detection amplifier 303 and above-mentioned write driver 304 determines each memory heap（Bank) whether 301 have read-write operation, and send enabled instruction to bit line selecting switch 302, indicating that above-mentioned bit line selecting switch 302 is chosen needs pre-filled unit CELL in the memory heap bank without read-write operation, the unit CELL write-ins 1 that above-mentioned 304 pairs of write driver is chosen, implement pre-filled；In formal write operation, above-mentioned write driver 304 is after write operation instruction is received, if desired the target CELL currencys that the destination address section write is had been filled with 1, and above-mentioned destination address section need write-in data different from above-mentioned, then it is 0 to change above-mentioned target CELL.

In embodiments of the present invention, pre-filled 1 scheme can be carried out pre-fill 1 to above-mentioned memory heap (bank) all CELL without read-write operation to operate, i.e. write-in 1 is operated, the CELL that former data can also be selected to be 0 is revised as 1, the CELL that former data are 1 is without processing, the operation to CELL can be so reduced, so that save power consumption and extend CELL life-span, it is specific as follows：Alternatively, the above-mentioned upward rheme line options switch 302 of control circuit 305 sends enabled instruction, indicating that above-mentioned bit line selecting switch 302 is chosen needs pre-filled unit CELL in the memory heap bank without read-write operation, the unit CELL write-ins 1 that above-mentioned 304 pairs of write driver is chosen, implement pre-filled, including：

Above-mentioned control circuit 305 reads the above-mentioned memory heap without read-write operation by above-mentioned detection amplifier 303（Bank) the former data of the unit CELL in 301, if former data are 1, control disconnects write operation loop, if former data are 0, and above-mentioned control circuit 305 indicates write driver 304 to the pre-filled unit CELL write-ins 1 of above-mentioned needs.

Above-mentioned control circuit 305, be additionally operable to read need write data, and determine current data whether be 1, if 1 does not then send write instruction to above-mentioned write driver 304, that skips unit CELL writes 1 operation, if 0, then write instruction is sent to above-mentioned write driver 304, it is 0 above-mentioned write driver 304 is changed above-mentioned target CELL.

Following examples will provide PCM structure more detailed descriptions, refer to shown in Fig. 4, be that PCM structure charts are as follows：

The major function of each module is as follows：

PCM storage medium (PCM Storage Cell Array), comprising multiple bank, Fig. 4 show n Bank;I.e. n memory heap（ bank );

PCM bit line selecting switch（BitLine Sel), for selecting to need the Bitline of read-write operation;Word line driver（ WordLine Driver );

S/A、 W/D:Full name Fen Do are Sense Amplify (detection amplifiers）, Write Driver (write drivers）, this is the shared resource in PCM bank.Sense Amplify are used for the signal for detecting and amplifying CELL during read operation.Write Driver are used to provide driving current during write operation, and (the prolonged low current of row write 1 is entered to CELL）Or write the 0 (high current of short time）.

Latch input address（Address MUX), for latching the address of input and being distributed to WordLine

Driver, BitLine Sel。

Pre-filled control circuit（ Preset circuit ):That is Preset controls circuit, and concrete function has：(1), Preset controls circuit that some bank can be controlled to carry out preset operations, and the control process of specific preset operations is：The former data of CELL are first read, when the former data of CELL are 1, are then operated without preset（Disconnect write operation loop）, write operation number of times is reduced, to save power consumption and improve the CELL life-spans；When former CELL data are 0 Preset (write-in 1);

(2), the control process that Preset pauses one continue is：Address, write to preset operations (are write）Parameter etc. is preserved, to carry out other CELL read-write operation during preset, continues original CELL preset operations after the completion of other CELL read-write.

Pre-filled control circuit may be referred to shown in Fig. 5, wherein cell array（Cell Array), bit line selecting switch, S/A and W/D annexation it is same as shown in Figure 4, the interface and the reading data-interface in S/A for writing data are further illustrated in W/D, in Figure 5, two Slow be further comprises and rush device, (the first Slow rushes device for one of them）It is connected between W/D and bit line selecting switch, the interface that the first Slow rushes device meets another Slow and rushes device（2nd Slow rushes device）, above-mentioned 2nd Slow rushes the interface of device as an input of control instruction, Also provided in W/D and write input interface, the circuit can complete following function：Original CELL data are first read, when former CELL data are 1, are then operated without preset（Disconnect write operation loop）, write operation number of times is reduced, to save power consumption and improve the CELL life-spans；When former CELL data are 0 Preset (write-in 1).

Be described below the present embodiments relate to several major functional steps and flow：For convenience of describing, illustrate below by taking 2 bank as an example, can actually expand to multiple bank.

First, PCM controller:The read-write task that scheduled reception is arrived, when there is read-write operation, sends read write command, and record which bank belonged to.Then, Preset orders are sent to other bank.

Specific PCM controller implementing procedure figure, as shown in Figure 6：

601 :Read-write operation is first checked whether；If it is, into 602, otherwise into 607;

602:It is determined that whether the Bank for occurring read/write is bankl, if it is, into 603, otherwise entering

604;

603:Read/write command is sent to Bankl, sent after finishing（Completed without waiting for read/write）Into

605;

604:Read/write command is sent to Bank2, sent after finishing（Completed without waiting for read/write）Into

606;

605:, can be pre-filled to Bank2 parallel during Bankl performs read/write, terminate epicycle operation； 606:, can be pre-filled to Bankl parallel during Bank2 performs read/write, terminate epicycle operation； 607:Determine whether Bankl is preferential according to queue length preference strategy, if it is, into 608, otherwise into 609;

608:It is pre-filled to Bankl, terminate epicycle operation；

609:It is pre-filled to Bank2, terminate epicycle operation.

Above flow can be summarized as：Read-write operation is first checked whether, if without pending read/write operation, Preset orders can be initiated.It is specific which bank is carried out, there can be a variety of strategies, the embodiment of the present invention can be by the preferential strategy of queue length.If pending read/write operation, then the read/write operation is first initiated, then to other（It is idle）Bank sends Preset orders.

PCM sides perform specific as follows to Preset orders：When PCM is performed in Preset, if there is other CELL read-write task centre, the read-write operation of the CELL can be caused to postpone.In order to avoid such case, Preset can be added in PCM sides and suspends/continue function, it is specific as follows：Preset controls circuit pair Address, write parameters of preset operations etc. are preserved, to carry out other CELL read-write operation during Preset, continue original CELL Preset operations after the completion of other CELL read-write；Preset is operated based on the iterative SET operation being described above.Shown in idiographic flow below figure 7 is shown：

701 :It is loaded into optimal conjecture parameter；

The conjecture parameter is performed for the relevant parameter of write-in 1.

702:Carry out write operation；

In this step, initially performed using above-mentioned conjecture parameter and carry out write operation, it is follow-up to use the new parameter predicted in 705.

703:The complete rear retaking of a year or grade resistance value of write operation；

704:Determine whether resistance value meets preset value, if it is, this write-in 1 terminates, otherwise, into 705;

705:The new parameter of prediction；

706:Determine currently stored heap（Bank) whether there is read/write operation, if it is, into 707;Otherwise 702 are entered;

707:Read/write operation is performed, 702 are entered after finishing.

In above step 701 and 704, it will receive the target component of correlation, the execution of correspondence step is instructed.

Above step, can be summarized as：Optimal conjecture parameter is first loaded into, then enters row write.Rear retaking of a year or grade resistance value is write to determine whether to meet preset value.If meeting preset value, Preset terminates.If not meeting preset value, new parameter is calculated.Then judge whether this bank has the read-write operation of hang-up, if it is not, continuing the Preset of next round iteration;If so, then suspending Preset, the Preset that next round iteration is further continued for after read-write operation is performed.

The embodiment of the present invention, additionally provides the implementation that another Preset controls circuit, specific as follows：The write circuit of circuit is controlled for Preset, basic skills is：First retaking of a year or grade original CELL data：When data are 1, then operated without preset（Disconnect write operation loop）, write operation number of times is reduced, to save power consumption and improve the CELL life-spans；When data are 0 Preset (write-in 1).

The above method is so based on, there can be different implementations.It is illustrated in fig. 8 shown below, is followed successively by from top to bottom：Slow rushes device（), buffer inverting amplifier, FET and driving is write（write driver );Slow rushes device connection inverting amplifier, inverting amplifier and reconnects FET, and driving is write in FET connection； The program rushes device buffer retakings of a year or grade original CELL data by Slow, when for 1 when shut-off write driver;When for 0 when driving write driver perform the operation of write-in 1.

The implementation of other parts in the present embodiment may be referred to previous embodiment.

Above example, by lifted bank it is idle when concurrency, the delay of normal write operation can be greatly reduced, it is final to improve PCM system write performance.

The embodiment of the present invention additionally provides a kind of equipment, and the equipment can be terminal, as shown in figure 9, for convenience of description, illustrate only the part related to the embodiment of the present invention, particular technique details is not disclosed, refer to present invention method part.The terminal can be to include mobile phone, tablet personal computer, PDA (Personal Digital Assistant, personal digital assistant), POS (Point of Sales, point-of-sale terminal）, any terminal device such as vehicle-mounted computer, so that terminal is mobile phone as an example：

Fig. 9 is illustrated that the block diagram of the part-structure of the mobile phone related to terminal provided in an embodiment of the present invention.With reference to Fig. 9, mobile phone includes：Radio frequency（Radio Frequency, RF) circuit 910, memory 920, input block 930, display unit 940, sensor 950, voicefrequency circuit 960, Wireless Fidelity（Wireless fidelity, WiFi) part such as module 970, processor 980 and power supply 990.It it will be understood by those skilled in the art that the handset structure shown in Fig. 9 does not constitute the restriction to mobile phone, can include than illustrating more or less parts, either combine some parts or different parts arrangement.Wherein, memory 920 uses phase change memory medium.

Each component parts of mobile phone is specifically introduced with reference to Fig. 9：

RF circuits 910 can be used for receiving and sending messages or communication process in, the reception of signal and with sending , Te Do after the downlink information of base station is received, is handled to processor 980；In addition, being sent to base station by up data are designed.Generally, RF circuits 910 include but is not limited to antenna, at least one amplifier, transceiver, coupler, low-noise amplifier（Low Noise Amplifier, LNA), duplexer etc..In addition, RF circuits 910 can also be communicated by cordless communication network and other equipment.Above-mentioned radio communication can use any communication standard or agreement, including but not limited to global system for mobile communications（Global System of Mobile communication, GSM), month good business (General Packet Radio Service, GPRS) of general grouped wireless, CDMA（Code Division Multiple Access, CDMA), WCDMA（Wideband Code Division Multiple Access, WCDMA), Long Term Evolution（Long Term Evolution, LTE), Email, Short Message Service（Short Messaging Service, SMS) etc.. Memory 920 can be used for storage software program and module, and processor 980 is stored in the software program and module of memory 920 by operation, so as to perform various function application and the data processing of mobile phone.Memory 920 can mainly include storing program area and storage data field, wherein, the application program that storing program area can be needed for storage program area, at least one function（Such as sound-playing function, image player function etc.）Deng；Storage data field can be stored uses created data according to mobile phone（Such as voice data, phone directory etc.）Deng.In addition, memory 920 can include high-speed random access memory, nonvolatile memory, for example, at least one disk memory, flush memory device or other volatile solid-state parts can also be included.

Input block 930 can be used for the numeral or character information for receiving input, and the key signals that generation is set with the user of mobile phone and function control is relevant to input.Specifically, input block 930 may include contact panel 931 and other input equipments 932.Contact panel 931, also referred to as touch-screen, touch operation (such as user use any suitable object or annex operations on contact panel 931 or contact panel 931 near such as finger, stylus) of the user on or near it is collected, and corresponding attachment means are driven according to formula set in advance.Optionally, contact panel 931 may include both touch detecting apparatus and touch controller.Wherein, touch detecting apparatus detects the touch orientation of user, and detects the signal that touch operation is brought, and transmits a signal to touch controller；Touch controller receives touch information from touch detecting apparatus, and is converted into contact coordinate, then gives processor 980, and the order sent of reception processing device 980 and can be performed.Furthermore, it is possible to realize contact panel 931 using polytypes such as resistance-type, condenser type, infrared ray and surface acoustic waves.Except contact panel 931, input block 930 can also include other input equipments 932.Specifically, other input equipments 932 can include but is not limited to physical keyboard, function key（Such as volume control button, switch key etc.）, trace ball, mouse, the one or more in action bars etc..

Display unit 940 can be used for showing the information inputted by user or be supplied to the information of user and the various menus of mobile phone.Display unit 940 may include display panel 941, optionally, liquid crystal display (Liquid Crystal Display can be used, LCD), the form such as Organic Light Emitting Diode (Organic Light-Emitting Diode, OLED) configures display panel 941.Further, contact panel 931 can cover display panel 941, after contact panel 931 detects the touch operation on or near it, processor 980 is sent to determine the type of touch event, corresponding visual output is provided on display panel 941 according to the type of touch event with preprocessor 980.Although in fig .9, contact panel 931 and display panel 941 are input and the input function that mobile phone is realized as two independent parts, in some embodiments In, can be by contact panel 931 and the input that is integrated and realizing mobile phone of display panel 941 and output function.Mobile phone may also include at least one sensor 950, such as optical sensor, motion sensor and other sensors.Specifically, optical sensor may include ambient light sensor and proximity transducer, wherein, ambient light sensor can adjust the brightness of display panel 941 according to the light and shade of ambient light, proximity transducer can close display panel 941 and/or backlight when mobile phone is moved in one's ear.As one kind of motion sensor, accelerometer sensor can detect in all directions（Generally three axles）The size of acceleration, can detect that size and the direction of gravity when static, the application available for Shi Do mobile phone postures（Such as horizontal/vertical screen switching, dependent game, magnetometer pose calibrating）, vibration Shi Do correlation functions（Such as pedometer, percussion）Deng；The other sensors such as the gyroscope, barometer, hygrometer, thermometer, the infrared ray sensor that can also configure as mobile phone, will not be repeated here.

Voicefrequency circuit 960, loudspeaker 961, microphone 962 can provide the COBBAIF between user and mobile phone.Electric signal after the voice data received conversion can be transferred to loudspeaker 961, voice signal output is converted to by loudspeaker 961 by voicefrequency circuit 960；On the other hand, the voice signal of collection is converted to electric signal by microphone 962, by voicefrequency circuit 960 receive after be converted to voice data, after voice data output processor 980 is handled again, through RF circuits 910 to be sent to such as another mobile phone, or voice data exported to memory 920 so as to further processing.

WiFi belongs to short range wireless transmission technology, and mobile phone can help user to send and receive e-mail, browse webpage and access streaming video etc. by WiFi module 970, and it has provided the user wireless broadband internet and accessed.Although Fig. 9 shows WiFi module 970, but it is understood that, it is simultaneously not belonging to must be configured into for mobile phone, can be omitted as needed in the essential scope for do not change invention completely.

Processor 980 is the control centre of mobile phone, utilize various interfaces and the various pieces of connection whole mobile phone, software program and/or module in memory 920 are stored in by operation or execution, and call the data being stored in memory 920, the various functions and processing data of mobile phone are performed, so as to carry out integral monitoring to mobile phone.Optionally, processor 980 may include one or more processing units；It is preferred that, processor 980 can integrated application processor and modem processor, wherein, application processor mainly handles operating system, user interface and application program etc., and modem processor mainly handles radio communication.It is understood that above-mentioned modem processor can not also be integrated into processor 980.

Mobile phone also includes (the such as battery of power supply 990 powered to all parts）, it is preferred that power supply can be logically contiguous by power-supply management system and processor 980, so as to realize that management is filled by power-supply management system The functions such as electricity, electric discharge and power managed.

Although not shown, mobile phone can also include camera, bluetooth module etc., will not be repeated here.In embodiments of the present invention, the processor 980 included by the terminal also has following functions：Monitor each memory heap in phase transition storage（Bank) whether there is read-write operation；Above-mentioned phase transition storage has two or more memory heaps（bank );To the memory heap without read-write operation（Bank the unit in)（CELL) pre-filled 1;When needing to write data in above-mentioned phase transition storage, if desired the destination address section pre-filled 1 of the data write, and the target CELL currencys in above-mentioned destination address section need write-in data different from above-mentioned, then it is 0 to change above-mentioned target CELL.

The embodiment of the present invention, when PCM some memory heaps（When bank) having read-write operation, processor 980 can be to the memory heap without read-write operation（Bank Preset operations) are carried out, Preset orders only need to address bus and controlling bus, it is not necessary to data/address bus, therefore can accomplish and other memory heaps（Bank) read-write operation is completely concurrent.So as to lift read-write concurrency, the delay of normal write operation, lifting are reduced

PCM system write performance.

In embodiments of the present invention, pre-filled 1 scheme can be carried out pre-fill 1 to above-mentioned memory heap (bank) all CELL without read-write operation to operate, i.e. write-in 1 is operated, the CELL that former data can also be selected to be 0 is revised as 1, the CELL that former data are 1 is without processing, the operation to CELL can be so reduced, so that save power consumption and extend CELL life-span, it is specific as follows：Processor 980, for the memory heap without read-write operation（Bank the unit CELL pre-filled 1 in) includes：The above-mentioned memory heap without read-write operation is read first（Bank the former data of the unit CELL in), if former data are 1, disconnect write operation loop, if former data are 0, write 1.

In embodiments of the present invention, it is possible to occur to above-mentioned memory heap（Bank read-write operation), so needs to suspend pre-filled operation, it is to avoid read-write operation postpones, and the embodiments of the invention provide specific solution is as follows：Processor 980, for the memory heap without read-write operation（Bank also include during the unit CELL pre-filled 1 in)：If PCM phase transition storages 920 monitor the memory heap for carrying out pre-filled 1 in above-mentioned phase transition storage（Bank) there is read-write operation, then PCM phase transition storages 920 suspend to above-mentioned memory heap（Bank pre-filled 1 operation), until above-mentioned memory heap（Bank read-write operation) terminates.

In addition, in embodiments of the present invention, processor 980 may monitor multiple memory heaps（Bank) without read-write operation, memory heap can be arbitrarily selected in this case（Bank pre-filled operation) is carried out, also may be used Pre-filled operation is carried out to preferably use following manner：Processor 980, if for monitoring two or more memory heaps（Bank it is above-mentioned to the memory heap without read-write operation) without read-write operation（Bank the unit CELL pre-filled 1 in) includes：By queue length priority principle, to above-mentioned two or more than two memory heaps（Bank) without the longer memory heap of read-write operation queue length（Bank the unit CELL pre-filled 1 in).

It is understood that in embodiments of the present invention, if the data that write target CELL are 1, write operation may not necessarily be performed, the embodiments of the invention provide specific implementation in this case is as follows：Memory 920, if the destination address section of the data write for above-mentioned needs pre-filled 1, and it is 1 to be currently needed for the data of write-in, then disconnects write operation loop, skip unit CELL filling.

Based on preceding description, in embodiments of the present invention, PCM memory cell is a two-dimentional matrix structure, is divided according to row and column (row), and each column includes multiple memory cell again（Each CELL storages lbit).Present invention incorporates RAM (Random Access Memory, random access memory）The institutional framework of chip, proposition bank be (bar shaped）The scheme of concurrent operations between heap, improves system write operation speed.RAM-as there is multiple bank (such as current DDR3 (Double Data Rate 3, octuple rate DRAM）Chip typically has 8 bank), with hoist capacity and property an ancient type of spoon.

It is worth noting that, said apparatus is simply divided according to function logic, but above-mentioned division is not limited to, as long as corresponding function can be realized；In addition, the specific name of each functional unit is also only to facilitate mutually distinguish, the protection domain being not intended to limit the invention.

In addition, one of ordinary skill in the art will appreciate that realizing the whole in above-mentioned each method embodiment or portion It can be by program step by step to instruct the hardware of correlation to complete, corresponding program can be stored in a kind of computer-readable recording medium, and storage medium mentioned above can be read-only storage, disk or CD etc..

It these are only the present invention preferably embodiment; but protection scope of the present invention is not limited thereto; any one skilled in the art is in the technical scope that the embodiment of the present invention is disclosed; the change or replacement that can be readily occurred in, should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be defined by scope of the claims.

Claims

Claim

1st, a kind of data storage control method, it is characterised in that including：

Whether each memory heap bank in monitoring phase transition storage has read-write operation, to the unit CELL pre-filled 1 in the memory heap bank without read-write operation;The phase transition storage has two or more memory heap bank;

When needing to write data in the phase transition storage, if desired the destination address section pre-filled 1 of the data write, and the target CELL currencys in the destination address section need write-in data different from described, then it is 0 to change the target CELL.

2nd, method according to claim 1, it is characterised in that also include：

If the destination address section of the data for needing to write pre-filled 1, and it is 1 to be currently needed for the data of write-in, then disconnects write operation loop, skip unit CELL filling.

3rd, method according to claim 1, it is characterised in that the unit CELL pre-filled 1 in the described couple of memory heap bank without read-write operation includes：

The former data of the unit CELL in the memory heap bank without read-write operation are read first, if former data are 1, write operation loop are disconnected, if former data are 0, write 1.

4th, method according to claim 2, it is characterised in that also include during the unit CELL pre-filled 1 in the memory heap bank without read-write operation：

If monitoring, the pre-filled 1 memory heap bank of carrying out in the phase transition storage has read-write operation, suspends pre-filled 1 operation to the memory heap bank, until the read-write operation of the memory heap bank terminates.

5th, according to Claims 1-4 any one methods described, it is characterised in that if monitoring, two or more memory heap bank do not have the unit CELL pre-filled 1 in read-write operation, the described couple of memory heap bank without read-write operation to include：

By queue length priority principle, there is no the unit CELL pre-filled 1 in the longer memory heap bank of read-write operation queue length to described two or more than two memory heap bank.

6th, a kind of data recording control apparatus, it is characterised in that including：

Whether monitoring unit, each memory heap bank for monitoring in phase transition storage has read-write operation；The phase transition storage has two or more memory heap bank;

Fills unit, in the memory heap bank without read-write operation that is monitored to the monitoring unit Unit CELL pre-filled 1;

Write control unit, for when needing to write data in the phase transition storage, if desired the destination address section of the data write is by the fills unit pre-filled 1, and the target CELL currencys in the destination address section need write-in data different from described, then it is 0 to change the target CELL.

7th, device according to claim 6, it is characterised in that

It is described to write control unit, if being additionally operable to the destination address section pre-filled 1, and it is 1 to be currently needed for the data of write-in, then disconnects write operation loop, skip unit CELL filling of the data for needing to write.

8th, device according to claim 6, it is characterised in that

The fills unit, the former data for reading the unit CELL in the memory heap bank without read-write operation that the monitoring unit is monitored first, if former data are 1, disconnect write operation loop, if former data are 0, write 1.

9th, device according to claim 6, it is characterised in that

The fills unit, it is additionally operable to during the fills unit is to the unit CELL pre-filled 1 in the memory heap bank without read-write operation, if the monitoring unit monitors that the pre-filled 1 memory heap bank of carrying out in the phase transition storage has read-write operation, then suspend pre-filled 1 operation to the memory heap bank, until the read-write operation of the memory heap bank terminates.

10th, according to claim 6 to 9 any one described device, it is characterised in that

The fills unit, if monitoring that two or more memory heap bank do not have read-write operation for the monitoring unit, queue length priority principle is then pressed, does not have the unit CELL pre-filled 1 in the longer memory heap bank of read-write operation queue length to described two or more than two memory heap bank.

11st, a kind of phase transition storage, it is characterised in that including：Two or more are using the memory heap bank of phase change memory medium, bit line selecting switch, detection amplifier, write driver；The detection amplifier is connected with bit line selecting switch, and the write driver is connected with bit line selecting switch, and the bit line selecting switch is connected with the detection amplifier and the write driver, it is characterised in that also included：Control circuit；

The control circuit is connected with the bit line selecting switch, the detection amplifier and the write driver；

Detect that amplifier and the write driver determine that each memory heap bank is described in the control circuit monitoring It is no to have read-write operation, and send enabled instruction to bit line selecting switch, indicating that the bit line selecting switch is chosen needs pre-filled unit CELL in the memory heap bank without read-write operation, unit CELL write-in 1 of the write driver to choosing, and implements pre-filled；The write driver is after write operation instruction is received, and the target CELL currencys that the destination address section if desired write is had been filled with 1, and destination address section need write-in data different from described, then it is 0 to change the target CELL.

12nd, the phase transition storage according to claim 11, it is characterized in that, it is described to send enabled instruction to bit line selecting switch, indicating that the bit line selecting switch is chosen needs pre-filled unit CELL in the memory heap bank without read-write operation, the write driver to choose unit CELL write-in 1, implement it is pre-filled including：

The control circuit reads the former data of the unit CELL in the memory heap bank without read-write operation by the detection amplifier, if former data are 1, then control disconnects write operation loop, if former data are 0, the control circuit indicates that write driver needs pre-filled unit CELL write-ins 1 to described.

13rd, the phase transition storage according to claim 11 or 12, it is characterised in that

The control circuit, it is additionally operable to read the data for needing to write, and determine whether current data is 1, if 1 does not then send write instruction to the write driver, that skips unit CELL writes 1 operation, if 0, then write instruction is sent to the write driver, it is 0 the write driver is changed the target CELL.