CN101404179A - Method for improving programming speed of phase-change memory - Google Patents
Method for improving programming speed of phase-change memory Download PDFInfo
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- CN101404179A CN101404179A CNA2008102024058A CN200810202405A CN101404179A CN 101404179 A CN101404179 A CN 101404179A CN A2008102024058 A CNA2008102024058 A CN A2008102024058A CN 200810202405 A CN200810202405 A CN 200810202405A CN 101404179 A CN101404179 A CN 101404179A
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Abstract
The invention provides a method and a realization method used for improving the programming speed of a phase-change memory, and is characterized in that global SET programming operation is carried out on a part of a memory unit or a memory unit block which has no data or memorizes no data during the idle programming time of the memory; the idle time is a task state that the memory unit is in a standby state without programming; the global SET programming operation leads all memory units or memory unit blocks to be in a data '1' state. The invention also comprises a circuit used for realizing the global SET method: whether next operations of reading, writing and wiping exist is monitored within the inherent time after the operations of reading, writing and wiping are completed; if so, the memory is regarded as being busy and the global SET operation is not carried out; if not, the memory is regarded as being idle and the global SET operation is started.
Description
Technical field
The present invention relates to a kind of method and implementation method that promotes programming speed of phase-change memory, belong to the semiconductor memory field.
Background technology
Phase transition storage (PCRAM) is putative a kind of important nonvolatile memory of future generation, will occupy important one seat in the semiconductor memory market in future, has wide commercial application prospect.In phase transition storage, be utilize phase-change material in the storer " high resistant " and " low-resistance " but between two states the inverse conversion under the electric pulse effect realize the storage of data " 0 " and " 1 ".In the programming of phase transition storage, realize that low-resistance arrives the variation of high resistant, need apply a RESET pulse, be characterized in higher and narrower, its objective is the fusing that realizes phase-change material; Realize that high resistant arrives the variation of low-resistance, then need to apply a SET pulse, be characterized in the medium and broad of intensity, its objective is the crystallization that realizes phase-change material.In the programming of phase transition storage, (the former be about the time latter about 10 times) is longer than the RESET programming time in the SET programming time far away, so the programming time of phase transition storage mainly is limited by the SET time.In the evolution of storer, the demand of high speed nonvolatile semiconductor memory is just being promoted the lifting of phase transition storage storage speed, the speed that promotes phase transition storage has following several respects: exploitation phase-change material at a high speed; Carry out reading in advance of phase transition storage, reduce the number of times of programming operation etc.The present invention is longer than the RESET programming time far away in view of the SET programming time, and in addition, storer has a large amount of free time when standby, propose another kind of solution at the program speed that how to promote storer.
Summary of the invention
The object of the present invention is to provide a kind of method that promotes programming speed of phase-change memory, and propose the implementation method of this method on circuit.
Present PCRAM is the storer of binary states, be that data in the memory stores are for " 0 " and " 1 " two states, in programming process, RESET (makes storage unit realize the programming of high-impedance state, write " 0 ") program speed will be far away faster than the program speed of SET (making storage unit realize the programming of low resistance state, one writing).And according to probability statistics, in programming, the probability that need carry out RESET and SET programming is suitable basically, and therefore, the program speed of PCRAM mainly is limited by the speed of SET process.
The present invention proposes a kind ofly in memory program free time the storage unit or the memory cell block of no datat or storage unit or the memory cell block of not storing data division to be carried out SET programming operation of overall importance.Described free time be memory cell for holding state, do not have the programming task.SET programming operation of overall importance makes all storage unit or memory cell block all be in the data one state, storage unit or unit module are carried out in the programming operation process of SET of overall importance, if originally just be in one state, then needn't carry out SET programming operation process; Otherwise, then need the SET programming operation, making transformation of data is one state.Behind the programming operation by SET of overall importance, all be from the SET attitude to all programming operations of PCRAM, the initial state that is about to all storage unit that need programme or memory cell block is set to low resistance state, writes data at low resistance state again.Obviously, to initial state be SET attitude (low resistance state, data " 1 ") when programming, have two kinds may, the one, write data " 1 ", just need not to do any programming operation in the case, compare with straight WriteMode and saved a large amount of time; The 2nd, obtain RESET attitude (high-impedance state, data " 0 "), so only need to send the of short duration RESET pulse of pulse width.This kind programmed method is than traditional method that contains the SET programming, and program speed significantly rises.In addition, above-mentioned SET process of overall importance is to utilize the free time in the PCRAM use to carry out, the programming efficiency of PCRAM device is further promoted, final this method can shorten the program speed of storer greatly, and rationally utilize the time (efficiently being utilized the speed when having promoted programming free time).
In a word, a kind of method that promotes programming speed of phase-change memory that the present invention proposes, it is characterized in that utilizing free time in the phase transition storage use to no datat or do not store the storage unit of data division or memory cell block carries out SET operation (making storage unit forward low resistive state to from high-impedance state), when data write, all programming operations all were from SET attitude (" 1 ").
1. one of feature be write in data fashionable, if the data of writing " 1 " then do not need storage unit is operated;
2. two of feature be write in data fashionable, if the data of writing " 0 " then use RESET (making storage unit change to the process of high-impedance state from low resistance state) programming signal that storage unit is operated;
3. three of feature is to utilize the high resistant of phase-change material and the storage that the reversible transition between the low-resistance is realized data;
4. four of feature is that the purpose of programming operation is to make storage unit be set to low resistance state; Described " RESET " operation is to have fast speeds than " SET " operation, and the purpose of " RESET " programming operation is to make storage unit reach high-impedance state;
5. five of feature is to utilize free time to carry out overall SET operation, does not take the busy period of data reading and writing; The no datat or the storage unit of not storing data division are carried out overall SET operation; Described " no datat or the storage unit of not storing data division " is to adopt the method that indicates to show that this storage unit is a no datat.Can be at single storage unit, also can be at the whole memory unit piece;
6. six of feature is when a certain storage block is programmed, and other no datat or storage unit or the memory cell block of not storing data division are carried out overall SET programming operation.
The present invention also provides a kind of circuit implementation method of overall SET method: utilize clock counter, whether monitoring has reading and writing next time, wipes operation in intrinsic time after reading and writing, wiping operation are finished: if having, think that then storer is busy, do not carry out overall SET; If no, think that then storer free time, this moment start overall SET operation.After executing reading and writing, wiping operation, clock begins counting, sets an adjustable count value.When before next reading and writing, wiping the operation arriving,,, carry out the SET operation at the unit of not storing data in the storage chip just start overall SET operation so if the clock count cycle reaches count value; If the clock period does not reach count value, just carry out next reading and writing so, wipe operation and empty the count cycle.In the process of carrying out overall SET operation, if having reading and writing, wiping operation to occur, interrupt overall SET operation at once, carry out reading and writing, wipe and operate, and empty the count cycle, reach count value again up to the clock count cycle and carry out overall SET operation once more.
By accommodometer numerical value, can regulate the startup frequency of overall SET operation, thus the range of application of regulating storer.Comparatively concentrated in programming data when memory application, and power consumption requires lowlyer, and the storer that capacity is bigger can suitably be set less count value; If programming data comparatively disperses, and rate request is higher, and the storer that capacity is less can suitably be set bigger count value.
Description of drawings
Fig. 1 PCRAM program timing sequence synoptic diagram.
Fig. 2 PCRAM SET process of overall importance is about to all device cells of not storing data and carries out SET between at one's leisure, obtains SET attitude (data " 1 ") as initial state.
Programming synoptic diagram in the storage unit of Fig. 3 PCRAM after SET programming of overall importance, adding black " 0 " among the figure is exactly RESET programmed cells (data " 0 "), and all the other do not become, without any need for operation.
Fig. 4 overall situation SET circuit is realized state machine diagram.
Embodiment
Further illustrate substantive distinguishing features of the present invention and obvious improvement below in conjunction with accompanying drawing.
1. the characteristics of current PC RAM are that the process of write data " 1 " and write data " 0 " is asymmetric, and the speed of the process of write data " 1 " (being the SET process) will be much slower than the process of write data " 0 " (being the RESET process), as shown in Figure 1.If SET process that can speed is slower is operated between at one's leisure, the program speed of phase transition storage will be promoted significantly.
2. the PCRAM free time, unit or cell block that to not store data (perhaps data are deleted) carry out the overall situation " SET " operation, utilize the SET pulse with " 0 " attitude (high-impedance states all in the device cell, the RESET attitude) changes one state into, be equivalent to be initialised to " 1 ", as shown in Figure 2.
3. when PCRAM need programme, be to carry out in the memory module of " 1 " through the total data behind the overall SET exactly.When writing data continuously,, do not need to carry out any programming operation if one writing just can be skipped; If write " 0 ", then utilize the RESET operation that " 1 " is rewritten as " 0 ", be about to relevant phase-change memory cell and be converted to high-impedance state from low resistance state, the synoptic diagram of this process is as shown in Figure 3.
4. will be because of the speed of RESET programming far above the speed of SET programming, when busy programming, no longer need the SET operation after employing the method, the program speed of PCRAM just promotes greatly; In addition, exist half probability will carry out the one writing operation, run into this situation and can skip, saved the programming time of half again; And mostly the overall SET operation of PCRAM memory module is to finish in the time of PCRAM free time, so the storage speed of all final storeies is greatly improved.
As shown in Figure 4, overall SET circuit is realized state machine diagram: after executing reading and writing, wiping, clock begins counting, sets an adjustable count value.When before next reading and writing, wiping the operation arriving,,, carry out the SET operation at the unit of not storing data in the storage chip just start overall SET operation so if the clock count cycle reaches count value; If the clock period does not reach count value, just carry out next reading and writing so, wipe operation and empty the count cycle.In the process of carrying out overall SET operation, if having reading and writing, wiping operation to occur, interrupt overall SET operation at once, carry out reading and writing, wipe and operate, and empty the count cycle, reach count value again up to the clock count cycle and carry out overall SET operation once more.By accommodometer numerical value, can regulate the startup frequency of overall SET operation, thus the range of application of regulating storer.Comparatively concentrated in programming data when memory application, and power consumption requires lowlyer, and the storer that capacity is bigger can suitably be set less count value; If programming data comparatively disperses, and rate request is higher, and the storer that capacity is less can suitably be set bigger count value.
What should emphasize is that description of the invention and application are illustrative, is not only with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment or change all are possible, and for the person of ordinary skill of the art, the method for the replacement of embodiment and equivalence is known.Those skilled in the art are noted that under the situation that does not break away from spirit of the present invention or essential characteristic the present invention can realize with other forms, process, method.
Claims (8)
1, a kind of method that promotes programming speed of phase-change memory is characterized in that in memory program free time no datat or storage unit or the memory cell block of not storing data division being carried out SET programming operation of overall importance; Described free time is that memory cell is in holding state, does not have the task status of programming; Described SET programming operation of overall importance makes all storage unit or memory cell block all be in the data one state.
2, press the method for the described lifting programming speed of phase-change memory of claim 1, it is characterized in that storage unit or memory cell block are carried out the programming operation of SET of overall importance, storage unit or memory cell block are in one state, then needn't carry out the SET operation to storage unit or memory cell block; Storage unit or memory cell block are not in one state, then need storage unit or memory cell block are carried out the SET programming operation, and making transformation of data is one state.
3, press the method for claim 1 or 2 described lifting programming speed of phase-change memory, it is characterized in that by behind the SET programming operation of overall importance, all programming operations that make phase transition storage all are from the SET attitude, even storage unit or memory cell block forward low resistance state to from high-impedance state.
4, by the method for the described lifting programming speed of phase-change memory of claim 1, the storage unit or the memory cell block that it is characterized in that described no datat or do not store data division adopt the method that indicates to show that storage unit or memory cell block are no datat.
5, by the method for the described lifting programming speed of phase-change memory of claim 4, the method that it is characterized in that indicating is at single storage unit or at the whole memory unit piece.
6, press the method for the described lifting programming speed of phase-change memory of claim 1, when it is characterized in that a certain storage unit or memory cell block programmed, other no datat or storage unit or the memory cell block of not storing data division are carried out overall SET programming operation.
7, realize the method for the described lifting programming speed of phase-change memory of claim 1, it is characterized in that the steps include:
1. after executing reading and writing, wiping, clock begins counting, sets an adjustable count value;
2. when before next reading and writing, wiping the operation arriving,, then start overall SET operation if the clock count cycle reaches count value; Carry out overall SET programming operation at no datat in the storage chip or the unit of not storing data;
If 3. the clock period does not reach count value, then carry out next reading and writing, wipe and operate and empty the count cycle;
4. in the process of carrying out overall SET operation,, interrupt overall SET operation at once, carry out reading and writing, wipe and operate, and empty the count cycle, reach count value again up to the clock count cycle and carry out overall SET operation once more if having reading and writing, wiping operation to occur.
8,, it is characterized in that by regulating clock count value, the startup frequency of regulating overall SET programming operation by the implementation method of the described lifting programming speed of phase-change memory of claim 7.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102013271B (en) * | 2009-09-08 | 2013-04-24 | 中国科学院上海微系统与信息技术研究所 | Fast reading device and method of phase change memory |
| CN104318956A (en) * | 2014-09-30 | 2015-01-28 | 山东华芯半导体有限公司 | Method and device for programming storage array of resistive random access memory |
| CN104517640A (en) * | 2013-09-30 | 2015-04-15 | 华为技术有限公司 | Phase change memory management method and phase change memory management apparatus |
| WO2015081488A1 (en) * | 2013-12-03 | 2015-06-11 | 华为技术有限公司 | Data storage control method and apparatus |
| CN105264608A (en) * | 2014-04-30 | 2016-01-20 | 华为技术有限公司 | Data storage method, memory controller and central processing unit |
| CN106610883A (en) * | 2015-10-27 | 2017-05-03 | 腾讯科技（深圳）有限公司 | Detection method and device |
| US10418100B2 (en) | 2015-03-30 | 2019-09-17 | Xi'an Uniic Semiconductors Co., Ltd. | RRAM subarray structure proving an adaptive read reference current |
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2008
- 2008-11-07 CN CN2008102024058A patent/CN101404179B/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102013271B (en) * | 2009-09-08 | 2013-04-24 | 中国科学院上海微系统与信息技术研究所 | Fast reading device and method of phase change memory |
| CN104517640A (en) * | 2013-09-30 | 2015-04-15 | 华为技术有限公司 | Phase change memory management method and phase change memory management apparatus |
| CN104517640B (en) * | 2013-09-30 | 2017-08-25 | 华为技术有限公司 | A kind of phase transition internal memory management method and device |
| CN105264609B (en) * | 2013-12-03 | 2018-05-18 | 华为技术有限公司 | A kind of data storage control method and device |
| WO2015081488A1 (en) * | 2013-12-03 | 2015-06-11 | 华为技术有限公司 | Data storage control method and apparatus |
| CN105264609A (en) * | 2013-12-03 | 2016-01-20 | 华为技术有限公司 | Data storage control method and apparatus |
| CN105264608B (en) * | 2014-04-30 | 2018-03-06 | 华为技术有限公司 | Method, Memory Controller Hub and the central processing unit of data storage |
| CN105264608A (en) * | 2014-04-30 | 2016-01-20 | 华为技术有限公司 | Data storage method, memory controller and central processing unit |
| CN104318956B (en) * | 2014-09-30 | 2018-05-15 | 西安紫光国芯半导体有限公司 | A kind of resistive random access memory storage array programmed method and device |
| CN104318956A (en) * | 2014-09-30 | 2015-01-28 | 山东华芯半导体有限公司 | Method and device for programming storage array of resistive random access memory |
| US10522221B2 (en) | 2014-09-30 | 2019-12-31 | Xi'an Uniic Semiconductors Co., Ltd. | Storage array programming method and device for resistive random access memory |
| US10418100B2 (en) | 2015-03-30 | 2019-09-17 | Xi'an Uniic Semiconductors Co., Ltd. | RRAM subarray structure proving an adaptive read reference current |
| CN106610883A (en) * | 2015-10-27 | 2017-05-03 | 腾讯科技（深圳）有限公司 | Detection method and device |
| CN106610883B (en) * | 2015-10-27 | 2020-09-11 | 腾讯科技（深圳）有限公司 | Detection method and device |
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