CN105262056B - A kind of pwm signal isolated variable system based on pulse transformer - Google Patents
A kind of pwm signal isolated variable system based on pulse transformer Download PDFInfo
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- 230000001681 protective effect Effects 0.000 claims abstract description 41
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- 230000002457 bidirectional effect Effects 0.000 claims description 10
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Abstract
The present invention provides a kind of pwm signal isolated variable system based on pulse transformer, including pwm signal input protective module, a primary pwm signal isolated variable module, a grade pwm signal restore reconstructed module, a primary source VCC under-voltage protective module, a primary fault protective module, a primary ERROR signal output module；The pwm signal is reduced to and the HPWM signal of original PWM input signal same-phase after signal isolation conversion module and secondary pwm signal reduction reconstructed module.
Description
Technical field
The present invention relates to a kind of electronic information technology, especially a kind of pwm signal isolated variable based on pulse transformer
System.
Background technique
For pwm signal in transmission, common isolation method has optical isolation and Magnetic isolation, and light-coupled isolation mode is due to isolation electricity
It presses relatively low, there are problems that transmission delay, aging and poor reliability etc..And use pulse transformer isolation method
Relatively high isolation voltage may be implemented in (Magnetic isolation), and the high reliablity of transformer, transmission delay are small, may be implemented compared with
The problem of high switching frequency, there is no agings, therefore, when driving high pressure all-controlling power electronics device, become using pulse
The isolation that depressor completes driving signal as isolation element is a relatively good selection.But based on traditional transformer
Pwm signal isolated variable circuit usually require that control pulse duty factor less than 50%, the saturation problem of traditional transformer magnetic core
The turn-on time of control pulse is limited, in addition, easily break down there is also PWM waveform distortion, the disadvantages of poor reliability, very
The application of this kind of circuit is limited in big degree.
Summary of the invention
The pwm signal isolated variable system based on pulse transformer that the purpose of the present invention is to provide a kind of.System tool
Have that signal transmission frequencies are high, transmission delay is small, function expansibility is strong, reliable and stable, at low cost, outer dimension is small, strong applicability
The features such as, it is highly suitable to be applied in the dedicated driving circuit of wholly-controled device (such as IGBT, power MOSFET).
A kind of pwm signal isolated variable system based on pulse transformer, including a pwm signal input protective module, one
Primary pwm signal isolated variable module, grade pwm signal reduction reconstructed module, a primary source VCC under-voltage protective module,
One primary fault protective module, a primary ERROR signal output module.
The pwm signal input protective module receives PWM input signal, if circuit system breaks down, blocks PWM arteries and veins
Rush at secondary transmitting；The primary pwm signal isolated variable module is used to PWM input signal transformation being modulated into bidirectional pulse；
The secondary pwm signal reduction reconstructed module is of coupled connections with primary pwm signal isolated variable module, double to the secondary after coupling
It is reduced to by way of signal reconstruction to pulse and the HPWM signal of original PWM input signal same-phase；The primary source is owed
It presses protective module to be used to provide supply voltage under-voltage protection to circuit system, if supply voltage occurs under-voltage, issues power supply and owe
Press signal；The primary fault protective module, which is used to work as, receives line under-voltage signal or secondary pwm signal reduction reconstructed module
When breaking down, pwm signal is blocked to transmit to secondary；If line under-voltage signal or secondary pwm signal restore reconstructed module
Trouble shooting, generates reset signal, and circuit works normally；The primary ERROR signal output module is in line under-voltage or secondary
Output error signal when pwm signal reduction reconstructed module breaks down.
Further, which further includes temporary source energy supply module, for providing interim electricity when line under-voltage
Source voltage, and the module charges to the numerical value of supply voltage when supply voltage is normal.
Further, which further includes secondary fail protective module, for when secondary pwm signal reduction reconstructed module hair
When raw failure, generates fault-signal and trigger primary fault protective module.
Compared with prior art, the present invention having the advantage that (1) present invention includes eight modules, eight modules are mutual
Between be electrically connected, perfect in shape and function；(2) good opportunity failure protection module is arranged in system, failure when can be for under-voltage and PWM reconstruct into
Row detection, and issue instruction and targetedly protected；(3) protective module hinders pwm signal when system breaks down
Transmission, prevents the secondary injury caused by system.
The present invention is described further with reference to the accompanying drawings of the specification.
Detailed description of the invention
Fig. 1 is principle of the invention figure.
Fig. 2 is the schematic diagram of the invention with temporary source energy supply module and secondary fail protective module.
Fig. 3 is the schematic diagram of implementing circuit of the present invention.
Fig. 4 be implementing circuit of the present invention in pwm signal each point typical waveform schematic diagram in conversion process.
Fig. 5 is implementing circuit of the present invention each point typical waveform schematic diagram in error protection memory module.
Specific embodiment
A kind of pwm signal isolated variable system based on pulse transformer, which is characterized in that inputted including a pwm signal
Primary 2, the grade pwm signals of pwm signal isolated variable module of protective module 1, one restore reconstructed module 3, a primary source VCC
Under-voltage protective module 4,5, one primary ERROR signal output module 6 of a primary fault protective module；
The pwm signal input protective module 1 receives PWM input signal, if circuit system breaks down, blocks PWM
Pulse is transmitted to secondary；
The primary pwm signal isolated variable module 2 is for being modulated into bidirectional pulse for the transformation of PWM input signal；
The secondary pwm signal reduction reconstructed module 3 is of coupled connections with primary pwm signal isolated variable module 2, to coupling
Secondary bidirectional pulse afterwards is reduced to and the HPWM signal of original PWM input signal same-phase by way of signal reconstruction；
Described 4 pieces of primary source under-voltage protection mould are used to provide supply voltage under-voltage protection to circuit system, if power supply is electric
When extruding existing under-voltage, line under-voltage signal is issued；
The primary fault protective module 5, which is used to work as, receives line under-voltage signal or secondary pwm signal reduction reconstruct mould
When block breaks down, pwm signal is blocked to transmit to secondary；If line under-voltage signal or secondary pwm signal reduction reconstructed module hair
Raw trouble shooting, generates reset signal, and circuit works normally；The primary fault protective module 5 includes primary fault protection note
Recall module and primary fault reseting module；
The primary ERROR signal output module 6 breaks down in line under-voltage or secondary pwm signal reduction reconstructed module
When output error signal.
In conjunction with Fig. 2, which further includes temporary source energy supply module 7, for providing interim electricity when line under-voltage
Source voltage, and the module charges to the numerical value of supply voltage when supply voltage is normal.
In conjunction with Fig. 2, which further includes secondary fail protective module 8, for when secondary pwm signal reduction reconstructed module hair
When raw failure, generates fault-signal and trigger primary fault protective module.
The duty ratio that pwm signal is inputted in Fig. 4 is 50%, and the Same Name of Ends of supply voltage 15V, pulse transformer T1 are as schemed
Shown in 3, i.e. the end B of pulse transformer T1 primary coil L1 corresponds to the end F of secondary coil L2.
One provides the power supply VCC of operating voltage, and VCC chooses 15V in this example.
One pwm signal inputs protective module, by supply voltage VCC, the 16th resistance R16, the 6th Schmidt's NAND gate
U6, the 8th capacitor C8 and the 8th diode D8 composition, can be used for when circuit system breaks down, block pwm pulse to secondary
Transmitting, prevents from causing secondary hazards to system；Wherein, PWM input signal is connected to the pin 10 of the 6th Schmidt's NAND gate U6, electricity
Source voltage VCC is connected to GND through the 16th resistance R16 and the 8th capacitor C8, and the pin 9 of the 6th Schmidt's NAND gate U6 is connected to the tenth
The common end of six resistance R16 and the 8th capacitor C8 connection, while the pin 9 of the 6th Schmidt's NAND gate U6 passes through the 8th diode
D8 is connected to the point of the A in circuit；
The specific work process and principle of pwm signal input protective module: under normal circumstances, the current potential of A point is high level,
Therefore the 8th diode D8 positive can end, and supply voltage VCC is charged by the 16th resistance R16 to the 8th capacitor C8, until
Pressure drop on 8th capacitor C8 is close to supply voltage VCC, and the 6th Schmidt NAND gate U6 pin 9 is equivalent to high level, at this time
The signal with 180 ° of phase difference of PWM input signal phase can be exported after 6th Schmidt's NAND gate U6, which believes by primary PWM
It is coupled in the secondary coil L2 of pulse transformer T1 in the form of bidirectional pulse after number isolated variable circuit, finally by secondary
After pwm signal restores reconfigurable circuit, it is reduced to believe with the HPWM of original PWM input signal same-phase by way of signal reconstruction
Number；When circuit system breaks down, the current potential of A point can become low level, since the pressure drop on the 8th capacitor C8 before this is close
In supply voltage VCC, therefore the 8th diode D8 meeting forward conduction, the 8th capacitor C8 can be fast to A point by the 8th diode D8
Speed is discharged, and after discharge process, the current potential of the 6th Schmidt NAND gate U6 pin 9 can be pulled down to low level by equivalent, then
No matter how PWM input signal changes at this time, and the 6th Schmidt's NAND gate U6 can export always high level, primary pwm signal every
There is blocking effect to direct current signal from translation circuit, therefore PWM input signal will not be coupled and be transmitted in secondary circuit system,
It prevents from causing secondary hazards to system, realizes the protection to circuit system.
One primary pwm signal isolated variable circuit, mainly includes the 15th resistance R15, the 6th capacitor C6, the 5th capacitor
C5, pulse transformer T1 and the 25th resistance R25, main function be by PWM input signal transformation be modulated into bidirectional pulse, then
Through pulse transformer T1 isolation coupling to secondary；Wherein, an end of the 15th resistance R15 is connected to the 6th Schmidt's NAND gate U6's
Output end, the other end are connected to GND through the inductive primary L1 of the 6th capacitor C6, the 5th capacitor C5 and pulse transformer T1, the
An end of 25 resistance R25 is connected to HGND, and the other end is connected to HGND through the inductive secondary L2 of pulse transformer T1；
The specific work process and principle of primary pwm signal isolated variable circuit: the output letter of the 6th Schmidt's NAND gate U
Number U6_OUT, when the rising edge of U6_OUT arrives, the upper impulse of the 6th capacitor C6 and the 5th capacitor C5 in U6_OUT is made
Under, it is believed that instantaneous short circuit, inductive drop incude formula:
The induced current change rate in the inductive primary L1 of pulse transformer T1 is positive at this time, according to inductive drop sense
Formula is answered, can generate instantaneous positive impulse voltage on the end B of pulse transformer T1 inductive primary L1 at this time, pulse becomes
Depressor T1 inductive primary L1 is in the charging stage.Stable high level mistake is gradually exported to coming by rising edge in U6_OUT
Induced current change rate in the inductive primary L1 of Cheng Zhong, pulse transformer T1 is still positive, but can be gradually reduced, until arteries and veins
The charging stage for rushing transformer T1 inductive primary L1 terminates, meanwhile, the 6th capacitor C6 and the 5th capacitor C5 can be entered and be filled
The electric stage.When induced current after high level, in the inductive primary L1 of pulse transformer T1 is stablized in the output of U6_OUT
Change rate is gradually negative, and the inductive primary L1 of pulse transformer T1 becomes discharge regime, incudes formula according to inductive drop,
It will form negative voltage on the end B of pulse transformer T1 inductive primary L1, until discharge regime terminates, pulse transformer T1
The end B voltage on inductive primary L1 becomes zero, and charging process is completed in the 6th capacitor C6 and the 5th capacitor C5 at this time.
When the failing edge of U6_OUT arrives, the 6th capacitor C6 and the 5th capacitor C5 can be by the 15th resistance to U6_OUT
Electric discharge, there are discharge loops in circuit system: C5- > C6- > R15- > U6_OUT- > GND- > T1_L1- > C5, and discharge current becomes
Rate is positive, and the C-terminal of pulse transformer T1 inductive primary L1 charges, therefore the primary inductance of pulse transformer T1
The end B of coil L1 will form instantaneous negative sense impulse voltage.The discharge process of 6th capacitor C6 and the 5th capacitor C5 gradually terminates, and puts
Gradually by just becoming negative, the charging stage of the C-terminal of pulse transformer T1 inductive primary L1 terminates simultaneously gradually electric current changing rate
It is transitioned into the discharge regime at the end B, the voltage at the end B of the inductive primary L1 of pulse transformer T1 can be transitioned by negative voltage
Forward voltage.After the discharge process of 6th capacitor C6 and the 5th capacitor C5, the inductive primary L1 of pulse transformer T1
The discharge regime at the end B also terminate therewith, the voltage at the end B becomes zero.This is each ginseng in a complete cycle of U6_OUT
Several change procedures.Wherein, the change procedure U6_OUT signal of the end the B voltage of the inductive primary L1 of pulse transformer T1 it
Between relationship it is as shown in Figure 4.
The end position of the same name of pulse transformer T1 is as shown in figure 3, therefore on the end E of pulse transformer T1 secondary coil L2
The variation of induced voltage is with the end the B voltage of primary coil L1 on the contrary, the induced voltage at the end E of pulse transformer T1 secondary coil L2
T1_L2 can generate pressure drop on the 25th resistance R25, and the change procedure of T1_L2 is as shown in Figure 4.
According to analysis above it is found that primary pwm signal isolated variable circuit realizes PWM input signal converting modulation
At bidirectional pulse, then through pulse transformer T1 isolation coupling to secondary purpose.
One secondary pwm signal restores reconfigurable circuit, mainly include the 24th resistance R24, the 13rd diode D13,
12nd diode D12, the 23rd resistance R23, the 11st schmitt inverter U11 and the tenth schmitt inverter U10, it is main
Acting on is that will be coupled to secondary bidirectional pulse by pulse transformer T1, is reduced to by way of signal reconstruction and original PWM
The HPWM signal of input signal same-phase；Wherein, the anode of the 13rd diode D13 is connected to HGND, the 13rd diode D13's
Cathode is connected to what the 25th resistance R25 was connect with the inductive secondary L2 of pulse transformer T1 through the 24th resistance R24
Common end, while the cathode of the 13rd diode D13 is connected to the input terminal of the 11st schmitt inverter U11, the 11st apply it is close
The output end of special phase inverter U11 is connected to through the tenth schmitt inverter U10, the 23rd resistance R23 and the 12nd diode D12
The input terminal of 11st schmitt inverter U11 itself, while the output end output of the tenth schmitt inverter U10 is by reduction
HPWM signal afterwards；
The specific work process and principle of secondary pwm signal reduction reconfigurable circuit: as shown in figure 4, working as pulse transformer T1
When the direct impulse of the end the E induced voltage T1_L2 of secondary coil L2 arrives, T1_L2 can be by the 24th resistance to the 11st
The input terminal of schmitt inverter U11, it is assumed that the positive turnover voltage of the 11st schmitt inverter U11 is ViT+, works as T1_L2
When reaching ViT+, the output of the 11st schmitt inverter U11 is low level, the tenth schmitt inverter by high level overturning
The output of U10 is high level by low level overturning, the output of the tenth schmitt inverter U10 by the 23rd resistance R23 and
The input terminal of the 11st schmitt inverter U11 is returned to after 12nd diode D12, thus it is equivalent form one it is positive and negative
Feedback system, in this way before the negative-going pulse of T1_L2 does not arrive, U11- > U10 > R23- > D12- > U11 can be continued for, together
When since the cathode potential of the 13rd diode D13 is approximately high level, and anode potential is HGND low level, therefore the 13rd
Diode D13 can positive cut-off.When the negative-going pulse of T1_L2 arrives, the end E of pulse transformer T1 secondary coil L2 can be generated
Relative to the negative-going pulse that current potential HNGD is negative, and due to the 13rd diode D13 anode potential be HGND, the tenth
Three diode D13 meeting forward conduction, while the current potential of G point can be pulled down to HGND, therefore the 11st schmitt inverter U11
Input terminal is low level, exports low level by the tenth schmitt inverter U10.In the E of pulse transformer T1 secondary coil L2
After the negative-going pulse at end, although the 13rd diode D13 positive can end, since the current potential of G point is through the 24th electricity
The secondary coil L2 of resistance R24 and pulse transformer T1 pulled down to HGND low level, therefore is passing through the 11st Schmidt's reverse phase
Low level is still exported after device U11 and the tenth schmitt inverter U10, which continues until pulse transformer T1 secondary coil
The direct impulse of the end the E induced voltage T1_L2 of L2 arrives.This is the variation of the parameters in a complete cycle of T1_L2
Process.Wherein, the relationship between HPWM and T1_L2 is as shown in Figure 4.
According to analysis above it is found that secondary pwm signal reduction reconfigurable circuit realizes by way of signal reconstruction also
Originally it was and the purpose of the HPWM signal of original PWM input signal same-phase.
One primary source VCC under-voltage protective module mainly includes supply voltage VCC, the 8th resistance R8, the 9th resistance
R9, the first zener diode ZD1, second transistor Q2, the tenth resistance R10 and third Schmidt NAND gate U3, main function are
The function of supply voltage VCC under-voltage protection is provided to circuit system, when supply voltage VCC occurs under-voltage, which can be to first
Grade error protection memory module sends the under-voltage signal of supply voltage VCC, triggers under-voltage protection mechanism；Wherein, supply voltage VCC is passed through
8th resistance R8, the 9th resistance R9 and the first zener diode ZD1 are connected to GND, and the emitter of second transistor Q2 is connected to power supply
Voltage VCC, the common end connection that the base stage of second transistor Q2 is connect with the 8th resistance R8 and the 9th resistance R9, second transistor
The collector of Q2 is connected to GND through the tenth resistance R10, and the pin 4 of third Schmidt's NAND gate U3 is connected to the collection of second transistor Q2
Electrode；
The specific work process and principle of primary source VCC under-voltage protective module: the first zener diode ZD1's of setting is steady
Pressure value is 12V, and emitter-base bias voltage of second transistor Q2 is 0.7V, between the 8th resistance R8 and the 9th resistance R9
There is following proportionate relationship:
When supply voltage VCC is working properly, VCC=15V, the base voltage of second transistor Q2 at this time:
Since the emitter voltage of second transistor Q2 is VCC=15V, the emitter and base voltage of second transistor Q2
Difference be 1.5V, therefore the conducting of second transistor Q2, the current potential on the pin 4 of third Schmidt's NAND gate U3 is approximately power supply
Voltage VCC, is equivalent to high level.
When supply voltage VCC is in under-voltage condition, i.e. VCC < 13V, the base voltage of second transistor Q2 at this time:
The emitter of second transistor Q2 and the difference of base voltage are less than 0.5V, therefore the cut-off of second transistor Q2, the
Current potential on the pin 4 of three Schmidt's NAND gate U3 is pulled down to GND, is equivalent to low level.And work as third Schmidt NAND gate
When current potential on the pin 4 of U3 changes to low level by high level, primary fault protection memory module will be triggered, to realize
Supply voltage VCC under-voltage protection.
One primary fault protects memory module, mainly include supply voltage VCC, the first transistor Q1, the 4th resistance R4,
5th resistance R5, first capacitor C1, first diode D1, the 6th resistance R6, the 7th resistance R7, the 11st diode D11, the 4th
Diode D4, the 5th diode D5, second Schmidt's NAND gate U2, third Schmidt's NAND gate U3, the 24th resistance R24,
Tenth resistance R10, the 7th capacitor C7, the 14th resistance R14, thirteenth resistor R13, the 6th diode D6, the 7th diode D7,
4th capacitor C4, the 4th Schmidt's NAND gate U4, the 5th Schmidt's NAND gate U5, eleventh resistor R11, twelfth resistor R12,
Third capacitor C3 and third transistor Q3, main function be when occur supply voltage VCC it is under-voltage or it is secondary break down when, all can
Primary fault protection memory module is triggered, which can permanently latch the error signal of generation, and form memory, while wrong
It in the presence of error signal, blocks pwm signal to transmit to secondary, prevents from causing secondary hazards to system, which is continued until event
Barrier releases and releases error signal latch by primary fault reseting module or power cutoff voltage VCC and remove memory, in this way
Protection mechanism realize to the reliably protecting of circuit system, prevent because failure it is not adequately addressed in the case where, make circuit system again
System work causes to repeat to damage to circuit system.Wherein, supply voltage VCC is through the 7th resistance R7, first diode D1 and first
Capacitor C1 is connected to GND, and the collector of the first transistor Q1 is connected to supply voltage VCC, and the base stage of the first transistor Q1 is through the 4th electricity
Resistance R4 is connected to GND, and the emitter of the first transistor Q1 is connected to GND, while the emitter of the first transistor Q1 through the 5th resistance R5
The common end connection being connect with first diode D1 and first capacitor C1, the pin 1 of second Schmidt's NAND gate U2 and the 7th electricity
The common end connection that resistance R7 is connected with first diode D1, while the pin 1 of second Schmidt's NAND gate U2 is through the 11st pole
The common end connection that pipe D11 is connect with the 4th capacitor C4 and the 5th Schmidt's NAND gate U5, second Schmidt's NAND gate U2's is defeated
Outlet is connect with the pin 3 of third Schmidt's NAND gate U3, and the pin 4 of third Schmidt's NAND gate U3 connects through the tenth resistance R10
To GND, the output end of third Schmidt's NAND gate U3 is connected to the pin 2 of second Schmidt's NAND gate U2 through the 4th diode D4,
The output end of third Schmidt's NAND gate U3 is connected to GND, the 7th capacitor through the 5th diode D5 and the 24th resistance R24 simultaneously
An end of C7 is connected to the output end of the 6th Schmidt's NAND gate U6, and the another of the 7th capacitor C7 is connected to the 4th Schmidt's NAND gate
The pin 8 of U4, the pin 8 of the 4th Schmidt's NAND gate U4 through the 14th resistance R14 and thirteenth resistor R13 be connected to the 4th apply it is close
The pin 7 of special NAND gate U4, the anode of the 7th diode D7 are connected to the pin 8 of the 4th Schmidt's NAND gate U4, the 6th diode
The anode of D6 is connected to the pin 7 of the 4th Schmidt's NAND gate U4, the cathode of the 7th diode D7 and the cathode of the 6th diode D6
Be connected to supply voltage VCC, the 14th resistance R14 connected with thirteenth resistor R13 it is public be connected to supply voltage VCC,
An end of four capacitor C4 is connected to the pin 7 of the 4th Schmidt's NAND gate U4, and the another of the 4th capacitor C4 is connected to the 5th Schmidt
The output end of NAND gate U5, the pin 5 and pin 6 of the 5th Schmidt's NAND gate U5 are connected to the defeated of the 4th Schmidt's NAND gate U4
The base stage of outlet, third transistor Q3 is connected to supply voltage VCC, while the base stage of third transistor Q3 through eleventh resistor R11
Inductive primary L1 through twelfth resistor R12, third capacitor C3 and pulse transformer T1 is connected to GND, third transistor Q3
Emitter be connected to supply voltage VCC, the collector of third transistor Q3 is connected to the pin 2 of second Schmidt's NAND gate U2；
The specific work process and principle of primary fault protection memory module: under normal circumstances, the first transistor Q1 conducting,
Pressure drop on 5th resistance R5 or first capacitor C1 is approximately supply voltage VCC, and the current potential of first diode D1 cathode is approximately
Supply voltage VCC, and the current potential of first diode D1 anode is not more than supply voltage VCC, therefore first diode D1 is positive
Cut-off.Meanwhile under normal circumstances, the pressure drop end value on the second capacitor C2 is approximately close to supply voltage VCC, therefore the two or two
The cut-off of pole pipe D2 forward direction.Therefore the pressure drop on the second Schmidt NAND gate U2 pin 1 depends on the 11st diode D11 anode
Current potential, when the current potential of the 11st diode D11 anode is low level, the 11st diode D11 positive can equally end, power supply
Voltage VCC forms the pressure drop close to supply voltage VCC in the second Schmidt NAND gate U2 pin 1 after the 7th resistance R7, when
When the current potential of 11st diode D11 anode is high level, supply voltage VCC makes the 11st diode D11 through the 7th resistance R7
Forward conduction, therefore the current potential on the second Schmidt NAND gate U2 pin 1 is pulled down to low level.Current potential at lower surface analysis X2
Situation:
Assuming that the output signal U 6_OUT original state of the 6th Schmidt's NAND gate U6 is low level, when rising edge arrives
When, the end I of the 7th capacitor C7 can simultaneously form the voltage close to supply voltage VCC, but due to supply voltage VCC before this
The 14th resistance R14 is passed through to the end H for being loaded into the 7th capacitor C7, therefore the voltage at the 7th both ends capacitor C7 can reach balance
State.When failing edge arrives, the voltage at the end I of the 7th capacitor C7 is instantaneously removed, and the current potential of U6_OUT is low level, at this time
Have transient current circuit: VCC- > R14- > C7- > U6_OUT, in this process, the equivalent impedance of the 7th capacitor C7 are much smaller than
14th resistance R14, therefore approximate can ignore the impedance of the 7th capacitor C7, then the voltage almost all of supply voltage VCC
It is added on the 14th resistance R14, the current potential on the 4th Schmidt NAND gate U4 pin 8 is approximately GND low level, so the 4th applies
Close spy NAND gate U4 can export high level, and the 5th Schmidt's NAND gate U5 can export low level, and before this process, the 4th applies
Current potential on close spy's NAND gate U4 pin 8 and the 4th Schmidt NAND gate U4 pin 7 stabilizes to high level, thus the 4th apply it is close
Special NAND gate U4 exports low level, and the 5th Schmidt's NAND gate U5 exports high level, therefore before this process, the 4th capacitor C4
The voltage at both ends reaches equilibrium state, is high level, and when this process arrives, i.e. when the failing edge of U6_OUT arrives, the
Five Schmidt's NAND gate U5 can export low level, then similar to have current loop: VCC- > R13- > C4- > U5_OUT, the 4th electricity
The equivalent impedance for holding C4 is much smaller than thirteenth resistor R13, therefore approximate can ignore the impedance of the 4th capacitor C4, then power supply is electric
The voltage almost all of pressure VCC is added on thirteenth resistor R13, and the current potential on the 4th Schmidt NAND gate U4 pin 7 is approximately
GND low level.After the low level state of U6_OUT is stablized, supply voltage VCC can be respectively by the 14th resistance R14 to the 7th electricity
Hold C7 charging and charge by thirteenth resistor R13 to the 4th capacitor C4, when the end the H voltage and the 4th capacitor C4 of the 7th capacitor C7
The end J voltage when reaching approximately supply voltage VCC, charging process terminates.Charge constant τ:
τ=RC
Electricity after charging process, on the 4th Schmidt NAND gate U4 pin 8 and the 4th Schmidt NAND gate U4 pin 7
Position stabilizes to high level, and the 4th Schmidt's NAND gate U4 exports low level, and the 5th Schmidt's NAND gate U5 exports high level, this
When, it is high level that the voltage at the 4th both ends capacitor C4, which reaches equilibrium state,.Potential state and the 5th Schmidt at point X2 with
The output state of NOT gate U5 is identical.This is the change procedure of each parameter in mono- complete cycle of U6_OUT.Wherein, at point X2
Potential change is as shown in Figure 5.
Low and high level of the current potential on the one hand with the 4th diode D4 output on second Schmidt NAND gate U2 pin 2 has
It closes, while related with the current potential at point X1.Current potential situation at analysis site X1 below:
Set between the emitter and base stage of third transistor Q3 that PN junction pressure drop is 0.7V, eleventh resistor R11 and the tenth
There is following relationship between two resistance R12:
Known by Fig. 3, eleventh resistor R11, twelfth resistor R12, third capacitor C3, third transistor Q3 and the 6th resistance
R6 constitutes capacitive coupling common-base amplification circuit, and analyzes the B terminal potential of pulse transformer T1 primary coil L1 in front
Relationship between U6_OUT, as shown in Figure 5.Assuming that the original state of TI_L1 is before rising edge arrives, then third at this time
The L terminal potential of capacitor C3 can be stablized to be ended in approximate supply voltage VCC, third transistor Q3, the current potential quilt on the 6th resistance R6
It is pulled down to GND low level；When the rising edge of TI_L1 arrives, the voltage at the both ends third capacitor C3 can reach equilibrium state, third
Capacitor C3 can consider that no electric current flows through；When the failing edge of TI_L1 arrives, current loop is had: VCC- > R11- > R12- >
C3- > T1_L1- > GND, since in the process, the equivalent impedance of third capacitor C3 is much smaller than eleventh resistor R11 or the 12nd
Resistance R12, therefore the voltage almost all of supply voltage VCC is divided by eleventh resistor R11 and twelfth resistor R12, then the
The voltage of three transistor Q3 base stages:
At this point, the voltage difference between the emitter and base stage of third transistor Q3 is 1.7V, it is greater than PN junction pressure drop 0.7V, because
This third transistor Q3 is connected, and the current potential on the 6th resistance R6 is become the high level of approximate supply voltage VCC from low level.Together
When, supply voltage VCC charges through eleventh resistor R11 and twelfth resistor R12 to third capacitor C3, after charging process,
The end the L voltage of third capacitor C3 is close to supply voltage VCC, and third transistor Q3 ends again at this time, on the 6th resistance R6
Current potential returns to low level by high level.This is the change procedure of each parameter in mono- complete cycle of U6_OUT.Wherein, at point X1
Potential change it is as shown in Figure 5.
According to the analysis of front it is found that in positive row situation, the current potential situation of the second Schmidt NAND gate U2 pin 1 depends on
In with the current potential at X2, and the current potential of the second Schmidt NAND gate U2 pin 2 depend on X1 at current potential, known according to Fig. 5, second
Current potential low and high level on Schmidt NAND gate U2 pin 1 and pin 2 is complementary, therefore the high electricity of second Schmidt's NAND gate U2 output
It is flat, and known according to primary source VCC under-voltage protective module, the current potential on third Schmidt NAND gate U3 pin 4 is high level, because
This third Schmidt's NAND gate U3 exports low level, and the 4th diode D4 and the 5th diode D5 forward direction are ended, and the 24th
Voltage on resistance R24 is pulled down to GND low level.
Trigger two kinds of situations of primary fault protection memory module: (1) primary source voltage VCC occurs under-voltage；(2) secondary
Fault secure circuit feeds back failure to primary.The first situation is analyzed first, and primary source voltage VCC occurs under-voltage:
When primary source voltage VCC occurs under-voltage, known according to the analysis of front, third Schmidt NAND gate U3 pin 4
On current potential occur from high level becoming low level, then third Schmidt's NAND gate U3 can export high level, the 4th diode
D4 and the 5th equal forward conduction of diode D5, the voltage on the 24th resistance R24 are equivalent to high level, and the current potential of A point is by height
Level becomes low level, is known according to the analysis that pwm signal inputs protective module, the output U6_OUT of the 6th Schmidt's NAND gate U6
Perseverance is high level, and third transistor Q3 ends always at this time, and the current potential at X1 depends on the conducting situation of the 4th diode D4, by
It is connected in the 4th diode D4, therefore current potential X1 at is high level, and simultaneously because current potential perseverance at point X2 is high level, because
The permanent pin 1 of this second Schmidt NAND gate U2 is high level, then second Schmidt's NAND gate U2 exports low level, in this way meeting
Third Schmidt's NAND gate U3 is further set to export high level, even if primary source voltage VCC under-voltage situation terminates at this time, the
The level of three Schmidt NAND gate U3 pins 4 becomes high level again, and process above still will do it, and the current potential perseverance of A point is low
Level.Above-mentioned working mechanism realizes error protection memory primary source voltage VCC occurred under undervoltage condition.
Secondary fail protection circuit is analyzed again by failure feedback to primary situation: when secondary circuit system jam
When, a forward voltage pulse is had at point X3, it, can be in pulse transformer according to the relationship between pulse transformer T1 Same Name of Ends
There is a negative voltage pulse in the end B of T1 primary coil L1, and the negative voltage pulse can be such that third transistor Q3 is connected, from
And a high level pulse is formed on the 6th resistance R6, it is assumed that the duration of the high level pulse is Δ t, this high level
Pulse can be such that the relationship of the low and high level complementation between the pin 1 and pin 2 of second Schmidt's NAND gate U2 terminates, second apply it is close
Will appear between the pin 1 and pin 2 of special NAND gate U2 while the case where for high level, at the same for the duration of high level by
The duration of Δ t of the upper high level pulse of R6 is determined.Within this Δ t time, second Schmidt's NAND gate U2 exports low level,
Third Schmidt's NAND gate U3 exports high level, the 4th diode D4 and the 5th equal forward conduction of diode D5, the 24th electricity
Voltage on resistance R24 is equivalent to high level, and the current potential of A point becomes low level from high level, inputs protective module according to pwm signal
Analysis know that the output U6_OUT perseverance of the 6th Schmidt's NAND gate U6 is high level, since the 4th diode D4 is connected, X1
The current potential at place is high level, and simultaneously because current potential perseverance at point X2 is high level, therefore second Schmidt's NAND gate U2 draws
Permanent foot 1 is high level, then second Schmidt's NAND gate U2 output low level, can further make third Schmidt's NAND gate in this way
U3 exports high level, even if secondary circuit system jam situation terminates at this time, the end B of pulse transformer T1 primary coil L1
There is a negative voltage pulse to disappear, third transistor Q3 can be height by the output U6_OUT perseverance of the 6th Schmidt's NAND gate U6
Level and end, but process above still will do it, and the current potential perseverance of A point is low level.Above-mentioned working mechanism realizes to secondary
Error protection memory when circuit system breaks down.
One primary fault reseting module, including reset signal RESET, first resistor R1, the first schmitt inverter U1,
4th resistance R4, the first transistor Q1, supply voltage VCC, the 5th resistance R5, first capacitor C1, the 7th resistance R7, the one or two pole
Pipe D1, main function be when primary error protection memory module because occur supply voltage VCC it is under-voltage or it is secondary break down when meeting
Triggering primary fault protection memory module simultaneously generates the error signal permanently latched, forms memory, after circuit system trouble shooting,
Reset signal RESET is inputted by the primary fault reseting module to unlock the mistake letter that primary fault protects memory module to latch
Number, and memory signal is removed, thus the normal operation of restoring circuit system；Wherein, reset signal RESET is connected to the first Schmidt
The input terminal of phase inverter U1, while the input terminal of the first schmitt inverter U1 is connected to GND, the first Schmidt through first resistor R1
The output of phase inverter U1 is connected to the base stage of the first transistor Q1, while the output end of the first schmitt inverter U1 is through the 4th electricity
Resistance R4 is connected to GND, and the collector of the first transistor Q1 is connected to supply voltage VCC, while the collector of the first transistor Q1 is through the
Seven resistance R7 are connected to the anode of first diode D1, and the cathode of first diode D1 is connected to GND, first crystal through first capacitor C1
The emitter of pipe Q1 is connected to GND, while the cathode of the emitter of the first transistor Q1 and first diode D1 through the 5th resistance R5
Connection；
The specific work process and principle of primary fault reseting module: the 5th resistance R5 of setting is far smaller than the 7th resistance
R7, according to front primary fault protect memory module analysis know, trigger primary fault protection memory module when, second apply it is close
Can have high level on the pin 1 and pin 2 of special NAND gate U2 jointly always just makes the failure occurred always by " memory is protected
Shield ", then after the fault condition of generation releases, if original RESET signal to be become inputting the height of Δ T time from low level
Level signal, then first Schmidt's NAND gate can export the low level signal of Δ T time, in Δ T time, the first transistor
Q1 can be become ending from conducting, have current path: VCC- > R7- > D1- > R5- > GND, since the 5th resistance R5 is far smaller than
Seven resistance R7, therefore the current potential of first diode D1 anode can be approximately zero, i.e. electricity on the second Schmidt NAND gate U2 pin 1
Position is low level, then second Schmidt's NAND gate U2 exports high level, due on third Schmidt NAND gate U3 pin 4 at this time
Current potential be high level, therefore third Schmidt's NAND gate U3 exports low level, and the current potential of the 24th resistance R24 is pulled down to
The current potential of GND low level, A point becomes high level from low level, relieves the block to PWM input signal at this time, the 6th apply it is close
The output U6_OUT of special NAND gate U6 restores normal, and the low and high level of realization again at point X1 and point X2 is complementary, when Δ T time knot
Shu Hou, the second Schmidt NAND gate U2 pin 1 and pin 2 realize low and high level complementation again, to realize to primary fault
Protect the unlock of memory module, the normal operation of restoring circuit system.
One primary ERROR signal exports logic level selecting module, including the 7th schmitt inverter U7, the 8th apply it is close
Special phase inverter U8, supply voltage VCC, 3rd resistor R3, second resistance R2, the 22nd resistance R22, the 17th resistance R17,
Four transistor Q4, the 18th resistance R18, the 9th diode D9, the tenth diode D10, the 21st resistance R21, the 19th electricity
Resistance R19, the 20th resistance R20, first choice switch S1, the 9th comparator U9 and fault output signal ERROR, main function are
When the logic level, i.e. selectable circuit system jam of fault output signal ERROR may be selected, fault output signal
ERROR is high level or low level, improves circuit system applicability；Wherein, the input of the 7th schmitt inverter U7 is connected to
The cathode of 5th diode D5, the output end of the 7th schmitt inverter U7 and the input terminal of the 8th schmitt inverter U8 connect
It connects, the output end of the 8th schmitt inverter U8 is connected to the pin 1 of the 9th comparator U9, power supply electricity through the 22nd resistance R22
Pressure VCC is connected to the output end of the 8th schmitt inverter U8 through 3rd resistor R3, at the same supply voltage VCC through 3rd resistor R3 and
What second resistance R2 was connected to that GND, 3rd resistor R3 and second resistance R2 connect public is connected to the 8th schmitt inverter U8's
The output end of output end, the collector of the 4th transistor Q4 are connected to the output end of the 8th schmitt inverter U8, the 4th transistor
The emitter of Q4 is connected to the pin 2 of the 9th comparator U9, and supply voltage VCC connects through the 20th resistance R20 and the 19th resistance R19
To GND, the public emitter for being connected to the 4th transistor Q4 of the 20th resistance R20 and the 19th resistance R19 connection, the 4th is brilliant
The base stage of body pipe Q4 is connected to GND through the 17th resistance R17, while the base stage of the 4th transistor Q4 is connected to through the 18th resistance R18
The anode of the cathode of 9th diode D9, the 9th diode D9 is connect with the anode of the tenth diode D10, meanwhile, the 9th 2 pole
The anode of pipe D9 is connected to supply voltage VCC through first choice switch S1, and the anode of the tenth diode D10 is through the 21st resistance
R21 is connected to the output end of the 9th comparator U9, and the output end of the 9th comparator U9 exports fault output signal ERROR；
The specific work process and principle of primary ERROR signal output logic level selecting module: setting second resistance R2,
Exist between 3rd resistor R3, the 17th resistance R17, the 18th resistance R18, the 19th resistance R19 and the 20th resistance R20 and closes
System:
When first choice switch S1 is disconnected, under normal circumstances, the current potential of A point is high level, the 8th schmitt inverter
U8 exports low level, the current potential of the 9th comparator U9 pin 1:
The current potential of 9th comparator U9 pin 2:
Therefore the output signal ERROR of the 9th comparator U9 is low level.
When a failure occurs it, the current potential of A point is low level, and the 8th schmitt inverter U8 exports high level, and the 9th compares
The current potential of device U9 pin 1:
The current potential of 9th comparator U9 pin 2:
Therefore the output signal ERROR of the 9th comparator U9 is high level.
When first choice switch S1 closure, supply voltage VCC is by first choice switch S1, the tenth diode D10, the
The output end of 21 resistance R21 to the 9th comparator U9, therefore output signal ERROR is equivalent to and has added pull-up resistor.
4th transistor Q4 base voltage are as follows:
4th transistor Q4 emitter voltage are as follows:
Therefore, the 4th transistor Q4 is connected.
Under normal circumstances, the current potential of the 9th comparator U9 pin 1:
And because the 4th transistor Q4 is connected, the current potential of the 9th comparator U9 pin 2 is approximately equal to the 8th Schmidt
The output level of phase inverter U8, and the low level of the 8th schmitt inverter U8 output at this time, therefore the 9th comparator U9 pin 1
Current potential is greater than the current potential of the 9th comparator U9 pin 2, therefore the output signal ERROR of the 9th comparator U9 is high level.
Under fault condition, the 8th schmitt inverter U8 exports high level, therefore the electricity of the 9th comparator U9 pin 2 at this time
Position is approximately equal to supply voltage VCC, the current potential of the 9th comparator U9 pin 1:
Therefore, the current potential of the 9th comparator U9 pin 1 is less than the current potential of the 9th comparator U9 pin 2, therefore the 9th compares
The output signal ERROR of device U9 is low level.
When according to analytic process above it is found that realizing circuit system and break down, fault output signal ERROR is height
Level or low level purpose.
One temporary source energy supply module 7, by the second capacitor C2, the 7th resistance R7, the second diode D2 and third
Diode D3 is constituted, wherein supply voltage VCC is connected to the anode of the second diode D2, the second diode D2 through the 7th resistance R7
Cathode be connected to the positive ends of the second capacitor C2, the negative polarity of the second capacitor C2 is connected to GND, while the second capacitor C2 is just
Polarity is connected to the anode of third diode D3, and the cathode of third diode D3 is connected to supply voltage VCC, which is mainly used for
In the case where supply voltage VCC instantaneous voltage sag occurs or interrupts, the electric energy being stored in the second capacitor C2 passes through third
Diode D3 provides a system to temporary source voltage, and in the normal situation of supply voltage VCC, and supply voltage VCC passes through the
Seven resistance R7 and the second diode D2 charge to the second capacitor C2, numerical value of the charging voltage end value close to supply voltage VCC；
One secondary fail protects circuit, by the 25th resistance R25, pulse transformer T1, third capacitor C3, the 12nd
Resistance R12, eleventh resistor R11, third transistor Q3, the 6th resistance R6 and the tenth resistance R10 are constituted, wherein the 25th electricity
An end of resistance R25 is connected to HGND, and the other end of the 25th resistance R25 is connected to through the secondary coil L2 of pulse transformer T1
One end of HGND, third capacitor C3 are connected to GND through the primary coil L1 of pulse transformer T1, and the other end of third capacitor C3 is through
12 resistance R12 and eleventh resistor R11 are connected to supply voltage VCC, and the emitter of third transistor Q3 is connected to supply voltage
VCC, the base stage of third transistor Q3 are connected to the common end that twelfth resistor R12 is connected with eleventh resistor R11, third transistor
The collector of Q3 is connected to GND through the tenth resistance R10, which can be by secondary fail pulse X3 on the 25th resistance R25
The pressure drop of formation is coupled to primary through pulse transformer T1, then can be formed on the side the L1 inductance coil of pulse transformer T1
Rp pulse, this pulse is using by eleventh resistor R11, twelfth resistor R12, third capacitor C3 and third transistor Q3 structure
At capacitive coupling common-base amplification circuit after, Q3 is connected instantaneously, thus on the 6th resistance generate a high level pulse,
It triggers primary fault and protects memory module, and logic level selecting module is exported by primary ERROR signal and exports ERROR letter
Number.
The specific work process and principle of secondary fail protection circuit: when secondary circuit system jam, at point X3
A forward voltage pulse is had, it, can be in pulse transformer T1 primary line according to the relationship between pulse transformer T1 Same Name of Ends
There is a negative voltage pulse in the end B for enclosing L1, and the negative voltage pulse can be such that third transistor Q3 is connected, thus the 6th
A high level pulse is formed on resistance R6, to trigger primary fault protection memory module.
The isolated variable process of pwm signal is as follows: the pwm signal of input initially enters pwm signal input protective module, just
In normal situation, A point is high level current potential, and the pwm signal of input enters subsequent module after reverse phase, if circuit system
It breaks down, A point becomes low level current potential, and the module can block pwm pulse to transmit to secondary at this time, avoids making to circuit system
At secondary damage；Then into primary pwm signal isolated variable circuit, the module is in pairs by the transformation modulation of PWM input signal
To pulse, then through pulse transformer T1 isolation coupling to secondary；It is coupled to secondary bidirectional pulse and enters back into secondary pwm signal also
Former reconfigurable circuit, the circuit are reduced to original pwm signal by way of signal reconstruction, finally the module output pwm signal
HPWM.It is under-voltage in case of supply voltage or secondary circuit breaks down during pwm signal transmitting, secondary fail letter
Number by secondary fail protection circuit enter primary circuit, can all trigger primary fault protection memory module, the module can will
The fault-signal of generation permanently latches, and forms memory, in the presence of simultaneous faults signal, pwm signal is blocked to transmit to secondary, prevented
Secondary hazards only are caused to system, which is continued until trouble shooting and by primary fault reseting module or power cutoff
The error signal that voltage VCC releases latches and removes memory, and such protection mechanism is realized to the reliably protecting of circuit system, prevents
Because failure it is not adequately addressed in the case where, so that circuit system is worked again, to circuit system cause repeat damage.Meanwhile circuit
After system jam, the ERROR signal of primary ERROR signal output logic level selecting module output generates level jump,
The level that the module can choose output ERROR signal is high level or low level, to improve the applicability of circuit.
Claims (3)
1. a kind of pwm signal isolated variable system based on pulse transformer, which is characterized in that including an offer operating voltage
Power supply, pwm signal input protective module, a primary pwm signal isolated variable module, a grade pwm signal reduction reconstruct
Module, a primary source VCC under-voltage protective module, a primary fault protective module, a primary ERROR signal output module；
Pwm signal input protective module receives PWM input signal, if circuit system breaks down, block pwm pulse to
Secondary transmitting；
The primary pwm signal isolated variable module is used to PWM input signal transformation being modulated into bidirectional pulse；
The secondary pwm signal reduction reconstructed module is of coupled connections with primary pwm signal isolated variable module, to time after coupling
Grade bidirectional pulse is reduced to and the HPWM signal of original PWM input signal same-phase by way of signal reconstruction；
The primary source under-voltage protective module is used to provide supply voltage under-voltage protection to circuit system, if supply voltage occurs
When under-voltage, line under-voltage signal is issued；
The primary fault protective module is used to receive line under-voltage signal or secondary pwm signal restores reconstructed module
When failure, pwm signal is blocked to transmit to secondary；If line under-voltage signal or secondary pwm signal reduction reconstructed module break down
It releases, generates reset signal, circuit works normally；
The primary ERROR signal output module is defeated when line under-voltage or secondary pwm signal reduction reconstructed module break down
Malfunction error signal；
Pwm signal input protective module by supply voltage (VCC), the 16th resistance (R16), the 6th Schmidt's NAND gate (U6),
8th capacitor (C8) and the 8th diode (D8) composition；Wherein, PWM input signal is connected to drawing for the 6th Schmidt's NAND gate (U6)
Foot 10, supply voltage (VCC) are connected to GND, the 6th Schmidt's NAND gate (U6) through the 16th resistance (R16) and the 8th capacitor (C8)
Pin 9 be connected to the common end of the 16th resistance (R16) and the connection of the 8th capacitor (C8), while the 6th Schmidt's NAND gate (U6)
Pin 9 be connected with the anode of the 8th diode (D8)；
Primary pwm signal isolated variable module includes the 15th resistance (R15), the 6th capacitor (C6), the 5th capacitor (C5), pulse
Transformer (T1) and the 25th resistance (R25)；Wherein, an end of the 15th resistance (R15) is connected to the 6th Schmidt's NAND gate
(U6) output end, inductive primary of the other end through the 6th capacitor (C6), the 5th capacitor (C5) and pulse transformer (T1)
(L1) it is connected to GND, an end of the 25th resistance (R25) is connected to HGND, secondary inductance of the other end through pulse transformer (T1)
Coil (L2) is connected to HGND；
Secondary pwm signal reduction reconstructed module includes the 24th resistance (R24), the 13rd diode (D13), the 12nd pole
Manage (D12), the 23rd resistance (R23), the 11st schmitt inverter (U11) and the tenth schmitt inverter (U10)；Its
In, the anode of the 13rd diode (D13) is connected to HGND, and the cathode of the 13rd diode (D13) is through the 24th resistance (R24)
It is connected to the common end that the 25th resistance (R25) is connect with the inductive secondary (L2) of pulse transformer (T1), while the tenth
The cathode of three diodes (D13) is connected to the input terminal of the 11st schmitt inverter (U11), the 11st schmitt inverter
(U11) output end is connected to through the tenth schmitt inverter (U10), the 23rd resistance (R23) and the 12nd diode (D12)
The input terminal of 11st schmitt inverter (U11) itself, while the output end of the tenth schmitt inverter (U10) exports and passes through
HPWM signal after reduction；
Primary source (VCC) under-voltage protective module includes supply voltage (VCC), the 8th resistance (R8), the 9th resistance (R9), first
Zener diode (ZD1), second transistor (Q2), the tenth resistance (R10) and third Schmidt NAND gate (U3)；Wherein, power supply
Voltage (VCC) is connected to GND through the 8th resistance (R8), the 9th resistance (R9) and the first zener diode (ZD1), second transistor
(Q2) emitter is connected to supply voltage (VCC), the base stage of second transistor (Q2) and the 8th resistance (R8) and the 9th resistance
(R9) the common end connection connected, the collector of second transistor (Q2) are connected to GND, third Schmidt through the tenth resistance (R10)
The pin 4 of NAND gate (U3) is connected to the collector of second transistor (Q2)；
Primary fault protective module includes supply voltage (VCC), the first transistor (Q1), the 4th resistance (R4), the 5th resistance
(R5), first capacitor (C1), first diode (D1), the 6th resistance (R6), the 7th resistance (R7), the 11st diode (D11),
4th diode (D4), the 5th diode (D5), second Schmidt's NAND gate (U2), third Schmidt NAND gate (U3), second
14 resistance (R24), the tenth resistance (R10), the 7th capacitor (C7), the 14th resistance (R14), thirteenth resistor (R13), the 6th
Diode (D6), the 7th diode (D7), the 4th capacitor (C4), the 4th Schmidt's NAND gate (U4), the 5th Schmidt's NAND gate
(U5), eleventh resistor (R11), twelfth resistor (R12), third capacitor (C3) and third transistor (Q3)；Wherein, power supply electricity
(VCC) is pressed to be connected to GND, the collection of the first transistor (Q1) through the 7th resistance (R7), first diode (D1) and first capacitor (C1)
Electrode is connected to supply voltage (VCC), and the base stage of the first transistor (Q1) is connected to GND through the 4th resistance (R4), the first transistor
(Q1) emitter is connected to GND, while the emitter of the first transistor (Q1) and first diode (D1) through the 5th resistance (R5)
With the common end connection of first capacitor (C1) connection, the pin 1 of second Schmidt's NAND gate (U2) and the 7th resistance (R7) and the
The common end connection of one diode (D1) connection, while the pin 1 of second Schmidt's NAND gate (U2) is through the 11st diode
(D11) the common end connection being connect with the 4th capacitor (C4) and the 5th Schmidt's NAND gate (U5), second Schmidt's NAND gate
(U2) output end is connect with the pin 3 of third Schmidt NAND gate (U3), and the pin 4 of third Schmidt NAND gate (U3) is through
Ten resistance (R10) are connected to GND, and the output end of third Schmidt NAND gate (U3) is connected to the second Schmidt through the 4th diode (D4)
The pin 2 of NAND gate (U2), while the output end of third Schmidt NAND gate (U3) is through the 5th diode (D5) and the 24th
Resistance (R24) is connected to GND, and an end of the 7th capacitor (C7) is connected to the output end of the 6th Schmidt's NAND gate (U6), the 7th capacitor
(C7) another pin 8 for being connected to the 4th Schmidt's NAND gate (U4), the pin 8 of the 4th Schmidt's NAND gate (U4) is through the tenth
Four resistance (R14) and thirteenth resistor (R13) are connected to the pin 7 of the 4th Schmidt's NAND gate (U4), the 7th diode (D7)
Anode is connected to the pin 8 of the 4th Schmidt's NAND gate (U4), and the anode of the 6th diode (D6) is connected to the 4th Schmidt's NAND gate
(U4) pin 7, the cathode of the 7th diode (D7) and the cathode of the 6th diode (D6) are connected to supply voltage (VCC), the
Public being connected to supply voltage (VCC) of 14 resistance (R14) and thirteenth resistor (R13) connection, the one of the 4th capacitor (C4)
It is connected to the pin 7 of the 4th Schmidt's NAND gate (U4), the 4th the another of capacitor (C4) is connected to the 5th Schmidt's NAND gate
(U5) output end, the pin 5 and pin 6 of the 5th Schmidt's NAND gate (U5) are connected to the defeated of the 4th Schmidt's NAND gate (U4)
The base stage of outlet, third transistor (Q3) is connected to supply voltage (VCC) through eleventh resistor (R11), while third transistor
(Q3) base stage connects through the inductive primary (L1) of twelfth resistor (R12), third capacitor (C3) and pulse transformer (T1)
To GND, the emitter of third transistor (Q3) is connected to supply voltage (VCC), and the collector of third transistor (Q3) is connected to second
The pin 2 of Schmidt's NAND gate (U2)；
Primary ERROR signal output module includes the 7th schmitt inverter (U7), the 8th schmitt inverter (U8), power supply electricity
Press (VCC), 3rd resistor (R3), second resistance (R2), the 22nd resistance (R22), the 17th resistance (R17), the 4th crystal
Manage (Q4), the 18th resistance (R18), the 9th diode (D9), the tenth diode (D10), the 21st resistance (R21), the tenth
Nine resistance (R19), the 20th resistance (R20), first choice switch (S1), the 9th comparator (U9) and fault output signal
ERROR；Wherein, the input of the 7th schmitt inverter (U7) is connected to the cathode of the 5th diode (D5), and the 7th Schmidt is anti-
The output end of phase device (U7) is connect with the input terminal of the cathode of the 8th diode (D8), the 8th schmitt inverter (U8) respectively,
The output end of 8th schmitt inverter (U8) is connected to the pin 1 of the 9th comparator (U9), power supply through the 22nd resistance (R22)
Voltage (VCC) is connected to the output end of the 8th schmitt inverter (U8) through 3rd resistor (R3), while supply voltage (VCC) is through
Three resistance (R3) and second resistance (R2) are connected to GND, and the public of 3rd resistor (R3) and second resistance (R2) connection is connected to the
The collector of the output end of the output end of eight schmitt inverters (U8), the 4th transistor (Q4) is connected to the 8th schmitt inverter
(U8) output end, the emitter of the 4th transistor (Q4) are connected to the pin 2 of the 9th comparator (U9), supply voltage (VCC) warp
20th resistance (R20) and the 19th resistance (R19) are connected to GND, the 20th resistance (R20) and the connection of the 19th resistance (R19)
The public emitter for being connected to the 4th transistor (Q4), the base stage of the 4th transistor (Q4) is connected to through the 17th resistance (R17)
GND, while the base stage of the 4th transistor (Q4) is connected to the cathode of the 9th diode (D9) through the 18th resistance (R18), the 9th 2
The anode of pole pipe (D9) is connect with the anode of the tenth diode (D10), meanwhile, the anode of the 9th diode (D9) is through first choice
Switch (S1) is connected to supply voltage (VCC), and the cathode of the tenth diode (D10) is connected to the 9th ratio through the 21st resistance (R21)
Compared with the output end of device (U9), the output end of the 9th comparator (U9) exports fault output signal ERROR.
2. system according to claim 1, which is characterized in that the system further includes temporary source energy supply module, is used
Temporary source voltage is provided when line under-voltage, and the module charges to the numerical value of supply voltage when supply voltage is normal；
Temporary source energy supply module is by the second capacitor (C2), the 7th resistance (R7), the second diode (D2) and the three or two pole
(D3) is managed to constitute；Wherein, supply voltage (VCC) is connected to the anode of the second diode (D2), the two or two pole through the 7th resistance (R7)
The cathode of pipe (D2) is connected to the positive ends of the second capacitor (C2), and the negative polarity of the second capacitor (C2) is connected to GND, while second
The positive ends of capacitor (C2) are connected to the anode of third diode (D3), and the cathode of third diode (D3) is connected to supply voltage
(VCC), which is mainly used for being stored in second in the case where supply voltage (VCC) instantaneous voltage sag occurs or interrupts
Electric energy in capacitor (C2) provides a system to temporary source voltage by third diode (D3), and supply voltage (VCC) just
In the case where often, supply voltage (VCC) is charged by the 7th resistance (R7) and the second diode (D2) to the second capacitor (C2), is filled
Numerical value of the piezoelectric voltage end value close to supply voltage (VCC).
3. system according to claim 1, which is characterized in that the system further includes secondary fail protective module, for working as
When secondary pwm signal reduction reconstructed module breaks down, generates fault-signal and trigger primary fault protective module；
Secondary fail protective module is by the 25th resistance (R25), pulse transformer (T1), third capacitor (C3), the 12nd electricity
Hinder (R12), eleventh resistor (R11), third transistor (Q3), the 6th resistance (R6) composition；Wherein the 25th resistance (R25)
An end be connected to HGND, secondary coil (L2) of the other end of the 25th resistance (R25) through pulse transformer (T1) is connected to
HGND, primary coil (L1) of the one end of third capacitor (C3) through pulse transformer (T1) are connected to GND, third capacitor (C3) it is another
One end is connected to supply voltage (VCC) through twelfth resistor (R12) and eleventh resistor (R11), the transmitting of third transistor (Q3)
Pole is connected to supply voltage (VCC), and the base stage of third transistor (Q3) is connected to twelfth resistor (R12) and eleventh resistor (R11)
The collector of the common end of connection, third transistor (Q3) is connected to GND through the 6th resistance (R6), and the module is by secondary fail pulse
The pressure drop that X3 is formed on the 25th resistance (R25) is coupled to primary through pulse transformer (T1), then can be in pulse transforming
Rp pulse is formed in the inductive primary (L1) of device (T1), this pulse is using by eleventh resistor (R11), the 12nd electricity
After the capacitive coupling common-base amplification circuit for hindering (R12), third capacitor (C3) and third transistor (Q3) composition, keep (Q3) instantaneous
Conducting, to generate a high level pulse on the 6th resistance, triggering primary fault protects memory module, and passes through primary
ERROR signal exports logic level selecting module and exports ERROR signal.
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| CN201510772818.XA CN105262056B (en) | 2015-11-12 | 2015-11-12 | A kind of pwm signal isolated variable system based on pulse transformer |
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| CN201510772818.XA CN105262056B (en) | 2015-11-12 | 2015-11-12 | A kind of pwm signal isolated variable system based on pulse transformer |
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| CN105262056B true CN105262056B (en) | 2019-01-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103546020A (en) * | 2013-10-28 | 2014-01-29 | 北京京铁信达铁路设备有限公司 | High-voltage IGBT driving and protecting circuit |
| CN203562766U (en) * | 2013-10-10 | 2014-04-23 | 济南沃尔电子有限公司 | Over-voltage and under-voltage protection circuit |
| CN103916011A (en) * | 2012-12-31 | 2014-07-09 | 乐金显示有限公司 | Power Supplying Apparatus And Display Apparatus Including The Same |
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2015
- 2015-11-12 CN CN201510772818.XA patent/CN105262056B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103916011A (en) * | 2012-12-31 | 2014-07-09 | 乐金显示有限公司 | Power Supplying Apparatus And Display Apparatus Including The Same |
| CN203562766U (en) * | 2013-10-10 | 2014-04-23 | 济南沃尔电子有限公司 | Over-voltage and under-voltage protection circuit |
| CN103546020A (en) * | 2013-10-28 | 2014-01-29 | 北京京铁信达铁路设备有限公司 | High-voltage IGBT driving and protecting circuit |
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Address after: 222061 No.18, Shenghu Road, Lianyungang City, Jiangsu Province Patentee after: The 716th Research Institute of China Shipbuilding Corp. Patentee after: China Shipbuilding Digital Information Technology Co.,Ltd. Address before: 222061 No.18, Shenghu Road, Lianyungang City, Jiangsu Province Patentee before: The 716th Research Institute of China Shipbuilding Corp. Patentee before: CSIC Information Technology Co.,Ltd. |