CN105259840A - Two-circuit board parallel communication system and method - Google Patents
Two-circuit board parallel communication system and method Download PDFInfo
- Publication number
- CN105259840A CN105259840A CN201510737575.6A CN201510737575A CN105259840A CN 105259840 A CN105259840 A CN 105259840A CN 201510737575 A CN201510737575 A CN 201510737575A CN 105259840 A CN105259840 A CN 105259840A
- Authority
- CN
- China
- Prior art keywords
- pwm1g
- circuit board
- circuit boards
- parallel communication
- pieces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25179—Parallel
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention relates to a two-circuit board parallel communication system and a method, in particular to a two-circuit board communication system using the simple parallel bus communication technology. The parallel communication system comprises two circuit boards which are mutually connected via a data bus and an address bus. One of the circuit boards is a main control board and the other is a slave unit. The main control board controls data read and write between the circuit boards. According to the invention, technical problems of low communication efficiency and real-time performance of a traditional serial communication method are solved. With the parallel communication method, high-speed data exchange between the circuit boards is achieved; a complex parallel communication protocol will not be used; occupied CPU resources are less; and the circuit boards are simple to maintain.
Description
Technical field
The present invention relates to a kind of two circuit board parallel communication system and methods, be specifically related to a kind of two circuit board communication systems adopting the simple parallel bus communication technology.
Background technology
Urban track traffic is the backbone of urban public transport, the main artery that passenger flow is transported, and is the lifeline engineering in city.Along with recent year rapid economic development, urban rail transit in China construction enters prosperity and development periods, and becomes track traffic market maximum in the world.
Along with the develop rapidly of Power Electronic Technique and computer technology, track traffic trailer system adopts AC Drive to become main flow.In alternating-current actuating system, the configuration mode of inverter and traction electric machine mainly contains 1C4M (1 Driven by inverter, 4 traction electric machines), 2 × 1C2M (1 Driven by inverter, 2 traction electric machines), 4 × 1C1M (1 Driven by inverter, 1 traction electric machine) Three models.Transmission for 2 × 1C2M form configures; the control circuit board of 2 inverters needs the information such as shared traction control instruction, logical sequence, network communication interface, Fault Identification and protection; a large amount of information is had to need between two blocks of control circuit plates mutual; and along with the raising that user requires trailer system; need mutual data volume also will increase between control circuit board; the real-time of data interaction also will improve, and traditional serial communication mode can not meet the demands.
Summary of the invention
The object of this invention is to provide a kind of two circuit board parallel communication systems, solve that traditional serial communication mode communication efficiency is low, the technical matters of poor real.
Technical solution of the present invention is: the two circuit board parallel communication systems provided, and comprise two pieces of circuit boards, its special character is: two pieces of circuit boards realize interconnection by data bus and address bus; One of them circuit board is master control board, and another circuit board is from equipment; Master control board controls the reading and writing data between two circuit boards.
The present invention also provides a kind of two circuit board parallel communication methods, and its special character is: comprise the following steps:
1] two pieces of circuit board PWM1G and PWM2G are realized interconnection by 16 bit data bus and 16 bit address buses;
2] arranging PWM1G is master control board, controls the reading and writing data between two pieces of circuit boards; Arranging PWM2G is from equipment;
3] data write:
3.1] write control signal is set to effectively by PWM1G;
3.2] PWM1G is to the two-port RAM write data being positioned at PWM2G inside;
3.3] PWM1G write control signal is set to invalid;
4] digital independent:
4.1] read control signal is set to effectively by PWM1G;
4.2] PWM1G reads data from the two-port RAM being positioned at PWM2G inside;
4.3] PWM1G read control signal is set to invalid;
Beneficial effect of the present invention:
(1) the present invention adopts parallel bus communication mode, and the high-speed data achieved between two pieces of control panels exchanges, and avoid adopting complicated parallel bus communication protocol, take cpu resource few, circuit board is safeguarded simple.
(2) the present invention adopts two-port RAM to control the buffer memory of communication between plates as two pieces, avoids the synchronous process in communication system, improves stability and the reliability of the communication information.
(3) invention adopts simple parallel bus communication mode, and all adopts fpga chip to realize, and avoids communication protocol and the hardware circuits such as exploitation USB or PCI, reduces design of hardware and software complexity.
Accompanying drawing explanation
Fig. 1 is the system chart of present pre-ferred embodiments.
Embodiment
See Fig. 1, present pre-ferred embodiments is made up of two pieces of circuit board PWM1G and PWM2G, and two pieces of circuit boards realize interconnection by 16 bit data bus and 16 bit address buses.Wherein, PWM1G is master control board, and PWM2G is from equipment.Master control board can control write control signal and read control signal, and write control signal and read control signal can not effectively simultaneously.
The mode that PWM1G writes data to PWM2G is: it is effective that PWM1G controls write control signal, and now PWM1G has 16 bit address buses, 16 bit data bus, and PWM1G is to PWM2G inner dual-port write data.After PWM1G data write operation completes, it is invalid that PWM1G controls write control signal.
The mode that PWM1G reads data from PWM2G is: it is effective that PWM1G controls read control signal, and now PWM2G has 16 bit address buses, 16 is data bus, and PWM1G reads data from the inner dual-port of PWM2G.After PWM1G read operation completes, it is invalid that PWM1G controls read control signal.
Further, two pieces of circuit boards of the present invention are also connected to each other by a two-port RAM.PWM2G safeguards dual port RAM data, reads the data that PWM1G upgrades in time, meanwhile, in time to two-port RAM refresh data, reads for PWM1G.
Claims (5)
1. two circuit board parallel communication systems, comprise two pieces of circuit boards, it is characterized in that: two pieces of circuit boards realize interconnection by data bus and address bus; One of them circuit board is master control board, and another circuit board is from equipment; Master control board controls the reading and writing data between two circuit boards.
2. two circuit board parallel communication systems according to claim 1, is characterized in that: also comprise a two-port RAM; Described two-port RAM, as buffer memory medium, is connected with two pieces of circuit boards respectively.
3. two circuit board parallel communication systems according to claim 2, is characterized in that: described data bus and address bus adopt 16 BITBUS network.
4. two circuit board parallel communication systems according to claim 3, is characterized in that: two pieces of circuit boards are all the logic control circuit plates based on fpga chip.
5. two circuit board parallel communication methods, is characterized in that: comprise the following steps:
1] two pieces of circuit board PWM1G and PWM2G are realized interconnection by 16 bit data bus and 16 bit address buses;
2] arranging PWM1G is master control board, controls the reading and writing data between two pieces of circuit boards; Arranging PWM2G is from equipment;
3] data write:
3.1] write control signal is set to effectively by PWM1G;
3.2] PWM1G is to the two-port RAM write data being positioned at PWM2G inside;
3.3] PWM1G write control signal is set to invalid;
4] digital independent:
4.1] read control signal is set to effectively by PWM1G;
4.2] PWM1G reads data from the two-port RAM being positioned at PWM2G inside;
4.3] PWM1G read control signal is set to invalid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510737575.6A CN105259840A (en) | 2015-11-02 | 2015-11-02 | Two-circuit board parallel communication system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510737575.6A CN105259840A (en) | 2015-11-02 | 2015-11-02 | Two-circuit board parallel communication system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105259840A true CN105259840A (en) | 2016-01-20 |
Family
ID=55099580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510737575.6A Pending CN105259840A (en) | 2015-11-02 | 2015-11-02 | Two-circuit board parallel communication system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105259840A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107291652A (en) * | 2017-07-05 | 2017-10-24 | 深圳市奈瑞特科学技术有限公司 | A kind of parallel communication method |
| CN108984441A (en) * | 2018-05-31 | 2018-12-11 | 烽火通信科技股份有限公司 | A kind of method and system keeping data transmission consistency |
| CN109188986A (en) * | 2018-10-25 | 2019-01-11 | 深圳易能电气技术股份有限公司 | Dual controller parallel bus communication device, method and communication apparatus |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1761856A1 (en) * | 2004-06-22 | 2007-03-14 | The General Electric Company | Computer system and method for queuing interrupt messages in a device coupled to a parallel communications bus |
| CN101414291A (en) * | 2007-10-17 | 2009-04-22 | 株洲南车时代电气股份有限公司 | Master-salve distributed system and parallel communication method applying the same |
| US20110196997A1 (en) * | 2010-02-11 | 2011-08-11 | Ruberg Alan T | Hybrid interface for serial and parallel communication |
| CN102999467A (en) * | 2012-12-24 | 2013-03-27 | 中国科学院半导体研究所 | High-speed interface and low-speed interface switching circuit and method based on FPGA (Field Programmable Gate Array) |
| CN203812236U (en) * | 2013-11-29 | 2014-09-03 | 力博特公司 | Data exchange system based on processor and field programmable gate array |
| CN205318144U (en) * | 2015-11-02 | 2016-06-15 | 日立永济电气设备（西安）有限公司 | Two circuit board parallel communication systems |
-
2015
- 2015-11-02 CN CN201510737575.6A patent/CN105259840A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1761856A1 (en) * | 2004-06-22 | 2007-03-14 | The General Electric Company | Computer system and method for queuing interrupt messages in a device coupled to a parallel communications bus |
| CN101414291A (en) * | 2007-10-17 | 2009-04-22 | 株洲南车时代电气股份有限公司 | Master-salve distributed system and parallel communication method applying the same |
| US20110196997A1 (en) * | 2010-02-11 | 2011-08-11 | Ruberg Alan T | Hybrid interface for serial and parallel communication |
| CN102999467A (en) * | 2012-12-24 | 2013-03-27 | 中国科学院半导体研究所 | High-speed interface and low-speed interface switching circuit and method based on FPGA (Field Programmable Gate Array) |
| CN203812236U (en) * | 2013-11-29 | 2014-09-03 | 力博特公司 | Data exchange system based on processor and field programmable gate array |
| CN205318144U (en) * | 2015-11-02 | 2016-06-15 | 日立永济电气设备（西安）有限公司 | Two circuit board parallel communication systems |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107291652A (en) * | 2017-07-05 | 2017-10-24 | 深圳市奈瑞特科学技术有限公司 | A kind of parallel communication method |
| CN107291652B (en) * | 2017-07-05 | 2020-06-09 | 深圳市奈瑞特科学技术有限公司 | Parallel communication method |
| CN108984441A (en) * | 2018-05-31 | 2018-12-11 | 烽火通信科技股份有限公司 | A kind of method and system keeping data transmission consistency |
| CN109188986A (en) * | 2018-10-25 | 2019-01-11 | 深圳易能电气技术股份有限公司 | Dual controller parallel bus communication device, method and communication apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104579885A (en) | Protocol converter and conversion method of CPCI bus and ISA bus | |
| CN104021107A (en) | Design method for system supporting non-volatile memory express peripheral component interface express solid state disc (NVMe PCIE SSD) | |
| CN105335548B (en) | A kind of MCU emulation mode for ICE | |
| CN204028898U (en) | The server of a kind of hard disk, any mixed insertion of compatible multiple solid state hard disc | |
| CN105208034A (en) | SPI bus and CAN bus protocol converting circuit and method | |
| CN105259840A (en) | Two-circuit board parallel communication system and method | |
| CN104714907B (en) | A kind of pci bus is converted to ISA and APB bus design methods | |
| CN113835487B (en) | System and method for realizing memory pool expansion of high-density server | |
| CN203191885U (en) | Server main board based on double-circuit loongson 3B CPU | |
| CN101650701B (en) | Converting device from parallel bus to RapidIO high-speed serial bus | |
| CN107943733A (en) | The interconnected method of parallel bus between a kind of veneer | |
| CN103514074A (en) | MVB network card development method and platform | |
| CN205318144U (en) | Two circuit board parallel communication systems | |
| CN205230035U (en) | PCIEBox integrated circuit board based on high -end server | |
| CN109407574A (en) | Output-controlling device and its method may be selected in a kind of multibus | |
| CN204374865U (en) | Reinforce server | |
| CN219574799U (en) | Multi-bus bridge based on AMBA bus and system on chip thereof | |
| CN102780598B (en) | A kind of bus communication, bus communication unit and system | |
| CN103279442A (en) | Message filtering system and message filtering method of high-speed interconnection bus | |
| CN107102965A (en) | A kind of data processing circuit, system and data processing method | |
| CN204406395U (en) | A kind of high speed communication interacted system of CPCI framework | |
| CN202617157U (en) | PCI express (PCIE) switched circuit | |
| CN105005233B (en) | Pulse power real-time control system based on Reflective memory network and dsp controller | |
| CN104598420A (en) | SoC chip architecture of 1394 bus | |
| CN107102961A (en) | Accelerate the method and system of arm processor concurrent working |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 710018 Shaanxi city of Xi'an Province Economic and Technological Development Zone Wenjing Road No. 15 Applicant after: Xi'an Zhongche InfoQuick Yongji Electric Co. Ltd. Address before: 710018 Shaanxi city of Xi'an Province Economic and Technological Development Zone Wenjing Road No. 15 Applicant before: HITACHI YONGE ELECTRIC EQUIPMENT(XI'AN) CO., LTD. |
|
| COR | Change of bibliographic data | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160120 |
|
| RJ01 | Rejection of invention patent application after publication |