CN105226926A - Method for solving MOS damage caused by too fast VR load change - Google Patents
Method for solving MOS damage caused by too fast VR load change Download PDFInfo
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- CN105226926A CN105226926A CN201510605872.5A CN201510605872A CN105226926A CN 105226926 A CN105226926 A CN 105226926A CN 201510605872 A CN201510605872 A CN 201510605872A CN 105226926 A CN105226926 A CN 105226926A
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Abstract
The invention discloses a method for solving MOS damage caused by too fast VR load change, which comprises the following concrete implementation processes: in the power supply conversion chip of the server mainboard, when the load change rate is too fast, the internal coupling interference of the power supply conversion chip is reduced, the wrong reception of the chip on a feedback signal is avoided, an internal logic error occurs, the normal work of the MOS in the conversion process is ensured, and the output voltage is in a normal application range. Compared with the prior art, the method for solving the problem that the MOS is damaged due to too fast VR load change aims at the problem that the MOS is burnt out due to too fast load change of a server mainboard under different configurations or different working modes, and ensures that a product does not have faults in the working process and the normal work is influenced; meanwhile, the method is also applied to improving the working stability of various server circuit board cards, and is high in practicability and easy to popularize.
Description
Technical field
The present invention relates to computer server technical field, specifically a kind of practical, solve the method that VR load variations causes MOS to damage too soon.
Background technology
When the design being engaged in server, we can find that the voltage transitions of large-scale server master board design is a lot.Comprise: power on start before, normal boot-strap run and system closedown after.For any one state, usually, in the process of design, all can have different change-over circuits, not only energy-conservation but also can the maximization of guaranteed efficiency, also preventing board be stuck in the course of work and occurs uncertain factor, causes damage to board.And the VR(VoltageRegulator on our mainboard, that is: electric pressure converter), can along with the difference of application demand after normal boot-strap runs, there is the load variations of different rates, MOS switching frequency in voltage transitions process also changes thereupon, load larger MOS switching frequency is higher, and load less MOS switching frequency is lower.
Mainboard VR is under different loads state, and its power supply conversion performance depends primarily on power supply conversion chip and sends the pwm signal response speed and the stability of control MOS start signal that regulate MOS switching sequence.Wherein: the response speed of pwm signal depends on the response time that chip itself sets, MOS start signal stability is then easily subject to external signal interference.
General circuit board of server all can be arranged in pairs or groups fixing configuration, but do not get rid of the reason of other board due to mechanism, Power Management Design, space, application demand etc., do not adopt the configuration that collocation is fixing, accurately cannot estimate the maximum rate of change of load in practical application.
If mainboard Inhaul operation program is too much, data volume is comparatively large, and load variations is too fast, then the MOS switching frequency conversion of changing voltage can be very fast.Due to the effect of outputting inductance, the faster PHASE voltage produced after upper MOS opens of MOS switching frequency will be higher, and the coupled interference that chip internal GND produces also will be larger; When the coupled interference on GND reaches about about 2.5V, the feedback voltage that just likely chip internal can be caused to read occurs abnormal, causes logic error.Thus, cause the situation occurring upper and lower two MOS conducting simultaneously, occur that short circuit burns out MOS.
In order to prevent the generation of this situation, proposing the method for designing that a kind of VR of solution load variations causes MOS to damage too soon herein, by increasing resistance between PHASE and GND, for filtering, reducing coupled interference.
Summary of the invention
Technical assignment of the present invention is for above weak point, provide a kind of practical, solve the method that VR load variations causes MOS to damage too soon.
Solve the method that VR load variations causes MOS to damage too soon, its specific design process is:
In the power supply conversion chip of server master board, when load variations speed is too fast, by reducing the interference of power supply conversion chip inner couplings, avoid chip to the garbled-reception of feedback signal, there is internal logic mistake, guarantee that in transfer process, MOS normally works, output voltage is in normal area of application.
In the power supply conversion chip of server master board, its voltage conversion circuit comprises the signal controller of input pwm signal, and the switching signal of this signal controller control connection two MOS is voltage-phase PHASE signal output part at the output of this signal controller; Wherein:
Pwm signal controls the switching signal of upper and lower MOS by the integration of signal controller, that is: when PWM is high level, upper MOS switching signal is high level, and lower MOS switching signal is low level, and upper MOS opens lower MOS and closes; When PWM is low level, upper MOS switching signal is low level, and lower MOS switching signal is high level, and upper MOS closes lower MOS and opens;
Voltage-phase PHASE increases a resistance be used for reducing the coupled interference produced, output, the output head grounding of the input connection signal controller of this resistance.
Resistance >=the 10kohm of described resistance, and this resistor power computing formula is: P=U2/R, wherein: 0V≤U < 25V.
The method that a kind of VR of solution load variations of the present invention causes MOS to damage too soon, has the following advantages:
The method that a kind of VR of solution load variations that the present invention proposes causes MOS to damage too soon, for server master board, under the different configuration of collocation or different working modes, load variations is too fast causes the problem burning out MOS, ensure that product there will not be fault in the course of the work, impact normally works; Meanwhile, the job stability improving all kinds of server circuit board is also applied to; By reducing the coupled interference of conversion chip GND, and then ensure that conversion chip normally works, output normal signal controls upper and lower MOS and opens and closes, and guarantees output voltage stabilization; Ensure that server master board is in the different configuration of collocation or large in calculation process amount, under running the application scenarios of the high requirement such as reaction speed is fast, application solutions server master board normally works; Only need increase a resistance in one group of voltage transitions circuit, user can arrange in pairs or groups different configuration according to the demand of oneself on server master board, safe operation data processing, expand range of application, meet consumers' demand to a greater extent, reduce R&D costs, practical, be easy to promote.
Accompanying drawing explanation
Accompanying drawing 1 controls upper and lower MOS switching circuit figure for improving front PWM.
For there is unusual waveforms figure when load variations is too fast before improvement in accompanying drawing 2.
Accompanying drawing 3 controls upper and lower MOS switching circuit figure for improving rear PWM.
Unusual waveforms figure is there is in accompanying drawing 4 for improving when back loading changes too fast.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
The invention provides a kind of method that the VR of solution load variations causes MOS to damage too soon, break original server collocation fixed configurations, supported data treating capacity is larger widely, load variations speed design concept faster.And adopting new idea: no matter server master board arranges in pairs or groups the network interface card of which kind of type, hard disk etc., and server master board can be supported, no longer causes crashing by the too fast impact of the load variations speed in mass data processing procedure.Such server master board application wider (requiring lower than the server master board of collocation fixed configurations), meets the application demand of different user to a greater extent.
Its specific implementation process is:
In the power supply conversion chip of server master board, when load variations speed is too fast, by reducing the interference of power supply conversion chip inner couplings, avoid chip to the garbled-reception of feedback signal, there is internal logic mistake, guarantee that in transfer process, MOS normally works, output voltage is in normal area of application.
In the power supply conversion chip of server master board, its voltage conversion circuit comprises the signal controller of input pwm signal, and the switching signal of this signal controller control connection two MOS is voltage-phase PHASE signal output part at the output of this signal controller; Wherein:
Pwm signal controls the switching signal of upper and lower MOS by the integration of signal controller, that is: when PWM is high level, upper MOS switching signal is high level, and lower MOS switching signal is low level, and upper MOS opens lower MOS and closes; When PWM is low level, upper MOS switching signal is low level, and lower MOS switching signal is high level, and upper MOS closes lower MOS and opens;
Voltage-phase PHASE increases a resistance be used for reducing the coupled interference produced, output, the output head grounding of the input connection signal controller of this resistance.
Resistance >=the 10kohm of described resistance, and this resistor power computing formula is: P=U2/R, wherein: 0V≤U < 25V.
Figure 1 shows that in server master board voltage transitions process, PWM controls upper and lower MOS switch junctions composition.When output loading change in rear end is too fast, the frequency change of pwm signal also can accelerate, and the switching frequency change of upper and lower MOS switch also accelerates, and corresponding coupled interference also becomes large.
Figure 2 shows that server master board is when load variations is too fast, cause that GND coupled interference is excessive has occurred control chip erroneous judgement, cause logic error to make upper and lower MOS conducting simultaneously.Now, input voltage is directly connected to GND by upper and lower two MOS, produces big current and has burnt out MOS.
When being operated under the comparatively large more complicated loading condition of operand according to the different configuration of server master board collocation or server, find to there will be system automatic shutdown and the phenomenon burning out MOS; By with electronics load meter to server master board take out carry, fictitious load changes mode of operation check waveform faster, as shown in Figure 2, load is under very heavy and very light two kinds of sights in rapid handoff procedure, the coupled interference that chip GND produces is larger, cause chip erroneous judgement, and occur the situation of upper and lower MOS conducting simultaneously.
Fig. 3 is the line map that after improving, PWM controls upper and lower MOS switch, PHASE increases a resistance be used for reducing the coupled interference produced, conversion chip can normally be worked, output normal signal controls upper and lower MOS and opens and closes, guarantee output voltage stabilization, this resistor power is 0.0625W.
Fig. 4 is for improving rear server master board when load variations is too fast, and because GND coupled interference is less, conversion chip normally works, waveform stabilization.
Finally, according to the structure complete design schematic diagram of Fig. 3, even if server master board also can be allowed in the fast-changing situation of load normally to work, as still normal in Fig. 4 server master board waveform when load accelerates fast.
Like this, the method for designing that a kind of VR of solution load variations in this paper causes MOS to damage too soon can be achieved.By reducing the coupled interference of conversion chip GND, can realize at server master board large in calculation process amount, under the application scenarios of the high requirement such as operation reaction speed is fast, application solutions server master board normally works, and occurring that high capacity runs lower deadlock and burns out the problem of MOS before solving.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; claims of the method that any a kind of VR of solution load variations according to the invention causes MOS to damage too soon and the those of ordinary skill of any described technical field to its suitable change done or replacement, all should fall into scope of patent protection of the present invention.
Claims (3)
1. solve the method that VR load variations causes MOS to damage too soon, it is characterized in that, its specific design process is:
In the power supply conversion chip of server master board, when load variations speed is too fast, by reducing the interference of power supply conversion chip inner couplings, avoid chip to the garbled-reception of feedback signal, there is internal logic mistake, guarantee that in transfer process, MOS normally works, output voltage is in normal area of application.
2. a kind of VR of solution load variations according to claim 1 method of causing MOS to damage too soon, it is characterized in that, in the power supply conversion chip of server master board, its voltage conversion circuit comprises the signal controller of input pwm signal, the switching signal of this signal controller control connection two MOS is voltage-phase PHASE signal output part at the output of this signal controller; Wherein:
Pwm signal controls the switching signal of upper and lower MOS by the integration of signal controller, that is: when PWM is high level, upper MOS switching signal is high level, and lower MOS switching signal is low level, and upper MOS opens lower MOS and closes; When PWM is low level, upper MOS switching signal is low level, and lower MOS switching signal is high level, and upper MOS closes lower MOS and opens;
Voltage-phase PHASE increases a resistance be used for reducing the coupled interference produced, output, the output head grounding of the input connection signal controller of this resistance.
3. a kind of VR of solution load variations according to claim 2 method of causing MOS to damage too soon, it is characterized in that, the resistance >=10kohm of described resistance, and this resistor power computing formula is: P=U2/R, wherein: 0V≤U < 25V.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510605872.5A CN105226926A (en) | 2015-09-22 | 2015-09-22 | Method for solving MOS damage caused by too fast VR load change |
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| CN201510605872.5A CN105226926A (en) | 2015-09-22 | 2015-09-22 | Method for solving MOS damage caused by too fast VR load change |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI676342B (en) * | 2018-11-29 | 2019-11-01 | 致茂電子股份有限公司 | Half-bridge circuit assembly and switch mode power supply |
| CN111245230A (en) * | 2018-11-29 | 2020-06-05 | 致茂电子(苏州)有限公司 | Half-bridge circuit assembly and switching type power supply |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727158A (en) * | 2008-10-16 | 2010-06-09 | 鸿富锦精密工业（深圳）有限公司 | Mainboard supply circuit |
| TW201025805A (en) * | 2008-12-22 | 2010-07-01 | Asustek Comp Inc | Switching power supply applied and computer system |
| US20110051479A1 (en) * | 2009-08-27 | 2011-03-03 | Dell Products L.P. | Systems and Methods for Controlling Phases of Multiphase Voltage Regulators |
| CN202041907U (en) * | 2011-05-16 | 2011-11-16 | 厦门玛司特电子工业有限公司 | Computer power supply |
| CN102591438A (en) * | 2011-01-13 | 2012-07-18 | 鸿富锦精密工业（深圳）有限公司 | Power supply circuit for central processing unit |
-
2015
- 2015-09-22 CN CN201510605872.5A patent/CN105226926A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727158A (en) * | 2008-10-16 | 2010-06-09 | 鸿富锦精密工业（深圳）有限公司 | Mainboard supply circuit |
| TW201025805A (en) * | 2008-12-22 | 2010-07-01 | Asustek Comp Inc | Switching power supply applied and computer system |
| US20110051479A1 (en) * | 2009-08-27 | 2011-03-03 | Dell Products L.P. | Systems and Methods for Controlling Phases of Multiphase Voltage Regulators |
| CN102591438A (en) * | 2011-01-13 | 2012-07-18 | 鸿富锦精密工业（深圳）有限公司 | Power supply circuit for central processing unit |
| CN202041907U (en) * | 2011-05-16 | 2011-11-16 | 厦门玛司特电子工业有限公司 | Computer power supply |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI676342B (en) * | 2018-11-29 | 2019-11-01 | 致茂電子股份有限公司 | Half-bridge circuit assembly and switch mode power supply |
| CN111245230A (en) * | 2018-11-29 | 2020-06-05 | 致茂电子(苏州)有限公司 | Half-bridge circuit assembly and switching type power supply |
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